JPS6444056A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS6444056A
JPS6444056A JP62201098A JP20109887A JPS6444056A JP S6444056 A JPS6444056 A JP S6444056A JP 62201098 A JP62201098 A JP 62201098A JP 20109887 A JP20109887 A JP 20109887A JP S6444056 A JPS6444056 A JP S6444056A
Authority
JP
Japan
Prior art keywords
circuit
hybrid integrated
integrated circuit
substrates
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62201098A
Other languages
Japanese (ja)
Inventor
Naoharu Senba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62201098A priority Critical patent/JPS6444056A/en
Publication of JPS6444056A publication Critical patent/JPS6444056A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To effectively utilize a space by providing a circuit substrate on the upper face or the bottom of a transfer molded package, and forming a hybrid integrated circuit. CONSTITUTION:A circuit substrate 4 is bonded to a lead frame 1, an active element 5 and a passive element 6 are placed, connected by metal fine wirings 2 to form a circuit. A sheathing resin 3 is performed by a transfer molding method. In this case, circuit substrates 7, 8 are simultaneously integrally formed on the upper face and the bottom of the resin 3. Then, an adhesive is adhered to the substrates 7, 8 by a printing method or a dispensing method, etc., a passive element 10 and an active element 9 are bonded to the substrates 7, 8 by dipping in solder bath, or by other method to form a circuit, thereby manufacturing a hybrid integrated circuit device. Thus, a space can be effectively utilized to enhance a mounting density.
JP62201098A 1987-08-11 1987-08-11 Hybrid integrated circuit Pending JPS6444056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62201098A JPS6444056A (en) 1987-08-11 1987-08-11 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62201098A JPS6444056A (en) 1987-08-11 1987-08-11 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6444056A true JPS6444056A (en) 1989-02-16

Family

ID=16435362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62201098A Pending JPS6444056A (en) 1987-08-11 1987-08-11 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6444056A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0665584A1 (en) * 1994-01-27 1995-08-02 " 3P" Licensing B.V. Method for encasing an electronic component with a hardening plastic, electronic components with plastic encasement obtained by this method, and mould for carrying out the method
US5444296A (en) * 1993-11-22 1995-08-22 Sun Microsystems, Inc. Ball grid array packages for high speed applications
US5638408A (en) * 1994-11-14 1997-06-10 Nec Corporation Variable transmission bit rate discrimination method and apparatus
US6343105B1 (en) 1997-06-10 2002-01-29 Nec Corporation Viterbi decoder
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6217153B2 (en) * 1982-04-28 1987-04-16 Iseki Agricult Mach
JPS6232553B2 (en) * 1976-07-26 1987-07-15 Fuji Photo Film Co Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6232553B2 (en) * 1976-07-26 1987-07-15 Fuji Photo Film Co Ltd
JPS6217153B2 (en) * 1982-04-28 1987-04-16 Iseki Agricult Mach

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444296A (en) * 1993-11-22 1995-08-22 Sun Microsystems, Inc. Ball grid array packages for high speed applications
EP0665584A1 (en) * 1994-01-27 1995-08-02 " 3P" Licensing B.V. Method for encasing an electronic component with a hardening plastic, electronic components with plastic encasement obtained by this method, and mould for carrying out the method
NL9400119A (en) * 1994-01-27 1995-09-01 3P Licensing Bv Method for encapsulating an electronic component with a hardening plastic, electronic components with plastic enclosure obtained by means of this method and mold for carrying out the method.
US5638408A (en) * 1994-11-14 1997-06-10 Nec Corporation Variable transmission bit rate discrimination method and apparatus
US6343105B1 (en) 1997-06-10 2002-01-29 Nec Corporation Viterbi decoder
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate

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