JPS642399A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS642399A JPS642399A JP62158578A JP15857887A JPS642399A JP S642399 A JPS642399 A JP S642399A JP 62158578 A JP62158578 A JP 62158578A JP 15857887 A JP15857887 A JP 15857887A JP S642399 A JPS642399 A JP S642399A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- cap
- metallic layer
- holes
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE: To obtain a positive magnetic shielding effect by previously bringing lead pins set up around a semiconductor element into contact with a metallic layer formed onto the surface of a substrate made of plastics and a cap made of a metal when the element is mounted onto the rear of the substrate and the rear of the substrate including the element is covered with the cap through a sealing resin frame.
CONSTITUTION: A recessed section is shaped to the rear of a substrate 1 made of plastics, a semiconductor element 8 is buried into the recessed section, and terminals fitted to the semiconductor element 8 are connected to a metallic layer surrounding the element 8 by using bonding wires 9. The whole rear including the element 8 is hermetically sealed with a cap 5 made of a metal through a resin sealing frame 6, through-holes 11 are bored penetrated through the metallic layer 2 applied onto the surface of the substrate 1 and the cap 5, lead pins 3 are inserted into the through-holes 11 while being protruded from the rear of the substrate 1, and fixed to a metallic layer 12 on the rear of the cap 5 by employing solder 4, and the pins 3 are connected to a power supply. Accordingly, the metallic layers are shaped onto the surface and rear of the substrate 1 and connected by the lead pins 3 through the through-holes 11, thus completing electromagnetic shielding to the element 8.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62158578A JPH0775279B2 (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62158578A JPH0775279B2 (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JPH012399A JPH012399A (en) | 1989-01-06 |
JPS642399A true JPS642399A (en) | 1989-01-06 |
JPH0775279B2 JPH0775279B2 (en) | 1995-08-09 |
Family
ID=15674750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62158578A Expired - Lifetime JPH0775279B2 (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0775279B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5323533A (en) * | 1991-03-26 | 1994-06-28 | Thomson-Csf | Method of producing coaxial connections for an electronic component, and component package |
EP0667643A1 (en) * | 1994-01-20 | 1995-08-16 | Tokin Corporation | Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same |
US5923540A (en) * | 1993-11-30 | 1999-07-13 | Fujitsu Limited | Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power |
EP1089336A3 (en) * | 1999-09-22 | 2005-07-20 | Lucent Technologies Inc. | Integrated circuit packages with improved EMI characteristics |
JP2008026079A (en) * | 2006-07-19 | 2008-02-07 | Matsushita Electric Works Ltd | Infrared detector and its manufacturing method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59186397A (en) * | 1983-04-06 | 1984-10-23 | 三菱電機株式会社 | Hybrid integrated circuit |
-
1987
- 1987-06-25 JP JP62158578A patent/JPH0775279B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59186397A (en) * | 1983-04-06 | 1984-10-23 | 三菱電機株式会社 | Hybrid integrated circuit |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5323533A (en) * | 1991-03-26 | 1994-06-28 | Thomson-Csf | Method of producing coaxial connections for an electronic component, and component package |
US5923540A (en) * | 1993-11-30 | 1999-07-13 | Fujitsu Limited | Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power |
EP0667643A1 (en) * | 1994-01-20 | 1995-08-16 | Tokin Corporation | Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same |
US5864088A (en) * | 1994-01-20 | 1999-01-26 | Tokin Corporation | Electronic device having the electromagnetic interference suppressing body |
US6448491B1 (en) | 1994-01-20 | 2002-09-10 | Tokin Corporation | Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same |
EP1089336A3 (en) * | 1999-09-22 | 2005-07-20 | Lucent Technologies Inc. | Integrated circuit packages with improved EMI characteristics |
JP2008026079A (en) * | 2006-07-19 | 2008-02-07 | Matsushita Electric Works Ltd | Infrared detector and its manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
JPH0775279B2 (en) | 1995-08-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |