JPS6421945A - Electronic element mounting module - Google Patents

Electronic element mounting module

Info

Publication number
JPS6421945A
JPS6421945A JP62177532A JP17753287A JPS6421945A JP S6421945 A JPS6421945 A JP S6421945A JP 62177532 A JP62177532 A JP 62177532A JP 17753287 A JP17753287 A JP 17753287A JP S6421945 A JPS6421945 A JP S6421945A
Authority
JP
Japan
Prior art keywords
chip carrier
cap
electronic element
fitted
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62177532A
Other languages
Japanese (ja)
Inventor
Yoshitaka Fukuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62177532A priority Critical patent/JPS6421945A/en
Publication of JPS6421945A publication Critical patent/JPS6421945A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To obtain the title module which can be made small in size by a method wherein a step-formed cap, on which a chip carrier can be fitted to the inner wall surface, covers an electronic element-mounted chip carrier having a metallized side face, and the part between the chip carrier and the cap is sealed with solder. CONSTITUTION:A cap 12, having a step on which a chip carrier 14 can be fitted to the inner wall surface, is covered on the chip carrier 14, at least having the metallized side face and also carrying an electronic element 13, in such a manner that the chip carrier 14 is fitted to the stepped part, and the region between the chip carrier 14 and the cap 12 is sealed with solder 16. For example, a through hole 11 for sealing of gas is formed on the above-mentioned cap 12. Also, on the surface of the above-mentioned chip carrier 14, a bonding pad 17 for mounting of the electronic element 13 and a bonding pad 18 for the bonding wire 19 used to connect the electron element 13 and the chip carrier 14 are provided, and an input-output conductive pad 21, which is connected to each pad 18 on the surface for formation of a specific electric circuit, is arranged and formed on the rear side of the chip carrier 14.
JP62177532A 1987-07-16 1987-07-16 Electronic element mounting module Pending JPS6421945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62177532A JPS6421945A (en) 1987-07-16 1987-07-16 Electronic element mounting module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62177532A JPS6421945A (en) 1987-07-16 1987-07-16 Electronic element mounting module

Publications (1)

Publication Number Publication Date
JPS6421945A true JPS6421945A (en) 1989-01-25

Family

ID=16032576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62177532A Pending JPS6421945A (en) 1987-07-16 1987-07-16 Electronic element mounting module

Country Status (1)

Country Link
JP (1) JPS6421945A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840055A (en) * 1981-08-28 1983-03-08 Satake Eng Co Ltd Device for processing and treating rice grain
GB2477492A (en) * 2010-01-27 2011-08-10 Thales Holdings Uk Plc Hermetically sealed integrated circuit package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262545A (en) * 1985-09-12 1987-03-19 Nec Corp Chip carrier and manufacture thereof
JPS62105449A (en) * 1985-10-31 1987-05-15 Toshiba Corp Hybrid integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262545A (en) * 1985-09-12 1987-03-19 Nec Corp Chip carrier and manufacture thereof
JPS62105449A (en) * 1985-10-31 1987-05-15 Toshiba Corp Hybrid integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840055A (en) * 1981-08-28 1983-03-08 Satake Eng Co Ltd Device for processing and treating rice grain
GB2477492A (en) * 2010-01-27 2011-08-10 Thales Holdings Uk Plc Hermetically sealed integrated circuit package
US8383462B2 (en) 2010-01-27 2013-02-26 Thales Holdings Uk Plc Method of fabricating an integrated circuit package

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