CN1744304A - 使用电极气密密封的高可靠性半导体装置 - Google Patents

使用电极气密密封的高可靠性半导体装置 Download PDF

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Publication number
CN1744304A
CN1744304A CNA2005100976217A CN200510097621A CN1744304A CN 1744304 A CN1744304 A CN 1744304A CN A2005100976217 A CNA2005100976217 A CN A2005100976217A CN 200510097621 A CN200510097621 A CN 200510097621A CN 1744304 A CN1744304 A CN 1744304A
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China
Prior art keywords
substrate
electrode
electrodes
semiconductor device
frame structure
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CNA2005100976217A
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CN100401504C (zh
Inventor
须贺唯知
伊藤寿浩
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Yorozu Yuchi
Toshiba Corp
NEC Corp
Sharp Corp
Sanyo Electric Co Ltd
Sony Corp
Fujitsu Semiconductor Ltd
Renesas Electronics Corp
Lapis Semiconductor Co Ltd
Panasonic Holdings Corp
Original Assignee
Renesas Technology Corp
Toshiba Corp
Fujitsu Ltd
NEC Corp
Oki Electric Industry Co Ltd
Sharp Corp
Sanyo Electric Co Ltd
Sony Corp
Matsushita Electric Industrial Co Ltd
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Application filed by Renesas Technology Corp, Toshiba Corp, Fujitsu Ltd, NEC Corp, Oki Electric Industry Co Ltd, Sharp Corp, Sanyo Electric Co Ltd, Sony Corp, Matsushita Electric Industrial Co Ltd filed Critical Renesas Technology Corp
Publication of CN1744304A publication Critical patent/CN1744304A/zh
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Publication of CN100401504C publication Critical patent/CN100401504C/zh
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

本发明涉及一种具有高可靠性的半导体装置，该装置不使用密封材料，而通过框架结构密封形成于基板上的电极以防止电极的劣化。本发明的框架结构密封形成于基板上的电极。框架结构内部为真空或者填充不与电极发生反应的气体，由此防止因氧气或水分而引起电极的劣化。

Description

使用电极气密密封的高可靠性半导体装置
                      技术领域
本发明涉及一种具有高可靠性的半导体装置，其不使用密封材料而通过框架结构密封形成于基板上的电极，从而防止电极的劣化。
                      背景技术
以往，在布线基板上安装半导体芯片来制作半导体装置时，使用在半导体芯片上的接合焊盘和布线基板上的引线间以金属细线连接而形成电连接的引线键合技术，但是近年来，为了应对针对电子设备的小型化和轻量化的要求以及半导体元件连接端子数的增大，就采用了倒装芯片安装技术，该技术在半导体芯片表面的电极上形成突起电极(以下称为突起(bump))，通过面朝下方式直接安装在布线基板上。
在该倒装芯片安装技术中，使用焊料或Au等金属材料在半导体芯片上所形成的多个电极上形成突起，在将这些多个突起与布线基板上所形成的对应的多个电极配合定位后进行加热压接。为了提高半导体装置的可靠性，在半导体芯片和布线基板之间，供给底部填充胶(underfill)材料，该底部填充胶材料作为用于保护电极不受诸如氧气或水分的氧化等来自周围环境的不良影响的密封树脂而起作用，此外，作为防止在加热压接后的冷却时由半导体芯片与布线基板间的热膨胀率差而产生的热应力导致破坏突起的热应力缓冲材料而起作用。
作为底部填充胶材料的供给方法，有如下方法：在将形成了突起的半导体芯片加热压接于布线基板上后，将液态树脂填充于半导体芯片和布线基板之间的方法；以及在先将液态树脂或树脂薄膜供给基板之后，再将半导体芯片接合于布线基板上的方法。
然而哪一种方法都需要供给底部填充胶材料的工序，因为还有底部填充胶材料的保管和使用期限的制约，所以存在作业效率低下和成本上升等问题。
另外，从如何降低环境负荷的观点出发，从电子设备中的接合了安装基板等多个部件的制品中分解回收部件从而进行再利用正成为一个课题，对于使用底部填充胶材料的情况，在分解时，底部填充胶材料的去除是个困难。
进而，伴随着半导体装置的薄型化，半导体芯片与布线基板间的间隔变小，随着形成于基板上的布线间的窄间距化的进展，在布线间充分地填充树脂就变得很困难。
因此，需要研究出如下的装置：不使用底部填充胶材料那样的树脂，就能够防止半导体芯片以及布线基板上电极的劣化，并缓冲半导体芯片与布线基板之间的热应力，从而确保半导体装置的可靠性。
作为不使用底部填充胶材料而缓冲具有突起的半导体芯片与布线基板间的热应力的装置，例如专利第3116926号说明书(专利文献1)中公开了在形成于半导体芯片上的突起的周围下部设置低弹性层以缓冲热应力的结构。
此外，也进行付与突起自身以弹性来缓冲热应力的研究。例如特开平11-214447号公报(专利文献2)和特开2001-156091号公报(专利文献3)中公开了通过在焊料突起内部形成空隙来缓冲热应力的结构。特开平11-233669号公报(专利文献4)中公开了形成对由聚酰亚胺或丙烯等感光树脂构成的芯体施加了镀镍的突起，并利用树脂的弹性来缓冲热应力的结构。特开2000-320148号公报(专利文献5)中公开了在焊料接合部使用U字型的弹性部件来缓冲产生于集成电路与安装基板间的热应力的结构。
进而，在小于10μm间距的微细接合中，突起连接变得困难，此外，当接合部上存在不同种类的材料时，通过在接合时的扩散反应而导致接合部材质变化从而无法确保可靠性，因此产生出下述需要：采用从接合部排除不同种类材料而使形成于半导体芯片上的电极与形成于布线基板上的电极直接接触的无突起结构。
在接合相同材质的基板彼此时(例如，在接合Si芯片彼此时或者将Si芯片向Si内插板(interposer)基板安装时)，不需要考虑热应力的产生，但是，在接合不同材质的基板时(例如，在将Si芯片于向印刷布线基板的树脂基板安装时)，由于在无突起结构中通过两块基板双方的变形来缓冲接合部的应力，所以要使基板尽可能薄型化使基板自身具有弹性。
现在，厚度50μm的薄型Si晶片大量生产，进而，厚度30μm以下的晶片正在开发中。
然而，在上述现有技术中，虽然不使用底部填充胶材料也能够达成底部填充胶材料所具有的应力缓冲功能，但是却没有进行关于防止电极劣化的密封性能的研究。
进而，在电子技术领域，作为从关系到提高维修、再加工的成品率的短期观点出发的课题以及作为从关系到所谓的循环、再利用的循环经济社会中制造业的根本的长远观点出发的课题，可分离的安装技术的开发正日益受到重视，在现有的安装技术中，因为通过接合半导体芯片的电极与布线基板的电极来制作半导体装置，因此在从布线基板分离半导体芯片时电极破损从而难以对半导体芯片和布线基板进行再利用。
                      发明内容
因此，本发明的目的在于：提供一种半导体装置，其是在布线基板上安装了半导体芯片的半导体装置，不使用密封树脂，具有高可靠性，进而目的在于：提供一种在保持高可靠性的同时可以容易地分离半导体芯片和布线基板的半导体装置。
本发明提供一种半导体装置，该装置包含：形成有一个或多个电极的第1基板、形成有一个或多个电极的第2基板以及框架结构，
形成于第1基板上的一个或多个电极的每个与形成于第2基板上的对应的一个或多个电极的每个电连接，
框架结构包围形成于第1和第2基板上的电极，由此气密密封这些电极，
经由框架结构接合第1基板和第2基板。
在本发明中，在第1基板和第2基板的组合中，包含有：Si基板-Si基板(半导体芯片彼此、半导体芯片和内插板)、Si基板-印刷布线基板(还包含柔性基板)、Si基板-化合物半导体基板(GaAs、InP等基板)、化合物半导体基板与印刷布线基板的组合等。在上述组合中，可以将任一基板作为第1基板。
在本发明的半导体装置中，该框架结构内部为真空，或者在其内部封入氮气或惰性气体或它们的混和物中的任一种。由此保护形成于半导体芯片和布线基板上的电极使其不受氧气、水分等影响而劣化，防止电连接的破坏。
本发明中所谓“真空”，是指低于大气压的压力状态。另外，作为“惰性气体”可列举出氩等稀有气体。
本发明的半导体装置其特征为：形成于第1基板上的一个或多个电极的每个与形成于第2基板上的对应的一个或多个电极的每个不被接合在一起，而是通过电极彼此的接触从而达成电连接。
进而，本发明的半导体装置其特征为：框架结构与第1基板和第2基板中至少一个基板可分离地接合着。
在本发明的半导体装置中，因为形成于半导体芯片上的电极与形成于布线基板上的电极不被接合在一起，而是通过电极彼此的接触来达成电连接，因此，只要经由框架结构将半导体芯片与布线基板可分离地接合，就能够容易不破损地分解电极，有利于进行半导体装置的维修和再利用等。
此外，如上所述，在本发明的半导体装置中，因为电极利用框架结构气密密封，因此，即使在半导体芯片的电极和布线基板的电极仅仅通过接触实现电连接的情况下，电极的接触部也不会由于氧气或水分而劣化，从而避免电连接破坏。
接合框架结构的方法，依赖于框架结构和接合框架结构的基板的材质，但是如果能够可分离地接合框架结构，则使用任何接合方法都可以。例如，可以通过焊料材料来接合框架结构。
这样，在从布线基板分离半导体芯片时电极不会破损，从而可以对上述布线基板和芯片进行再利用。
在本发明的半导体装置中，能够对形成于第1基板和第2基板上的电极的表面进行净化处理。
在本发明中，因为通过接触而达成电连接，所以为了降低接触电阻，去除接触表面上的氧化物和吸附的有机物等对接触表面进行净化是较有效的。
在要净化的接触表面上，通过在真空中照射等离子体、加速的离子束或高速原子束(FAB)或者原子团束或激光等的能量波，从而去除氧化物和有机物等。只要是能够在真空中将上述能量波照射在规定区域的装置则使用任意装置都能进行该净化处理。
本发明第1实施方式的半导体装置其特征为：形成于第1基板上的一个或多个电极的每个与形成于第2基板上的对应的一个或多个电极的每个经由具有弹性的突起电连接。
通常，当在基板上的电极上形成突起时，在突起的高度上产生偏差。在没有气密密封用的框架结构的现有半导体装置的情况下，为了通过将突起与对应的电极焊料接合从而达成电连接，可以通过焊料层的厚度吸收突起高度的偏差。
另一方面，本发明的半导体装置，因为将框架结构接合于基板，因此当在突起高度上有偏差时，就不能够确保充分的气密密封的同时达成突起与对应电极的电连接。然而，由于在框架结构与突起中图形不同，从而难以通过平坦化处理而使它们的高度一致。进而，即使能够在一个基板上使框架结构和突起的高度一致，但只要另一基板上的电极表面和与框架结构相对应的图形面的高度存在差异，就难以使框架结构与突起的高度一致达到理想的高度，难以达成充分的气密密封以及确实的电连接。
因此，在本发明第1实施方式的半导体装置中，使用具有弹性的突起，通过其弹性来吸收突起高度的偏差。
此外，根据本发明，当将框架结构接合于基板时，因为具有弹性的突起受到压缩而与对应的电极接触，即使不将突起接合到对应的电极上也能够达成电连接。此外，由于通过将框架结构接合于基板来构成半导体装置，所以即使不像现有的半导体装置那样将突起接合对应的电极上，也可以构成半导体装置。
在该第1实施方式中，上述具有弹性的突起的弹簧常数其特征为，例如是小于等于1000N/m这样的较小的值。因为突起的弹簧常数小，所以在将半导体芯片安装于布线基板上时当突起受到压缩时，由突起的反作用而加在形成于半导体芯片和布线基板上的电极上的应力减小，由此不会对形成于电极下部的布线层造成损伤，进一步提高了电极半导体装置的可靠性。
本发明第2实施方式的半导体装置其特征为，形成于第1基板上的一个或多个电极的每个与形成于第2基板的对应的一个或多个电极的每个通过无突起结构电连接。
当电极高密度化/微细化时，非常难以形成如在第1实施方式中使用的那样的突起。另外，为了防止因接合时的扩散反应而导致的材质变化以确保可靠性，优选从电极间排除不同种类材料。
因此，在本发明第2实施方式的半导体装置中，不使用突起而通过使电极彼此直接接触以达成电连接。
在该实施方式中，由于使用化学机械研磨等技术利用平坦化处理使框架结构与电极的高度一致，所以就能够在确保充分的气密密封的同时达成确实的电连接。
在该第2实施方式中，第1基板和第2基板的至少一个基板的厚度，或者第1基板和第2基板两者的基板厚度在50μm以下。
在第2实施方式中，与第1实施方式不同，因为形成于两个基板上的电极之间的接触部以无突起结构构成，所以因两个基板间的热膨胀系数差引起的热应力可以通过基板的变形来缓冲。因此为了确保半导体装置的可靠性，需要使基板尽可能薄型化。此外，由于使电极彼此直接接触，所以即使在电极高度有分布的情况下，则只要使基板薄型化从而基板自身变得具有弹性，就能够保证电极彼此的直接接触。
根据本发明，因为形成包围形成于半导体芯片和布线基板上的电极的框架结构，通过该框架结构气密密封电极，因此不使用密封树脂就可以防止电极的劣化，从而可以获得具有高可靠性的半导体装置。
进而，不接合电极彼此而仅通过电极间的接触来达成电连接，进而，因为将上述框架结构可分离地与基板接合，因此基板的分离变得容易，从而可以再利用。
                      附图说明
图1是在本发明半导体装置中使用的半导体芯片(a)和内插板(b)的俯视图。
图2是本发明第1实施方式的半导体装置安装工序的简要说明图。
图3是在本发明半导体装置中使用的具有弹性的突起的剖面图。
图4是构成本发明第2实施方式半导体装置的两个基板的剖面图。
                      具体实施方式
第1实施方式：
本发明第1实施方式的半导体装置其特征为：通过将第1基板安装在第2基板上来制作，形成于第1基板上的电极与形成于第2基板上的电极经由突起电连接。
作为具体例可以举出：将使用了Si基板的半导体芯片与使用了Si基板的内插板进行突起连接的半导体封装。
如图1(a)所示，使用通常的材料和方法，在半导体芯片1的Si基板10上，形成一个或多个电极11以及其它电路(未图示)。
如图1(b)所示，在内插板2的Si基板20上，形成一个或多个电极21以及其它电路(未图示)。进而，形成包围一个或多个电极21的框架结构23。
如图2所示，在一个或多个电极21的每个上分别接合具有弹性的突起22。因为形成于Si基板10上的多个电极11的配置与形成于Si基板20上的多个电极21的配置相对应，因此当将框架结构23与Si基板10接合从而将半导体芯片1安装于内插板2时，形成于Si基板10上的一个或多个电极11分别与形成于Si基板20上的对应的突起22的表面接触，达成电连接。
这里，所谓“对应的”，是指在将第1基板安装于第2基板时，位于形成于第1基板上的电极与形成于第2基板上的电极能够电连接的位置关系。
图3是形成于内插板2的一组电极和突起的剖面图。内插板2是通过如下来进行制作的：使用通常的材料和方法，在Si基板20上形成电极21以及其它电路，在用于电连接到电极21上的区域之外的区域上形成保护膜24。
虽然在电极21上能够直接形成突起22，但是优选在电极21上形成以防止电极21与突起22之间的组成物扩散和使粘接强度提高为目的的中间层25，并在其上形成突起22。
在现有方法中，具有弹性的突起例如是通过使用平版印刷技术在形成于基板的电极上进行层叠，或者是个别制作突起，通过使用现有的接合技术或者上述常温接合技术将其接合在形成于基板的电极上，从而在电极上形成突起。
此外，在本发明中，只要具有弹性则任意形状的突起都可以采用。例如可以采用图3(a)所示的弹簧突起221、图3(b)和(c)所示的树脂芯突起222和223，以及图3(d)所示的中空突起224等。
图3(a)作为1个具体例子，示出了一个具有曲柄形状的弹簧结构体的弹簧突起221，但也可以采用U字型和螺线形的弹簧结构体。图3(b)示出了树脂芯突起的一个具体例子，树脂芯突起222将树脂芯222a配置在电极21上，并于其上形成导电性覆盖膜222b从而可实现电连接。图3(c)示出了树脂芯突起的另一个具体例子。该树脂芯突起223具有多个树脂微球223a分散于导电体223b中的结构。图3(d)示出了中空突起的一个具体例子，该中空突起224具有在导电体的突起内部形成空腔的结构。
具体而言，在中间层25上，使用聚酰亚胺感光性树脂形成树脂芯222a，为了可以与电极21实现电连接，在树脂芯222a的周围通过镀镍而形成导电性覆盖膜222b，从而制成树脂芯突起222。
此外，框架结构23可以由Sn、Pb、Au或它们的合金、Cu或Ni等、通过电镀形成厚膜的材料来形成。此外，在框架结构形成后，还可以用易接合的材料来覆盖其表面。
框架结构23的接合可以采用加热接合、常温接合等技术适宜地进行。例如，在通过镀镍而形成的框架结构23的情况，可以通过附加焊料来接合到Si基板10上。
如图2所示，在将形成于Si基板20上的框架结构23接合到Si基板10时，调整框架结构23的高度，以使突起22的表面接触到形成于Si基板10上的电极11从而达成电连接。为此，例如，可以以电极11、突起22以及电极21的高度的总和略高于框架结构23的高度的方式设定。这样，在将半导体芯片1安装于内插板2时，突起22被压缩，突起22的表面接触基板上的电极从而达成电连接。
在通过现有技术将多个突起接合到基板上时，由于由偏差而产生的基板内的突起高度的最大差约为1μm，所以将半导体芯片安装于接合有多个突起的布线基板时，为了使多个突起全部接触到电极，就将最高的突起至少压缩1μm。这时，在使用现有的突起的情况下，由被压缩的突起的反作用而加在形成于半导体芯片和布线基板的每个电极焊盘的应力约为50gf，但随着半导体装置的小型化、薄型化的推进从而薄型化半导体芯片和布线基板的情况下，由于只要所述应力加在电极焊盘上就会引起半导体装置的故障，因此需要减小加在电极焊盘上的应力。
因此，在本发明中，多个突起以及框架结构高度的最大差值在1μm以内。即，在将半导体芯片1安装于内插板2时，最高的突起的最大压缩量为1μm。在此，在设定加在每个电极焊盘的最大容许压力例如为1gf的情况下，容许的突起的弹簧常数k则为1gf/1μm＝1000N/m。
即，在本发明中，优选突起的弹簧常数为1000N/m以下。
因为突起弹簧常数小，在将半导体芯片安装于布线基板而压缩突起时，由于减小了由突起的反作用而加在形成于半导体芯片和布线基板的电极上的应力，从而不会对形成于电极下部的布线层造成损伤，能够进一步提高半导体装置的可靠性。
当将框架结构23接合于Si基板10时，通过框架结构23气密密封形成于Si基板10和Si基板20上的电极，在框架结构内部形成空间30。空间30维持在真空，即低于大气压的压力状态。或者在空间30内，封入不与电极反应的例如氮气或氩等惰性气体或其混和物。
因为电极周围是真空或者是不与电极发生反应的气体环境，所以不会发生电极劣化而破坏电连接。
以这些突起22的表面分别接触到形成于Si基板10上的对应的多个电极11的方式进行定位后，通过将形成于Si基板20上的框架结构23接合到半导体芯片10上从而将半导体芯片1安装于内插板2，由此制作如图2所示的第1实施方式的半导体装置。
该实施方式中，在能够在真空中照射高速氩原子束的净化装置(未图示)中，通过照射高速氩原子束到Si基板10上的电极11的表面以及形成于Si基板20上的树脂芯突起222的表面从而去除表面上的氧化物和有机物等附着物，能够使这些表面净化。
由此，降低电极间的接触电阻。
在该实施方式中，可以在Si基板10上形成框架结构12，将该框架结构12接合于Si基板20，也可以将框架结构形成于Si基板10和Si基板20的双方的基板上，接合两个框架结构彼此。此外，也可以在形成于Si基板10上的电极11上形成具有弹性的突起12，通过使突起12与形成于Si基板20上的电极21相接触从而达成电连接。
第2实施方式：
本发明第2实施方式的半导体装置其特征为：通过将第1基板安装于第2基板来制作，形成于第1基板上的电极与形成于第2基板上的电极通过无突起结构电连接。
作为具体例子可以举出：将使用Si基板的半导体芯片与使用Si基板的内插板进行无突起连接的半导体封装。
如图4所示，使用通常的材料和方法，在半导体芯片1的Si基板10上，形成一个或多个电极11以及其它电路。更具体地说，在Si基板10上形成半导体元件的布线层16，并于其上形成绝缘层17。进而，在其之上形成以导电金属等构成的接地布线层18。
在绝缘层17和接地布线层18上，形成有到达布线层16的通孔，通过形成于该通孔内的连接布线，电极11与布线层16电连接。
另外，在接地布线层18上，形成有到达绝缘层17的通孔，通过形成于该通孔内的框架结构13，包围一个或多个电极11。
这样的框架结构13是由Sn、Pb、Au或它们的合金、Cu或Ni等能够通过电镀形成厚膜的材料形成的。
此外，还可以用易接合材料覆盖框架结构13的表面。
在内插板2的Si基板上也与半导体芯片1同样地，形成半导体元件的布线层26、绝缘层27以及接地布线层28，进而，形成包围一个或多个电极21的框架结构23。
因为形成于Si基板10上的多个电极11的配置与形成于Si基板20上的多个电极21的配置相对应，因此当框架结构13与框架结构23接合并将半导体芯片1安装于内插板2时，形成于Si基板10上的一个或多个电极11的每个与形成于Si基板20上的对应的一个或多个电极21的每个接触，达成电连接。
框架结构彼此的接合可以采用加热接合、常温接合等技术适宜地进行。例如，在由镀镍形成了框架结构13和23的情况下，可以通过附加焊料来接合框架结构彼此。
另外，在第2实施方式中，使第1基板和第2基板的至少一个基板、优选两者的基板的厚度都尽可能地薄型化，付与基板自身以弹性。由此，能够保证多个电极11的每个与多个电极21的每个相接触，此外，因为即使在两个基板材质不同的情况下，也能够缓冲热应力，所以就提高了半导体装置的可靠性。例如使基板厚度在50μm以下，优选30μm以下。
当接合框架结构13和框架结构23时，通过框架结构气密密封电极11和21，在框架结构内部形成空间30。空间30维持真空，即低于大气压的压力状态。或者，在空间30中封入不与电极反应的气体，例如氮气或者氩等惰性气体或其混合物。
因为电极周围是真空或者是不与电极发生反应的气体环境，所以不会有电极劣化从而破坏电接触的情况。
在该实施方式中，在能够在真空中照射高速氩原子束的净化装置(未图示)中，通过照射高速氩原子束到Si基板10上的电极11的表面以及形成于Si基板20上的电极21的表面，从而去除表面上的氧化物和有机物等附着物，能够使这些表面净化。由此，降低电极间的接触电阻。
在该实施方式中，可以仅在Si基板10上形成框架结构13，将该框架结构13接合于Si基板20上，也可以仅在Si基板20上形成框架结构23，将该框架结构23接合到Si基板10上。
虽然是使用代表例对本发明的半导体装置及其制造方法进行了说明，但是上述说明仅作为本发明的示例，本发明并不局限于此。

Claims (10)

1.一种半导体装置，其特征在于，
包含：形成有一个或多个电极的第1基板、形成有一个或多个电极的第2基板以及框架结构，
形成于第1基板上的一个或多个电极的每个电连接到形成于第2基板上的对应的一个或多个电极的每个上，
框架结构包围形成于第1和第2基板上的电极，由此气密密封这些电极，
第1基板和第2基板经由框架结构接合。
2.权利要求1所述的半导体装置，其特征在于，框架结构内部为真空。
3.权利要求1所述的半导体装置，其特征在于，框架结构内部密封有氮气或惰性气体或者它们的混合物之任一种。
4.权利要求1所述的半导体装置，其特征在于，形成于第1基板上的一个或多个电极的每个与形成于第2基板上的对应的一个或多个电极的每个不被接合在一起，而是通过电极彼此的接触从而达成电连接。
5.权利要求4所述的半导体装置，其特征在于，框架结构与第1基板和第2基板的至少一个基板可分离地接合着。
6.权利要求5所述的半导体装置，其特征在于，框架结构通过焊料而接合到基板上。
7.权利要求1所述的半导体装置，其特征在于，对形成于第1基板和第2基板上的电极的表面进行净化处理。
8.权利要求1所述的半导体装置，其特征在于，形成于第1基板上的一个或多个电极的每个与形成于第2基板上的对应的一个或多个电极的每个，经由具有弹性的突起而电连接。
9.权利要求8所述的半导体装置，其特征在于，具有弹性的突起的弹簧常数为1000N/m以下。
10.权利要求1所述的半导体装置，其特征在于，形成于第1基板上的一个或多个电极的每个与形成于第2基板上的对应的一个或多个电极的每个，通过无突起结构而电连接。
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