JP4932744B2 - 配線基板及びその製造方法並びに電子部品装置及びその製造方法 - Google Patents
配線基板及びその製造方法並びに電子部品装置及びその製造方法 Download PDFInfo
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- JP4932744B2 JP4932744B2 JP2008002649A JP2008002649A JP4932744B2 JP 4932744 B2 JP4932744 B2 JP 4932744B2 JP 2008002649 A JP2008002649 A JP 2008002649A JP 2008002649 A JP2008002649 A JP 2008002649A JP 4932744 B2 JP4932744 B2 JP 4932744B2
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- 229910045601 alloy Inorganic materials 0.000 description 8
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- 229910052737 gold Inorganic materials 0.000 description 5
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- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 229910017052 cobalt Inorganic materials 0.000 description 1
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- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Description
11…樹脂基板(配線基板本体)、
12,13…配線層、
12P,13P…パッド部、
14,15…ソルダレジスト層(保護膜/絶縁層)、
16,16a…シード層(導体層)、
17,17a…めっき配線層(導体層)、
20…チップ(電子部品)、
21…バンプ(電極端子)、
30…電子部品装置、
AG,AG1…空隙、
FB,FB1…フレキシブルバンプ(外部接続端子)。
Claims (5)
- 電子部品を実装する配線基板であって、
複数の端部及び該端部間に位置する略中央部分を有し、該略中央部分に前記電子部品の電極端子が接続可能に設けられた外部接続端子を備え、
前記外部接続端子は2層構造の導体層からなり、少なくとも外層側の導体層は、弾性を有するめっき配線により形成され、
前記外部接続端子の各端部が、前記配線基板の電子部品実装面側の絶縁層上に形成されるとともに、少なくとも端部の一部分が、前記絶縁層から露出するパッド部に電気的に接続されており、
前記外部接続端子は、平面的に見たときに少なくとも2本の配線パターンが交差している形状を有し、前記外部接続端子の略中央部分が、当該電子部品実装面との間に空隙を保つように突出して形成されていることを特徴とする配線基板。 - 前記外部接続端子の略中央部分は、断面的に見たときにアーチ状に成形されていることを特徴とする請求項1に記載の配線基板。
- 電子部品実装面側にパッド部を露出させて絶縁層が形成された配線基板本体を作製する工程と、
前記絶縁層上に、平面的に見たときにラインもしくはドットの形状を呈し、かつ、断面的に見たときに台形もしくは半円の形状を呈する犠牲層を形成する工程と、
前記犠牲層が形成されている側の面全体に第1の導体層を形成する工程と、
前記第1の導体層上に、前記パッド部に接続される外部接続端子を構成し弾性を有する第2の導体層を、電解めっきにより、平面的に見たときに少なくとも2本の配線パターンが交差している形状に形成する工程と、
前記犠牲層を除去する工程とを含むことを特徴とする配線基板の製造方法。 - 請求項1に記載の配線基板に、電子部品が、その電極端子を導電性バンプを介して前記外部接続端子に接続させて実装されていることを特徴とする電子部品装置。
- 電子部品実装面側にパッド部を露出させて絶縁層が形成された配線基板本体を作製する工程と、
前記絶縁層上に、平面的に見たときにラインもしくはドットの形状を呈し、かつ、断面的に見たときに台形もしくは半円の形状を呈する犠牲層を形成する工程と、
前記犠牲層が形成されている側の面全体に第1の導体層を形成する工程と、
前記第1の導体層上に、前記パッド部に接続される外部接続端子を構成し弾性を有する第2の導体層を、電解めっきにより、平面的に見たときに少なくとも2本の配線パターンが交差している形状に形成する工程と、
電子部品を、その電極端子を導電性バンプを介して前記第2の導体層上に接続して実装する工程と、
前記犠牲層を除去する工程とを含むことを特徴とする電子部品装置の製造方法。
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JP2008002649A JP4932744B2 (ja) | 2008-01-09 | 2008-01-09 | 配線基板及びその製造方法並びに電子部品装置及びその製造方法 |
US12/332,572 US7859121B2 (en) | 2008-01-09 | 2008-12-11 | Wiring board and method of manufacturing the same, and electronic component device using the wiring board and method of manufacturing the same |
US12/662,300 US8062927B2 (en) | 2008-01-09 | 2010-04-09 | Wiring board and method of manufacturing the same, and electronic component device using the wiring board and method of manufacturing the same |
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JP5367523B2 (ja) * | 2009-09-25 | 2013-12-11 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
US8632016B2 (en) * | 2011-07-11 | 2014-01-21 | George Schmitt & Company, Inc. | RFID chip employing an air gap buffer |
JP6520481B2 (ja) * | 2015-06-30 | 2019-05-29 | 富士電機株式会社 | 電子部品モジュール |
KR20200115757A (ko) * | 2019-03-25 | 2020-10-08 | 삼성디스플레이 주식회사 | 회로기판 및 이의 제조방법 |
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JP3058409B2 (ja) * | 1998-01-05 | 2000-07-04 | 日本電気株式会社 | 半導体チップの実装方法および実装構造 |
JP4207033B2 (ja) | 1998-03-23 | 2009-01-14 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US6333565B1 (en) * | 1998-03-23 | 2001-12-25 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
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US6183267B1 (en) * | 1999-03-11 | 2001-02-06 | Murray Hill Devices | Ultra-miniature electrical contacts and method of manufacture |
US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
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JP2009164493A (ja) | 2009-07-23 |
US8062927B2 (en) | 2011-11-22 |
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