TWI452659B - 電路板及其製作方法與封裝結構 - Google Patents

電路板及其製作方法與封裝結構 Download PDF

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Publication number
TWI452659B
TWI452659B TW101100028A TW101100028A TWI452659B TW I452659 B TWI452659 B TW I452659B TW 101100028 A TW101100028 A TW 101100028A TW 101100028 A TW101100028 A TW 101100028A TW I452659 B TWI452659 B TW I452659B
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Taiwan
Prior art keywords
bumps
bump
pin
circuit board
substrate
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TW101100028A
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English (en)
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TW201316464A (zh
Inventor
Pai Sheng Cheng
Chia Hui Wu
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Himax Tech Ltd
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Description

電路板及其製作方法與封裝結構
本發明係關於一種電路板及其製作方法與封裝結構，尤指一種其引腳具有一凸塊設於其上之電路板及其製作方法與封裝結構。
覆晶封裝製程係為一種現今使用最普遍的電子封裝製程。相較於其他封裝製程，使用於覆晶封裝製程中之晶片並不會藉由打線製程利用一焊墊將晶片電性連接至封裝基板，取而代之，各焊墊上係分別形成一金凸塊，然後翻轉晶片，再利用一異方性導電薄膜或銀膠將晶片之金凸塊黏著在封裝基板上。一般而言，覆晶封裝製程因不需額外導線來建立電性連接，而可有效降低封裝基板之大小，且增加晶片與封裝基板之間的電路傳遞。
請參考第1圖，第1圖為習知具有金凸塊之晶片之示意圖。如第1圖所示，一晶片10包括一晶片基板12、一焊墊14、一保護層16以及一金凸塊18。焊墊14設於晶片基板12上，且保護層16覆蓋晶片基板12以及部分焊墊14。金凸塊18設於焊墊14上，並與焊墊14相接觸。並且，為了避免晶片基板12在接合至封裝基板上時與封裝基板相接觸，金凸塊18具有一高度介於12微米與15微米之間。
然而，金凸塊係由金所構成，且金的價格不斷地往上升而非常昂貴，使將晶片接合於封裝基板上之製作成本亦不斷地增加。有鑒於此，降低將晶片接合於封裝基板上之製作成本實為業界努力之目標。
本發明之主要目的在於提供一種電路板及其製作方法與封裝結構，以降低將晶片接合於封裝基板上之製作成本。
為達上述之目的，本發明提供一種電路板，包括一基板、至少一引腳、至少一凸塊以及一焊料層。引腳設於基板上，且凸塊設於引腳上。焊料層覆蓋引腳與凸塊。
為達上述之目的，本發明提供一種封裝結構，包括一基板、至少一引腳、至少一第一凸塊、一焊料層以及一晶片。引腳設於基板上，且第一凸塊設於引腳上。焊料層覆蓋引腳與凸塊，且晶片設於第一凸塊上。
為達上述之目的，本發明提供一種電路板之製作方法。首先，提供一基板。然後，形成一引腳於基板上。接著，形成一凸塊於引腳上。隨後，形成一焊料層，以覆蓋引腳與凸塊。
本發明將第一凸塊設置於引腳上，可將晶片之第二凸塊之高度降低至小於5微米。因此，相較於習知金凸塊之高度介於12微米與15微米之間，本發明可有效地節省晶片之第二凸塊之材料成本，且將晶片接合於電路板上之製作成本亦可有效地降低。
請參考第2圖至第6圖，第2圖至第6圖為本發明一第一較佳實施例之電路板之製作方法示意圖，其中第6圖為本發明第一較佳實施例之電路板之剖面示意圖。如第2圖所示，首先，提供一基板102，然後形成一第一圖案化光阻層104於基板102上。第一圖案化光阻層104具有複數個第一開口104a，曝露出基板102之複數個部分。於本實施例中，基板102可為一印刷電路板、一可撓性電路板或一玻璃基板，且基板102之材料可包括聚亞醯胺、環氧樹脂或玻璃，但本發明之基板不以此為限。
如第3圖所示，接著，形成複數個引腳106於曝露出之基板102上，且各引腳106設於各第一開口104a中。於本實施例中，形成引腳106之步驟可利用一電鍍製程，但不限於此。此外，形成各引腳106之材料係由可藉由電鍍製程所形成之材料所構成，且可包括銅、鎳或鉻，但本發明並不限於此。
如第4圖所示，然後，形成一第二圖案化光阻層108於第一圖案化光阻層104與各引腳106之一部分上。第二圖案化光阻層108具有複數個第二開口108a，且各第二開口108a分別曝露出各引腳106。於本實施例中，各第二開口108a之寬度實質上等於或小於各引腳106之寬度。
如第5圖所示，接下來，形成複數個第一凸塊110分別於各曝露出之引腳106上，且各第一凸塊110分別設於各第二開口108a中。於本實施例中，形成第一凸塊110之步驟可利用另一電鍍製程，但不以此為限。此外，各第一凸塊110具有一高度H與一寬度W，各第一凸塊110之高度H實質上大於1微米，且各第一凸塊110之寬度W實質上等於或小於各引腳106之寬度。並且，各第一凸塊110包括鋁或銅，但本發明不限於此。
如第6圖所示，接著，移除第一圖案化光阻層104與第二圖案化光阻層108。然後，形成複數個焊料層112分別於引腳106與第一凸塊110上，且至此已完成本實施例之電路板100。於本實施例中，各焊料層112覆蓋各引腳106與各相對應之第一凸塊110，且焊料層112彼此電性絕緣。本發明並不限於此，且各焊料層112可僅分別設於各第一凸塊110上。此外，各焊料層112之材料係由可被用於與金接合之材料所構成，且可包括鎳、鉑、金或錫。並且，本發明之各焊料層112之材料並不限於此，且亦可為其他可藉由其他接合製程之導電材料。
值得注意的是，本實施例之電路板100包括形成於各引腳106上之各第一凸塊110，藉此當晶片與電路板100之間的間隙固定時，晶片用於接合第一凸塊110之第二凸塊之高度可被降低。因此，可節省晶片之第二凸塊之材料成本，且降低將晶片接合至電路板100上之製作成本。
於本發明中，第一開口104a之數量並不限為複數個，亦可僅為單一個，且引腳106之數量亦可為單一個。此外，第二開口108a之數量亦不限為複數個，而亦可為單一個，且第一凸塊110之數量與焊料層112之數量亦可分別僅為單一個。
本發明之電路板之製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化形，然為了簡化說明並突顯各實施例或變化形之間的差異，下文中使用相同標號標注相同元件，並不再對重覆部分作贅述。
請參考第7圖，且一併參考第2圖、第3圖與第6圖。第7圖為本發明一第二較佳實施例之電路板之製作方法示意圖。如第2圖與第3圖所示，相較於第一實施例，本實施例之製作方法於形成第二圖案化光阻層之步驟之前係與第一實施例相同，且不再重覆贅述。如第7圖所示，隨後，在形成第二圖案化光阻層108之前移除第一圖案化光阻層104。然後，形成第二圖案化光阻層108於基板102上，且第二圖案化光阻層108具有第二開口108a，分別曝露出各引腳106。接著，形成第一凸塊110分別於各曝露出之引腳106上。本實施例於後續之步驟係與第一實施例相同，如第6圖所示，在此不再贅述。
請參考第8圖至第10圖。第8圖至第10圖為本發明一第三較佳實施例之電路板之製作方法示意圖。如第8圖所示，首先，提供基板102，然後形成一金屬層114於基板102上。於本實施例中，形成金屬層114之步驟可為另一電鍍製程或一物理蒸鍍製程，但不限於此。並且，基板102之材料包括聚亞醯胺、環氧樹脂或玻璃，但本發明之基板不以此為限。金屬層114係由一導電材料所構成，且導電材料包括鋁、銅、鎳或鉻。如第9圖所示，接著，進行一微影與蝕刻製程，圖案化金屬層114，以形成複數個引腳圖案116於基板102上。如第10圖所示，然後，進行另一微影與蝕刻製程，圖案化各引腳圖案116，以同時形成複數個第一凸塊110與複數個引腳106。各第一凸塊110設於各引腳106上。其後，形成複數個焊料層112，以分別覆蓋各引腳106與各相對應之第一凸塊110。
本發明之電路板之結構並不以上述實施例為限。請參考第11圖，第11圖為本發明一第四較佳實施例之電路板之剖面示意圖。如第11圖所示，相較於第一實施例，本實施例之電路板200之各第一凸塊202係覆蓋各引腳106，使各第一凸塊202之寬度大於各引腳106之寬度，且各焊料層112覆蓋各第一凸塊202。
本發明另提供一種將具有凸塊之一晶片與一電路板組裝在一起之封裝結構。請參考第12圖與第13圖，第12圖為本發明一第五較佳實施例之封裝結構之上視示意圖，且第13圖為第12圖之封裝結構沿著剖面線A-A’之剖面示意圖。如第12圖與第13圖所示，封裝結構300包括一電路板100與一經片302，且晶片302設於電路板100上。本實施例之電路板100係與第一實施例之電路板相同，如第6圖所示，且相同部分不再贅述。於本實施例中，引腳106係沿著一第一方向304排列，且各引腳106沿著一第二方向306延伸出。並且，引腳106可區分為複數個長引腳308a、308b、308c、308d以及複數個短引腳310a、310b、310c、310d，且各長引腳308a、308b、308c、308d與各短引腳310a、310b、310c、310d係依序交替排列。因此，長引腳308a、308b、308c、308d之頂端312係形成於同一直線上，且短引腳310a、310b、310c、310d之頂端312亦形成於同一直線上。此外，長引腳308a、308b、308c、308d之至少一頂端312具有一沿著第一方向304之寬度實質上大於其連接之一主體部314之寬度，且短引腳310a、310b、310c、310d之至少一頂端312具有一沿著第一方向304之寬度實質上大於其連接之一主體部314之寬度。於本發明之其他實施例中，引腳106之頂端312亦可排列於同一直線上。
另外，長引腳308a、308b、308c、308d包括一第一長引腳308a、一第二長引腳308b、一第三長引腳308c、一第四長引腳308d，且短引腳310a、310b、310c、310d包括一第一短引腳310a、一第二短引腳310b、一第三短引腳310c、一第四短引腳310d。位於第一長引腳308a、第三長引腳308c、第四長引腳308d、第二短引腳310b、第三短引腳310c以及第四短引腳310d之頂端312上之第一凸塊110係具有一矩形形狀。位於第二長引腳308b之頂端312上之第一凸塊110具有十字形狀，且位於第一引腳310a之頂端312上之第一凸塊110具有圓形形狀。並且，位於第一長引腳308a、第三長引腳308c、第一短引腳310a與第四短引腳310d上之第一凸塊110沿著第一方向304之寬度係實質上小於其相對應之引腳106之頂端312之寬度。此外，位於第四長引腳308d之第一凸塊110之寬度實質上等於第四長引腳308d之頂端312之寬度，且位於第二短引腳310b與第三短引腳310c上之第一凸塊110之寬度實質上大於第二短引腳310b與第三短引腳310c之頂端312之寬度。再者，各第一凸塊110具有第一高度H1 ，實質上大於1微米。於本發明之其他實施例中，第一凸塊110可具有相同形狀或不同形狀，例如：矩形、圓形或十字形，且第一凸塊110沿著第一方向304之寬度可大於、等於或小於引腳106之頂端312沿著第一方向304之寬度。
晶片302包括一晶片基板316，複數個焊墊318、一保護層320以及複數個第二凸塊322。晶片基板316與電路板相對設置，且焊墊318設於晶片基板316面對電路板100之一側。保護層320覆蓋晶片基板316以及各焊墊318之一部分，且各第二凸塊322設於未被保護層320所覆蓋之各焊墊318上。並且，藉由進行一接合製程，各第二凸塊322可被接合至各焊料層112上，使各焊墊318可經由各第二凸塊322與各第一凸塊110分別電性連接至各引腳106。於本實施例中，各第二凸塊322包括金，且接合製程可為一共晶製程。並且，由金所構成之各第二凸塊322與接合在一起之各相對應之焊料層112彼此熔合而形成一金錫合金。本發明並不限於此，且第二凸塊322之材料亦可為可用於與焊料層相接合之導電材料。
此外，各第二凸塊322沿著第一方向304之寬度實質上可小於第一長引腳308a與第一短引腳310a之頂端312之寬度，且實質上可大於第二長引腳308b、第三長引腳308c、第四長引腳308d、第二短引腳310b、第三短引腳310c以及第四短引腳310d之頂端312之寬度。各第二凸塊322之寬度亦可大於位於第一長引腳308a、第三長引腳308c、第四長引腳308d以及第四短引腳310d上之第一凸塊110之寬度，並小於位於第二長引腳308b與第二短引腳310b上之第一凸塊110之寬度。並且，各第二凸塊322之寬度亦可等於位於第一短引腳310a與第三短引腳310c上之第一凸塊110之寬度。本發明之各第二凸塊並不限於上述寬度，且各第二凸塊322沿著第一方向304之寬度可大於、等於或小於第一凸塊110之寬度以及各引腳106之各頂端312之寬度。相同地，第二凸塊322沿著第二方向306之長度亦可大於、等於或小於第一凸塊110沿著第二方向306之長度。並且，由於各引腳106具有各第一凸塊110位於其上，因此當晶片302與電路板100之間的間隙固定在一特定距離時，本實施例之各第二凸塊322可具有一第二高度H2 ，實質上小於5微米。並且，因為金原子容易有遷移的現象，所以本實施例之各第二凸塊322之第二高度H2 因小於5微米而可避免金原子於兩相鄰之第二凸塊322之間產生遷移。各第二凸塊322與各相對應之焊料層112彼此接合而形成金錫合金，可避免於兩相鄰之第二凸塊322之間的金原子產生遷移。此外，本實施例之各焊墊318與各相對應引腳106之間具有一間隙G，實質上大於1微米，使位於晶片基板316上之電路以及其他非相對應之焊墊318不會電性連接至此相對應之引腳106。
相較於習知金凸塊之高度介於12微米與15微米之間，本實施例之封裝結構將各第一凸塊110設置於各引腳106上，以將各第二凸塊322之第二高度降低至小於5微米。因此，可有效地節省晶片302之第二凸塊322之材料成本，且降低將晶片302接合於電路板100上之製作成本。
本發明並不限利用共晶製程來接合第二凸塊與焊料層。請參考第14圖，第14圖為本發明一第六較佳實施例之封裝結構之上視示意圖。如第14圖所示，相較於第五實施例，本實施例之封裝結構400另包括一黏著層402，設於各第一凸塊110與各第二凸塊322之間，以用於將第二凸塊322與第一凸塊110接合。藉此，晶片302可藉由黏著層402接合在引腳106上。並且，黏著層402包括非導電膠(non-conductive adhesive paste，NCP)、非導電黏著薄膜(non-conductive adhesive film，NCF)、異方性導電膠(anisotropic conductive paste，ACP)或異方性導電薄膜(anisotropic conductive film，ACF)，但不限於此。
綜上所述，本發明將第一凸塊設置於引腳上，可將第二凸塊之高度降低至小於5微米。因此，相較於習知金凸塊之高度介於12微米與15微米之間，本發明可有效地節省晶片之第二凸塊之材料成本，且將晶片接合於電路板上之製作成本亦可有效地降低。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10．．．晶片
12．．．晶片基板
14．．．焊墊
16．．．保護層
18．．．金凸塊
100．．．電路板
102．．．基板
104．．．第一圖案化光阻層
104a．．．第一開口
106．．．引腳
108．．．第二圖案化光阻層
108a．．．第二開口
110．．．第一凸塊
112．．．焊料層
114．．．金屬層
116．．．引腳圖案
200．．．電路板
202．．．第一凸塊
300．．．封裝結構
302．．．晶片
304．．．第一方向
306．．．第二方向
308a．．．第一長引腳
308b．．．第二長引腳
308c．．．第三長引腳
308d．．．第四長引腳
310a．．．第一短引腳
310b．．．第二短引腳
310c．．．第三短引腳
310d．．．第四短引腳
312．．．頂端
314．．．主體部
316．．．晶片基板
318．．．焊墊
320．．．保護層
322．．．第二凸塊
400．．．封裝結構
402．．．黏著層
G．．．間隙
H1 ．．．第一高度
H2 ．．．第二高度
第1圖為習知具有金凸塊之晶片之示意圖。
第2圖至第6圖為本發明一第一較佳實施例之電路板之製作方法示意圖。
第7圖為本發明一第二較佳實施例之電路板之製作方法示意圖。
第8圖至第10圖為本發明一第三較佳實施例之電路板之製作方法示意圖。
第11圖為本發明一第四較佳實施例之電路板之剖面示意圖。
第12圖為本發明一第五較佳實施例之封裝結構之上視示意圖。
第13圖為第12圖之封裝結構沿著剖面線A-A’之剖面示意圖。
第14圖為本發明一第六較佳實施例之封裝結構之上視示意圖。
100．．．電路板
102．．．基板
106．．．引腳
110．．．第一凸塊
112．．．焊料層

Claims (4)

  1. 一種封裝結構，包括：一基板；至少一引腳，設於該基板上；至少一第一凸塊，設於該引腳上；一焊料層，覆蓋該引腳與該凸塊；以及一晶片，設於該第一凸塊上，其中該晶片具有至少一焊墊以及至少一第二凸塊，該第二凸塊設於該焊墊與該第一凸塊之間，且該第二凸塊具有一高度，實質上小於5微米。
  2. 如請求項1所述之封裝結構，另包括一黏著層，設於該第一凸塊與該第二凸塊之間，用於將該第二凸塊與該第一凸塊接合。
  3. 如請求項2所述之封裝結構，其中該黏著層包括非導電膠(non-conductive adhesive paste，NCP)、非導電黏著薄膜(non-conductive adhesive film，NCF)、異方性導電膠(anisotropic conductive paste，ACP)或異方性導電薄膜(anisotropic conductive film，ACF)。
  4. 如請求項1所述之封裝結構，其中該焊墊與該引腳之間具有一間隙，實質上大於1微米。
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