TW201034137A - Flip chip package structure - Google Patents

Flip chip package structure Download PDF

Info

Publication number
TW201034137A
TW201034137A TW98106899A TW98106899A TW201034137A TW 201034137 A TW201034137 A TW 201034137A TW 98106899 A TW98106899 A TW 98106899A TW 98106899 A TW98106899 A TW 98106899A TW 201034137 A TW201034137 A TW 201034137A
Authority
TW
Taiwan
Prior art keywords
copper
platform
bump
flip chip
flip
Prior art date
Application number
TW98106899A
Other languages
Chinese (zh)
Inventor
Shuo-Hsun Chang
Jun-Chung Hsu
Original Assignee
Kinsus Interconnect Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kinsus Interconnect Tech Corp filed Critical Kinsus Interconnect Tech Corp
Priority to TW98106899A priority Critical patent/TW201034137A/en
Publication of TW201034137A publication Critical patent/TW201034137A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

A flip chip package structure is disclosed, which comprises a substrate, a chip, a plurality of copper bumps, a plurality of copper platform, an electroplated layer and a green solder mask layer; wherein the substrate has copper bumps. Copper platforms are stacked on the copper bumps, and an electroplated layer is coated on the copper bumps and the copper platform on the copper bumps for connecting to pin pad of chip. The flip chip package structure does not need to keep distance of wirebound path so that area of original substrate can be reduced greatly, and thus the size of product can be reduced as well. Since the copper platforms are stacked on the copper bumps so that it is higher than circuit pattern layer. In this way, the chip can be padded up and the gap between the chip and substrate is increased for reducing risk of generating void when the covering material is injected, and thus increasing the package yield.

Description

201034137 六、發明說明： 【發明所屬之技術領域】 本發明係有關覆晶封裝結構，尤其是具有銅平台凸 塊之覆晶平台結構。 【先前技術】 覆晶(FlipChip ; FC)封裝為新世代的半導體封裝方 式，其中基板（substrate)與晶片I/O連接方式係仰賴基 ❹ 板上的鎖、錯凸塊與晶圓凸塊(waferbumping)做溶接，來 達到傳遞訊號或電能的目的。覆晶封裝在經由個人電腦 (Personal Computer ; PC)相關晶片產品的大量應用後，便 朝向手機、MP3等手持式產品之晶片封裝應用，近年來 有顯著的成長。相較於目前手持式消費性產品晶片盛行 的的打線接合晶片尺寸封裝(Wire_B〇nd type chip Scale201034137 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a flip chip package structure, particularly a flip chip platform structure having a copper land bump. [Prior Art] FlipChip (FC) package is a new generation of semiconductor packaging, in which the substrate and wafer I/O connection depends on the locks, bumps and bumps on the substrate. Waferbumping) is done to achieve the purpose of transmitting signals or power. Flip chip packaging has become a chip packaging application for handheld products such as mobile phones and MP3s after a large number of applications related to personal computer (Personal Computer; PC) related chip products, and has experienced remarkable growth in recent years. Wire-bonded chip size package (Wire_B〇nd type chip scale) compared to current handheld consumer product chips

Package)方式’金柱凸塊覆晶(G〇id §加d Bump FC)封裝可 免除晶圓凸塊的製程花費又仍可保有覆晶封裝的電性性 ❹ 此’並可藉著金柱凸塊的微細凸塊間距(Fine Bump Pitch) 來提高製概力。且由於改成覆晶封裝，基板不需保留 打線接合(Wire-Bond)路徑之距離，可大幅縮小原本基板 的面積，使產品尺寸跟著縮小。 參閱第-圖’傳統覆晶封裝結構示意圖，其中傳統 覆晶封裝結構1係包括-傳統覆晶平台結構4、—包覆材 料:以及—晶片8。該基板上之銅凸塊33中被電鍍層34 覆孤之邛分與位於晶片8下方之銅柱接腳墊丨^藉由焊接 方法相接合’再於該⑼8與該賴覆晶平台結構4之 間填充一包覆材料7。 3 201034137 多閱第^一圖、第二圖以及第四圖，将爲值缔豫曰伞 台結構俯視圖、傳統覆晶平台結構縱向剖面圖以及:統 覆晶平台結構橫向剖面圖，其中第二圖中的右圖為左圖 的局部結構放大圖、第三圖為第二圖中由割線A_A，切割 所顯示之結構以及第四圖為第二圖中由割線B-B，切割 所顯不之結構。如第二圖所示，此傳統覆晶平台結構4 係包含包括一基板40、一傳統周圍覆晶墊區域3〇以及一 、、、彔漆層50’其中該傳統覆晶墊區域3〇包括複數個傳統覆 ❹ 阳墊&，該等傳統覆晶塾3丨係個別包括一銅凸塊33覆 蓋於其上之電鍍層34。如第四圖所示，該銅凸塊33係低 於該綠漆層5〇 _定高度。 然而習用技術中由於該晶片8與該綠漆層5〇之間的 間隙dl太小，該包覆材料7内的填充物又不夠小，因此 會於晶片8與綠漆層50之間的間隙dl造成堵塞，使得 曰曰片8正下方產生空孔，造成封裝良率降低。 【發明内容】 ❹ 本發明之主要目的在提供一種覆晶封裝結構，係包 括一基板、一晶片、複數個銅平台凸塊、一電路圖案層、 一電鍍層以及一綠漆層，其中基板上具有複數個銅平台 凸塊以及電路圖案層，該等銅平台凸塊之高度高於該電 路圖案層之尚度。銅平台凸塊係包含一銅平台以及一銅 凸塊，而該銅平台堆疊於銅凸塊上，並在銅平台凸塊上 鍍一電鍍層，用以與位於晶片下方之晶片接腳墊相連 接。該覆晶封裝結構不需保留打線接合(^^]8〇1111(1)路 徑的距離，可大幅縮小原本基板的面積使產品尺寸跟著 201034137 因此本發明可解決上述習知技術的缺失，利用該等 銅平台凸塊之高度高於該電路圖案層之高度，用以塾高 晶片，使晶片與基板之間的間隙增加，減少灌入包覆材 料時產生空孔之風險並提昇封裴之良率。 【實施方式】 以下配合圖式及元件符號對本發明之實施方式做更 ❹ 詳細的_，俾使㈣者麵縣綱書後能 據以實施。 參閱第五圖’本發明之覆晶封裝結構之示意圖，此 覆晶封裝結構3係包括-晶片8、—覆晶平台結構5以及 一包覆材料7。該晶片8係包含複數個晶片接腳塾1〇， f中該等晶片接腳墊10位於該晶片8之下方。該覆晶平 台結構5係包括一基板40、複數個銅平台凸塊32、一電 鍍層34、一電路圖案層36以及一綠漆層5〇，其中該等 .銅平台凸塊32以及該電路圖案層36皆位於該基板仙之 上表面’其巾該等解台凸塊32巾的每―個銅平台凸塊 32中的-部份之高度係高於該電路圖案層抓之高度。該 、，亲漆層50則覆蓋於基板4〇上表面之一部份、電路圖案 層36之上表面以及該等銅平台凸塊犯上表面之一部>、 伤’該電觸34覆胁該等銅平台凸塊32上表面 被該綠漆層50覆蓋的部份。將位於基板上之銅平台 32中被電錢層34覆蓋之部分與位於晶片8下方之晶 腳墊ίο糟由熱麼(Thermo_compressi〇n)焊接方法相接 合，再於該晶片8與該覆晶平台結構5之間灌入一包覆 5 201034137Package) 'gold pillar bump flip-chip (G〇id § plus d Bump FC) package can eliminate the cost of wafer bumps and still retain the electrical properties of flip chip package ❹ The Fine Bump Pitch of the bumps increases the build-up force. Moreover, since the substrate is changed to a flip chip package, the substrate does not need to maintain the distance of the wire-bonding path, and the area of the original substrate can be greatly reduced, so that the product size is reduced. Referring to the 'panel' conventional flip chip package structure, the conventional flip chip package structure 1 includes a conventional flip chip structure 4, a cladding material: and a wafer 8. The copper bumps 33 on the substrate are covered by the plating layer 34, and the copper pillar pads located under the wafer 8 are joined by soldering method. Then the (9) 8 and the laminated crystal platform structure 4 are A coating material 7 is filled between them. 3 201034137 Read more ^1, 2nd and 4th, which will be the top view of the value of the umbrella structure, the longitudinal section of the traditional flip-chip platform structure and the transverse section of the platform structure, the second The figure on the right is an enlarged view of the partial structure on the left, the third is the structure shown by the cut line A_A in the second figure, and the fourth figure is the structure shown by the cut line BB in the second figure. . As shown in the second figure, the conventional flip chip platform structure 4 includes a substrate 40, a conventional surrounding flip chip region 3A, and a lacquer layer 50', wherein the conventional flip chip region 3 includes A plurality of conventional cover pads & the conventional flip chip 3 series individually include a plating layer 34 over which a copper bump 33 is overlaid. As shown in the fourth figure, the copper bumps 33 are lower than the height of the green lacquer layer. However, in the conventional technique, since the gap dl between the wafer 8 and the green lacquer layer 5 is too small, the filler in the covering material 7 is not small enough, so that a gap is formed between the wafer 8 and the green lacquer layer 50. The dl causes clogging, which causes voids to be formed directly under the cymbal 8, resulting in a decrease in package yield. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flip chip package structure comprising a substrate, a wafer, a plurality of copper landing bumps, a circuit pattern layer, a plating layer, and a green lacquer layer on the substrate. The utility model has a plurality of copper platform bumps and a circuit pattern layer, and the height of the copper platform bumps is higher than the degree of the circuit pattern layer. The copper platform bump comprises a copper platform and a copper bump, and the copper platform is stacked on the copper bump, and a plating layer is plated on the copper platform bump for the wafer pad under the wafer. connection. The flip chip package structure does not need to retain the distance of the wire bonding (^^)8〇1111(1) path, and the area of the original substrate can be greatly reduced to make the product size follow 201034137. Therefore, the present invention can solve the above-mentioned shortcomings of the prior art, and utilize the The height of the copper platform bumps is higher than the height of the circuit pattern layer to increase the wafer, increase the gap between the wafer and the substrate, reduce the risk of voids when filling the cladding material, and improve the yield of the package. [Embodiment] Hereinafter, the embodiment of the present invention will be further described in detail with reference to the drawings and the component symbols, and the fourth embodiment can be implemented after the invention. Referring to the fifth figure, the flip chip package structure of the present invention is The flip chip package structure 3 includes a wafer 8, a flip chip platform structure 5, and a cladding material 7. The wafer 8 includes a plurality of wafer pins 1 , f in the wafer pad 10 Located below the wafer 8. The flip-chip structure 5 includes a substrate 40, a plurality of copper landing bumps 32, a plating layer 34, a circuit pattern layer 36, and a green lacquer layer 5, wherein the copper Platform bumps 32 and The circuit pattern layer 36 is located on the upper surface of the substrate. The height of the portion of each of the copper platform bumps 32 of the substrate is higher than the height of the circuit pattern layer. The lacquer layer 50 covers a portion of the upper surface of the substrate 4, the upper surface of the circuit pattern layer 36, and one of the copper platform bumps on the surface > The portion of the copper platform bump 32 whose upper surface is covered by the green lacquer layer 50. The portion of the copper platform 32 on the substrate covered by the money layer 34 and the crystal pad located under the wafer 8 are damaged. Thermal (Thermo_compressi〇n) welding method is joined, and then a coating is applied between the wafer 8 and the flip-chip structure 5 5 201034137

材料7 ’其中該等晶片接腳墊丨〇可為銅柱凸塊(Cu pi丨lar Bump)或金柱凸塊(Gold Stud Bump)，該包覆材料7可 為底塗封裝(Under-Fill)或模制化合物(aiding Compound)。因該覆晶封裝結構3不需保留打線接合 (wirebound)路徑的距離’可大幅縮小原本基板的面積使 產品尺寸跟著縮小。而該等銅平台凸塊32之高度高於該 電路圖案層36之高度，用以墊高晶片，使晶片與綠漆層 50之間的間隙d2增加，減少灌入包覆材料7時產生空孔 之風險並提昇封裝之良率。 參閱第六圖，本發明之—實施例之示意圖，其中覆晶 平台結構可為第五圖的覆晶封裝結構之示範實施例，第六 圖中的右_左_局聽構放大®，此覆晶平台結構5 係包括基板40、一周圍覆晶(Peripheral FUp Chip)塾區域 30以及-綠漆層5〇 ’其中該周圍覆晶墊區域7〇包括複數 個覆晶塾71’鱗覆晶墊7H_細平台凸塊犯中被電 鍍層34覆蓋的部份’該綠漆層5〇係覆蓋於基板4〇的一 部份上表面與銅平台凸塊32的另—部份上表面。 、參閱第七_及第八圖，本發明之實關之橫向剖面 圖二及本&月之只施例之縱向剖面圖，其中第七圖為第六 蝴所顯示之結構以及第八圖為第六圖 贿齡之結構。如第七騎示，位於 =土上之複數個鋼平台凸塊32係個別包括-銅凸塊 平台咖°如第八圖所示，該銅平台咖堆 ^ #刀上，銅平台32b係凸出於銅凸 表向度。綠漆層50係覆蓋於基板40上表 面以及銅凸塊32a上表面之一部份，電鑛㈣則經由^ 6 201034137 金屬表面技術覆蓋於銅平台32a以及銅凸塊上表面中未被 該綠漆層50覆蓋的部份，其中該金屬表面技術可為錫電 錢(Plating Tin)、浸鍍錫（Immersion Tin)、有機保焊劑 製程（Organic Solderability Preservative ; 0SP)、化 錄金(Electroless Ni & Immersion Gold ; ENIG)或無電 鍍鈀鎳金（electroless nickel electroless palladium immersion gold ； ENEPIG) °Material 7' wherein the wafer pad pads may be Cu pi丨lar bumps or Gold Stud Bumps, and the cladding material 7 may be a primer package (Under-Fill) Or an aiding compound. Since the flip chip package structure 3 does not need to maintain the distance of the wirebound path, the area of the original substrate can be greatly reduced to reduce the size of the product. The height of the copper platform bumps 32 is higher than the height of the circuit pattern layer 36 for raising the wafer to increase the gap d2 between the wafer and the green lacquer layer 50, thereby reducing the empty space when filling the cladding material 7. The risk of holes increases the yield of the package. Referring to the sixth embodiment, a schematic diagram of an embodiment of the present invention, wherein the flip chip platform structure can be an exemplary embodiment of the flip chip package structure of the fifth figure, and the right_left_office structure of the sixth figure is enlarged, The flip chip platform structure 5 includes a substrate 40, a Peripheral FUp Chip germanium region 30, and a green paint layer 5〇, wherein the surrounding flip chip region 7〇 includes a plurality of flip chip 71' scale crystals The pad 7H_thin platform bump hits the portion covered by the plating layer 34. The green lacquer layer 5 covers a portion of the upper surface of the substrate 4 and the other upper surface of the copper land bump 32. Referring to the seventh and eighth figures, the transverse cross-sectional view of the actual embodiment of the present invention and the longitudinal cross-sectional view of only the embodiment of the present & month, wherein the seventh figure is the structure shown by the sixth butterfly and the eighth figure The structure of the bribe age for the sixth picture. For example, the seventh riding shows that the plurality of steel platform bumps 32 located on the soil are individually included - the copper bump platform is as shown in the eighth figure, the copper platform coffee maker ^ #刀, the copper platform 32b is convex Out of copper convexity. The green lacquer layer 50 covers a portion of the upper surface of the substrate 40 and a portion of the upper surface of the copper bump 32a, and the electric ore (4) is overlaid on the copper platform 32a and the upper surface of the copper bump via the metal surface technology of ^6 201034137. The portion covered by the lacquer layer 50, wherein the metal surface technology can be Plating Tin, Immersion Tin, Organic Solderability Preservative (0SP), and Electroless Ni &amp ; Immersion Gold ; ENIG) or electroless nickel electroless palladium immersion gold (ENEPIG) °

要注意的是，第七圖以及第八圖中的虛線僅是方便清 楚說明銅凸塊32a及銅平台32b之相對位置，銅凸塊32a 及銅平台32b實際上為連續性之結構。 人^上者料㈣娜本判讀佳實施例，並非 ㈣触祕域m凡有_ 應包括在任何修飾或變更’皆仍It is to be noted that the dashed lines in the seventh and eighth figures are only for the purpose of clearly explaining the relative positions of the copper bumps 32a and the copper land 32b, and the copper bumps 32a and the copper land 32b are actually continuous structures. The person who is on the subject (4) Naben has read the best example, not (4) the secret domain m has _ should be included in any modification or change’

7 201034137 【圖式簡單說明】 第一圖為傳統覆晶封裝結構示意圖。 第二圖為傳統覆晶平台結構俯視圖。 第三圖為傳統覆晶平台結構縱向剖面圖。 第四圖為傳統覆晶平台結構橫向剖面圖。 第五圖為本發明之覆晶封裝結構之示意圖。 第六圖為本發明之一實施例之示意圖。 第七圖為本發明之實施例之縱向剖面圖。 第八圖為本發明之實施例之橫向剖面圖。 ❿ 【主要元件符號說明】 1傳統覆晶封裝結構 3覆晶封裝結構 5覆晶平台結構 6晶片層 7包覆材料 8晶片 Ο ίο晶片接腳墊 14銅柱接腳墊 30傳統周圍覆晶墊區域 31傳統覆晶墊 32銅平台凸塊 32a銅凸塊 32b銅平台 33銅凸塊 34電鍍層 201034137 36電路圖案層 40基板 50綠漆層7 201034137 [Simple description of the diagram] The first picture is a schematic diagram of a traditional flip chip package structure. The second picture is a top view of the conventional flip-chip platform structure. The third picture is a longitudinal sectional view of a conventional flip-chip platform structure. The fourth picture is a transverse sectional view of the conventional flip-chip platform structure. The fifth figure is a schematic view of the flip chip package structure of the present invention. Figure 6 is a schematic illustration of an embodiment of the invention. Figure 7 is a longitudinal cross-sectional view of an embodiment of the present invention. The eighth figure is a transverse cross-sectional view of an embodiment of the present invention. ❿ [Main component symbol description] 1 traditional flip chip package structure 3 flip chip package structure 5 flip chip platform structure 6 wafer layer 7 cladding material 8 wafer Ο 晶片 接 晶片 接 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 铜 铜 铜 铜 铜 铜 铜 传统 传统 传统 传统 传统 传统Area 31 conventional flip chip 32 copper platform bump 32a copper bump 32b copper platform 33 copper bump 34 plating layer 201034137 36 circuit pattern layer 40 substrate 50 green paint layer

70 周圍覆晶（Peripheral Flip Chip)墊區域 Ή覆晶墊 A-Α’割線 B-B’割線 c-σ割線 D-D’割線 dl間隙 d2間隙70 Peripheral Flip Chip pad area ΉCrystal pad A-Α' secant B-B' secant c-σ secant D-D' secant dl gap d2 gap

Claims (1)

201034137 七、申請專利範圍·· 1. 一種覆晶封裝結構，包括： 一晶片，係包含複數個晶片接腳墊，而該等晶片接腳墊位 於該晶片之下方； 一覆晶平台結構，係包令^一基板、複數個銅平台凸塊、一 電鑛層、一電路圖案層以及一綠漆層，而該等銅平台凸塊 以及該電路圖案層皆位於該基板之上表面，該綠漆層覆蓋 於該基板上表面之一部份、該電路圖案層之上表面以及該 ❿ 等銅平台凸塊上表面之H該電騎舰由-金屬表 面技術覆蓋於該等銅平台凸塊上表面中未被該綠漆層覆蓋 的部份；以及 包復材科 π伋准入，亥晶片與該覆晶平台結構之間。 2. 依據申請專利範_ i項所述之覆晶雖結構，其中 銅平台凸塊烟包含-銅凸塊以及—銅平台 x 堆疊於該銅凸塊上表面之一部份。 幻十。係 3. 依據申請專利範圍第丨項所述之覆晶封裝結構，苴中 ==的每，鋼平台凸塊中覆蓋該電錢層之部分 4 項封裝結構’其_ 5依撼申咬直批 知接方法與該覆晶塾相接合。 5. 依據申明專她_4項所述 二 接方法係為熱壓焊接方法。 職4，其中該焊 6. ==第1項所述之覆晶封裝結構，其中兮金 =:錫電鍍、浸鑛錫、有機保焊劑製程Γί 金或無電鑛免錦金。 a表柱、化錄 7. 依據申請專利範圍筮^ 圍第1項所述之覆晶封裝結構，其中該等 201034137 銅=凸塊中的每一個铜平台 度孫高 於該電路_層之高度。 τ的一部知 8·依齡請專利範_丨項所述之覆晶封㈣構，其中該包 覆材料係為底塗封裝或模制化合物。 9.依據申請專利範圍第1項所述之覆晶封袭結構， 晶片接腳墊係為銅柱凸塊或金柱凸塊。 〃丁 β寺201034137 VII. Patent Application Scope 1. A flip chip package structure comprising: a wafer comprising a plurality of wafer pads, and the wafer pads are located under the wafer; a flip chip platform structure a substrate, a plurality of copper platform bumps, an electric ore layer, a circuit pattern layer, and a green lacquer layer, wherein the copper platform bumps and the circuit pattern layer are located on an upper surface of the substrate, the green The lacquer layer covers a portion of the upper surface of the substrate, the upper surface of the circuit pattern layer, and the upper surface of the copper platform bump of the crucible. The electric saddle is covered by the metal surface technology on the copper platform bump. The portion of the surface that is not covered by the green lacquer layer; and the π汲 access of the cladding material, between the wafer and the flip-chip structure. 2. According to the flip-chip structure described in the patent application, wherein the copper platform bump smoke comprises a copper bump and a copper platform x stacked on a portion of the upper surface of the copper bump. Magic ten. System 3. According to the flip-chip package structure described in the scope of the patent application, in the =中==, the steel platform bump covers a part of the four-package structure of the electric money layer. A batch bonding method is bonded to the flip chip. 5. According to the declaration of her _4 item, the second method is a hot-press welding method. Job 4, wherein the welding 6. == The flip chip package structure described in item 1, wherein the sheet metal =: tin plating, immersion tin, organic flux soldering process Γί gold or non-electric mine free gold. a table column, chemical record 7. According to the scope of the patent application, the flip chip package structure described in item 1, wherein each of the 201034137 copper=bumps is higher than the height of the circuit layer . A part of τ. The invention relates to a flip-chip seal (four) structure according to the invention, wherein the covering material is a primer coating or a molding compound. 9. According to the flip chip encapsulation structure described in claim 1, the wafer pad is a copper stud bump or a gold stud bump. Kenting Beta Temple
TW98106899A 2009-03-03 2009-03-03 Flip chip package structure TW201034137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW98106899A TW201034137A (en) 2009-03-03 2009-03-03 Flip chip package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW98106899A TW201034137A (en) 2009-03-03 2009-03-03 Flip chip package structure

Publications (1)

Publication Number Publication Date
TW201034137A true TW201034137A (en) 2010-09-16

Family

ID=44855414

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98106899A TW201034137A (en) 2009-03-03 2009-03-03 Flip chip package structure

Country Status (1)

Country Link
TW (1) TW201034137A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8674503B2 (en) 2011-10-05 2014-03-18 Himax Technologies Limited Circuit board, fabricating method thereof and package structure
TWI625829B (en) * 2014-08-01 2018-06-01 Electrical connection structure between front and back of chip and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8674503B2 (en) 2011-10-05 2014-03-18 Himax Technologies Limited Circuit board, fabricating method thereof and package structure
TWI452659B (en) * 2011-10-05 2014-09-11 Himax Tech Ltd Circuit board, fabricating method thereof and package structure
TWI625829B (en) * 2014-08-01 2018-06-01 Electrical connection structure between front and back of chip and manufacturing method thereof

Similar Documents

Publication Publication Date Title
TWI322448B (en) Semiconductor stacked multi-package module having inverted second package
US9129818B2 (en) Semiconductor device having conductive pads and a method of manufacturing the same
US20110049703A1 (en) Flip-Chip Package Structure
TWI273667B (en) Chip package and bump connecting structure thereof
US10879203B2 (en) Stud bump structure for semiconductor package assemblies
US20180114786A1 (en) Method of forming package-on-package structure
KR101051350B1 (en) Semiconductor device and manufacturing method thereof
JP2009239256A (en) Semiconductor device and method of fabricating same
CN108807297A (en) Electronic package and manufacturing method thereof
TW201250942A (en) Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
KR20040092411A (en) Wiring substrate and electronic parts packaging structure
JP2005539403A5 (en)
CN102543939A (en) Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof
CN101582395A (en) Wiring board
CN202434509U (en) Stackable semiconductor chip packaging structure
CN103219324A (en) Stackable semiconductor chip packaging structure and process thereof
US20050001303A1 (en) Method of manufacturing multi-chip stacking package
JP4836847B2 (en) Semiconductor device and manufacturing method of semiconductor device
TW201034137A (en) Flip chip package structure
TWI336516B (en) Surface structure of package substrate and method for manufacturing the same
CN102231376A (en) Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method
CN207818561U (en) A kind of encapsulating structure of semiconductor chip
Ooida et al. Advanced Packaging Technologies supporting new semiconductor application
TWI500129B (en) Semiconductor flip-chip bonding structure and process
CN101252107B (en) Semiconductor package structure and manufacturing method thereof