CN101252107B - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
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- CN101252107B CN101252107B CN2008100878082A CN200810087808A CN101252107B CN 101252107 B CN101252107 B CN 101252107B CN 2008100878082 A CN2008100878082 A CN 2008100878082A CN 200810087808 A CN200810087808 A CN 200810087808A CN 101252107 B CN101252107 B CN 101252107B
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- protective layer
- connection pad
- metal level
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention discloses a semiconductor packaging structure, which comprises a semiconductor base material, a first passivation layer, a first metallic layer, a second passivation layer, a second metallic layer and a third metallic layer, wherein, the semiconductor base material is provided with a surface; at least one first welded gasket and at least one second welded gasket are arranged on the surface; the first passivation layer covers the surface of the semiconductor base material and exposes the first welded gasket and the second welded gasket; the first metallic layer is formed on the first passivation layer and electrically connected with the second welded gasket; the second passivation layer is formed on the first metallic layer and exposes the first welded gasket and a part of the first metallic layer; the second metallic layer is formed on the second passivation layer and electrically connected with the first welded gasket; the third metallic layer is formed on the second passivation layer and electrically connected with the first metallic layer.
Description
Technical field
The invention relates to a kind of semiconductor package and manufacture method thereof, and particularly relevant for a kind of redistribution layer (Re-Distribution Layer; RDL) structure and manufacture method thereof.
Background technology
Along with electronic product towards light, thin, short, little development trend, correspondingly also will be on the encapsulation kenel towards the designs of high density pin more, and then produced the packaged type of many new kenels, the packaged type of these new kenels comprises: (1) ball-shaped grid array (Ball grid array, BGA), it is connected with circuit board by the tin ball, replaces traditional pin with the tin ball, and the tin ball is arranged with the pattern of display; (2) crystal face is encapsulated (Flip Chip) down and by the brilliant formula of falling that Solder Bumps combines with substrate; (3) quad flat package (Quad Flat Package, QFP) etc.Except that aforementioned, at present the encapsulation technology of tool advantage is distribution layer (Re-Distribution Layer again in the prior art; RDL), seeing through this technology can be with must be by the pressure welding point of chip center in the conventional package technology, be re-assigned to periphery, both sides or any side of chip, and make multi-plate chip can be vertical stacking, be staggeredly stacked or pile up in mode side by side by this design.
Existing redistribution layer when design and fabrication, be see through elongated individual layer circuit with power supply signal and ground signalling in addition again backguy distribute.But elongated individual layer circuit and can't be guaranteed the stable control of characteristic impedance under the transmission of the signal of high-speed high frequency, and when serious even cause the bounce-back of power supply noise and signal, this is its principal disadvantage.
Moreover, along with the increase of package count and the raising of density in single integrated circuit (IC) chip, relatively increased power consumption, though moreover the redistribution layer can see through periphery, both sides or any side that elongated circuit is re-assigned to pressure welding point chip, but make that also heat radiation is difficult for, cause the temperature of IC chip to rise, and then its characteristic, performance are influenced to some extent, cause the reduction of chip yield, this is its another shortcoming.
Therefore, existing redistribution layer utilizes the position of the pressure welding point of elongated cabling design and then input of redistribution signal and output, and it is too high to produce parasitic resistance, and causes the voltage undersupply, and the uncontrollable shortcoming of characteristic impedance.Moreover elongated line design also can increase thermal resistance, reduces the yield of chip.
Summary of the invention
Main purpose of the present invention provides a kind of semiconductor package, and its package design that can see through the redistribution layer in the IC of high-speed high frequency chip design can be controlled it to characteristic impedance.
Another object of the present invention provides a kind of semiconductor package, and it can reduce spurious impedance and inductance value in the redistribution layer package design.
A further object of the present invention provides a kind of semiconductor package, and it can reduce the thermal resistance value that is produced in the encapsulation of redistribution layer, and preferable heat radiation approach is provided, and then improves the Reliability of packaging body inner assembly.
Another purpose of the present invention provides the method that a kind of manufacturing has the semiconductor package of afore-mentioned characteristics.
For reaching above-mentioned purpose or other purpose, the present invention adopts following technical scheme: a kind of semiconductor package includes: semiconductor base material, one first protective layer, a first metal layer, one second protective layer, one second metal level and one the 3rd metal level, wherein said semiconductor substrate has a surface, has at least one first connection pad and at least one second connection pad on the described surface; Described first protective layer covers on the described semi-conductive surface, and exposes outside described first connection pad and described second connection pad; Described the first metal layer is formed on described first protective layer, and electrically connects with described second connection pad; Described second protective layer is formed on the described the first metal layer, and exposes described first connection pad and part the first metal layer; Described second metal level is formed on described second protective layer and electrically connects described first connection pad; And described the 3rd metal level is described is formed on described second protective layer, and electrically connects with described the first metal layer.
For reaching above-mentioned purpose or other purpose, the present invention also adopts following technical scheme: a kind of manufacture method of semiconductor package comprises following steps:
The semiconductor base material is provided, and described semiconductor substrate has a surface, is provided with one first connection pad and one second connection pad on described surface;
Form one first protective layer on the surface of described semiconductor substrate, described first protective layer covers the surface of described semiconductor substrate, and exposes described first connection pad and described second connection pad;
Form a first metal layer on described first protective layer, described the first metal layer and described second connection pad electrically connect;
Form one second protective layer on described the first metal layer, described second protective layer exposes described first connection pad and part the first metal layer;
On described second protective layer, form one the 4th metal level; And
Described the 4th metal level of patterning, to form one second metal level and one the 3rd metal level, wherein said second metal level and described first connection pad electrically connect, and described the 3rd metal level and described the first metal layer electrically connect.
Compared to prior art; semiconductor package of the present invention is by being provided with first protective layer, the first metal layer, second protective layer, second metal level and the 3rd metal level to realize the package design of redistribution layer; semiconductor package of the present invention can be applicable to the IC chip design of high-speed high frequency, makes it be able to the control characteristic impedance to see through the redistribution layer.In addition, semiconductor package provided by the present invention and manufacture method thereof can reduce spurious impedance and inductance value in the package design that redistributes layer.Design of the present invention also can help to reduce the thermal resistance value of redistribution layer package design, and preferable heat radiation approach is provided, and then improves the Reliability of packaging body inner assembly.
Description of drawings
Fig. 1 is the structural representation of semiconductor package manufacture method according to the present invention after first protective layer forms.
Fig. 2 is the structural representation of semiconductor package manufacture method according to the present invention after the first metal layer forms.
Fig. 3 is the structural representation of semiconductor package manufacture method according to the present invention after second protective layer forms.
Fig. 4 is the structural representation of semiconductor package manufacture method according to the present invention after second metal level forms.
Fig. 5 is the structural representation of semiconductor package manufacture method according to the present invention after the 3rd protective layer forms.
Fig. 6 is the semiconductor package schematic diagram after manufacturing is finished according to the inventive method.
Embodiment
Below will cooperate the graphic semiconductor package of the present invention that illustrates, and in conjunction with Fig. 1 to structural representation shown in Figure 6, semiconductor package of the present invention and manufacture method thereof are described in detail.This be noted that especially " on " and D score be meant the direction shown in the correlative type at this, mainly be to cooperate the explanation of this paper and tentative direction vocabulary, be not used for limiting the present invention.
Fig. 1 schematically demonstrates the manufacture method of the semiconductor package according to the present invention and forms structure after first protective layer.As shown in Figure 1, at first providing semiconductor base material 1, can be a wafer for example, has a surface 100, has at least one first connection pad 10 and at least one second connection pad 20 on it.Then form on the surface 100 that one first protective layer 101 covers this semiconductor substrate 1, and expose outside this first connection pad 10 and this second connection pad 20.The material of this first protective layer 101 can be benzocyclobutene (Benzo-Cyclo-Butence; BCB) or Polyimide (Polyimide), but not as limit.This first connection pad 10 is signal input and output, and this second connection pad 20 is an earth terminal.
Then, as shown in Figure 2, on first protective layer 101, form a first metal layer 201, and make this first metal layer 201 and this second connection pad 20 form electric connection.In addition, this first metal layer 201 exposes also around this first connection pad 10, and the isolation that is electrically insulated of this first metal layer 201 and this first connection pad 10.The material of this first metal layer 201 be selected from include gold, silver, copper and etc. the group of alloy.
Then, as shown in Figure 3, on the first metal layer 201, form one second protective layer 102, and expose the part the first metal layer 201 that this first connection pad 10 reaches round this first connection pad 10.The material of this second protective layer 102 can be benzocyclobutene (Benzo-Cyclo-Butence; BCB) or Polyimide (Polyimide), but not as limit.
Then as shown in Figure 4, on second protective layer 102, form one second metal level 202, and expose second protective layer 102 of part, and second metal level 202 electrically connects this first connection pad 10.In addition, form one the 3rd metal level 203 on this second protective layer 102, itself and this first metal layer 201 electrically connects, and exposes second protective layer 102 of part.This second metal level 202 be one the redistribution metal level, the 3rd metal level then can be used as the projection bottom metal layers (Under Bump Metallurgy, UBM).The material of this second metal level 202 and the 3rd metal level 203 be selected from include gold, silver, copper and etc. the group of alloy.The formation of this second metal level 202 and the 3rd metal level 203 can see through and form one the 4th metal level (not shown) on second protective layer; again the 4th metal level is implemented patterning (Patternizing) operation; and a part of material of the 4th metal level is got rid of on second protective layer 102, make all the other materials reside on second protective layer the 4th metal level on 102 form second metal level 202 and the 3rd metal level 203 respectively.
After second metal level 202 and 203 formation of the 3rd metal level; on second protective layer 102, form one the 3rd protective layer 103; as shown in Figure 5; the 3rd protective layer 103 covers part, this second metal level 202 and the 3rd metal level 203 that exposes in this second protective layer 102, and exposes this second metal level 202 of part and part the 3rd metal level 203.The material of the 3rd protective layer 103 can be benzocyclobutene (Benzo-Cyclo-Butence; BCB) or Polyimide (Polyimide), but not as limit.
Fig. 6 is the schematic diagram of the semiconductor package according to the present invention, and it is on the semi-finished product structure shown in Figure 5 solder bump 60 to be arranged on the part that second metal level 202 and the 3rd metal level 203 expose.
Comprehensively the above the invention provides a kind of semiconductor package and manufacture method thereof, and it can be applicable to the IC chip design of high-speed high frequency, makes it be able to the control characteristic impedance to see through the redistribution layer.
In addition, semiconductor package provided by the present invention and manufacture method thereof can reduce spurious impedance and inductance value in the package design that redistributes layer.Design of the present invention also can help to reduce the thermal resistance value of redistribution layer package design, and preferable heat radiation approach is provided, and then improves the Reliability of packaging body inner assembly.
Claims (7)
1. a semiconductor package includes the semiconductor base material, and described semiconductor substrate has a surface, has at least one first connection pad and at least one second connection pad on described surface; It is characterized in that: described semiconductor package also includes: one first protective layer, a first metal layer, one second protective layer, one second metal level, one the 3rd metal level and one the 3rd protective layer, wherein said first protective layer covers on the described semi-conductive surface, and exposes outside described first connection pad and described second connection pad; Described the first metal layer is formed on described first protective layer, and electrically connects with described second connection pad, and described the first metal layer exposes and surrounds described first connection pad, and is electrically insulated with described first connection pad; Described second protective layer is formed on the described the first metal layer, and exposes described first connection pad and part the first metal layer; Described second metal level is formed on described second protective layer and electrically connects described first connection pad; Described the 3rd metal level is described to be formed on described second protective layer, and electrically connects with described the first metal layer; Described the 3rd protective layer is formed on described second protective layer, and described the 3rd protective layer covers described second protective layer, described second metal level and described the 3rd metal level, and exposes part second metal level and part the 3rd metal level.
2. semiconductor package as claimed in claim 1 is characterized in that: the material of described the first metal layer is selected from the group that includes gold, silver, copper and alloy thereof.
3. semiconductor package as claimed in claim 1 is characterized in that: described first connection pad is signal input and output, and described second connection pad is an earth terminal.
4. the manufacture method of a semiconductor package comprises following steps:
The semiconductor base material is provided, and described semiconductor substrate has a surface, is provided with one first connection pad and one second connection pad on described surface;
It is characterized in that: the manufacture method of described semiconductor package also includes following steps:
Form one first protective layer on the surface of described semiconductor substrate, described first protective layer covers the surface of described semiconductor substrate, and exposes described first connection pad and described second connection pad;
Form a first metal layer on described first protective layer, described the first metal layer and described second connection pad electrically connect, and described the first metal layer exposes and surrounds described first connection pad, and is electrically insulated with described first connection pad;
Form one second protective layer on described the first metal layer, described second protective layer exposes described first connection pad and part the first metal layer;
On described second protective layer, form one the 4th metal level; And
Described the 4th metal level of patterning, to form one second metal level and one the 3rd metal level, wherein said second metal level and described first connection pad electrically connect, and described the 3rd metal level and described the first metal layer electrically connect; And
Form one the 3rd protective layer on described second protective layer, described the 3rd protective layer covers described second protective layer, described second metal level and described the 3rd metal level, and expose portion second metal level and part the 3rd metal level.
5. the manufacture method of semiconductor package as claimed in claim 4 is characterized in that: described first connection pad is signal input and output, and described second connection pad is an earth terminal.
6. the manufacture method of semiconductor package as claimed in claim 4, it is characterized in that: described the 3rd metal level is the projection bottom metal layers, described second metal level is the redistribution metal level.
7. the manufacture method of semiconductor package as claimed in claim 6 is characterized in that: described method further includes a step that electrically connects a solder bump on part second metal level that exposes and part the 3rd metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100878082A CN101252107B (en) | 2008-03-20 | 2008-03-20 | Semiconductor package structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100878082A CN101252107B (en) | 2008-03-20 | 2008-03-20 | Semiconductor package structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101252107A CN101252107A (en) | 2008-08-27 |
| CN101252107B true CN101252107B (en) | 2011-08-31 |
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| CN2008100878082A Active CN101252107B (en) | 2008-03-20 | 2008-03-20 | Semiconductor package structure and manufacturing method thereof |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866899A (en) * | 2009-04-20 | 2010-10-20 | 奇景光电股份有限公司 | Semiconductor device |
| CN102623415A (en) * | 2012-04-19 | 2012-08-01 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacturing method thereof |
| TWI716106B (en) * | 2019-09-16 | 2021-01-11 | 力成科技股份有限公司 | Resistance measuring method of package substrate and package substrate thereof |
| US11063011B1 (en) * | 2020-02-20 | 2021-07-13 | Nanya Technology Corporation | Chip and wafer having multi-layered pad |
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