JP2005539403A5 - - Google Patents
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- JP2005539403A5 JP2005539403A5 JP2004568930A JP2004568930A JP2005539403A5 JP 2005539403 A5 JP2005539403 A5 JP 2005539403A5 JP 2004568930 A JP2004568930 A JP 2004568930A JP 2004568930 A JP2004568930 A JP 2004568930A JP 2005539403 A5 JP2005539403 A5 JP 2005539403A5
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- Prior art keywords
- package
- packages
- substrate
- stacked
- module
- Prior art date
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- 239000000758 substrate Substances 0.000 claims 25
- 239000000463 material Substances 0.000 claims 3
Claims (14)
第2パッケージ基板上に少なくとも1つのダイスを有する第2パッケージを前記第1パッケージの上に配置し、
前記第1および第2基板間においてワイヤボンドz軸相互接続を形成することを特徴とするマルチパッケージの形成方法。 Providing a first package having at least one die on a first package substrate;
A second package having at least one die on a second package substrate is disposed on the first package;
Forming a wire bond z-axis interconnect between the first and second substrates;
第1パッケージ基板を具備するBGA第1パッケージを供給し、
第2パッケージ基板を具備する第2パッケージを供給し、前記第1パッケージ上に第2パッケージを積み重ね、そして
前記第1および第2基板をワイヤボンド接続することにより、前記第1および第2パッケージを電気的に相互接続することを特徴とするマルチパッケージモジュールの形成方法。 A method for forming a multi-package module, comprising:
Supplying a BGA first package having a first package substrate;
Supplying a second package comprising a second package substrate, stacking the second package on the first package, and wire-bonding the first and second substrates to form the first and second packages; A method of forming a multi-package module, characterized by being electrically interconnected.
遮蔽材を有する第1パッケージを供給し、
第2パッケージを供給し、
前記遮蔽材の略平面な上側表面に前記第2パッケージを積み重ね、そして、
前記第1および第2パッケージをワイヤボンドにより電気的に相互接続することを特徴とするマルチパッケージモジュールの形成方法。 A method of forming a multi-package module comprising a second package stacked on a first package, comprising:
Providing a first package having a shielding material;
Supply the second package,
Stacking the second package on a substantially planar upper surface of the shield; and
A method of forming a multi-package module, wherein the first and second packages are electrically interconnected by wire bonding.
ダイスおよび第2パッケージ基板を有する第2パッケージを供給し、前記第1パッケージ上に前記第2パッケージを積み重ね、
前記第1パッケージ基板と第2パッケージ基板とをワイヤボンド接続することにより、前記第1および第2パッケージを電気的に相互接続することを特徴とするマルチパッケージモジュールの形成方法。 Providing an upward die flip chip first package having a first package substrate;
Providing a second package having a die and a second package substrate, and stacking the second package on the first package;
A method of forming a multi-package module, wherein the first and second packages are electrically interconnected by wire-bonding the first package substrate and the second package substrate.
ダイスおよび第2パッケージ基板を有する第2パッケージを供給し、前記第1パッケージ上に前記第2パッケージを積み重ね、そして
前記第1パッケージ基板と前記第2パッケージ基板とをワイヤボンド接続することにより、前記第1および第2パッケージを電気的に相互接続することを特徴とするマルチパッケージモジュールの形成方法。 Supplying a downward facing die flip chip first package having a first package substrate;
Providing a second package having a die and a second package substrate, stacking the second package on the first package, and wire bonding the first package substrate and the second package substrate; A method of forming a multi-package module, wherein the first and second packages are electrically interconnected.
第2パッケージを供給し、
前記第1パッケージ上に前記第2パッケージを積み重ね、そして、
ワイヤボンディングにより前記第1パッケージおよび第2パッケージ間の電気的相互接続を形成することを特徴とするマルチパッケージモジュールの形成方法。 Supply the first package of stacked dies,
Supply the second package,
Stacking the second package on the first package; and
A method of forming a multi-package module, comprising forming an electrical interconnection between the first package and the second package by wire bonding.
Applications Claiming Priority (15)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41159002P | 2002-09-17 | 2002-09-17 | |
US60/411,590 | 2002-09-17 | ||
US10/632,553 | 2003-08-02 | ||
US10/632,550 | 2003-08-02 | ||
US10/632,552 | 2003-08-02 | ||
US10/632,551 US6838761B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US10/632,549 US7064426B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages |
US10/632,552 US20040061213A1 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
US10/632,568 | 2003-08-02 | ||
US10/632,551 | 2003-08-02 | ||
US10/632,550 US6972481B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
US10/632,568 US7205647B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
US10/632,553 US7053476B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
US10/632,549 | 2003-08-02 | ||
PCT/US2003/028919 WO2004027823A2 (en) | 2002-09-17 | 2003-09-15 | Semiconductor multi-package module having wire bond interconnection between stacked packages |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011137096A Division JP5602685B2 (en) | 2002-09-17 | 2011-06-21 | Multi-package module and method for forming the same |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005539403A JP2005539403A (en) | 2005-12-22 |
JP2005539403A5 true JP2005539403A5 (en) | 2006-11-02 |
JP4800625B2 JP4800625B2 (en) | 2011-10-26 |
Family
ID=32034538
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004568930A Expired - Fee Related JP4800625B2 (en) | 2002-09-17 | 2003-09-15 | Semiconductor multi-package module having wire bond interconnection between stacked packages and method of forming the same |
JP2011137096A Expired - Lifetime JP5602685B2 (en) | 2002-09-17 | 2011-06-21 | Multi-package module and method for forming the same |
JP2013123601A Expired - Lifetime JP5856103B2 (en) | 2002-09-17 | 2013-06-12 | Semiconductor multi-package module having wire bond interconnections between stacked packages |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011137096A Expired - Lifetime JP5602685B2 (en) | 2002-09-17 | 2011-06-21 | Multi-package module and method for forming the same |
JP2013123601A Expired - Lifetime JP5856103B2 (en) | 2002-09-17 | 2013-06-12 | Semiconductor multi-package module having wire bond interconnections between stacked packages |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1547141A4 (en) |
JP (3) | JP4800625B2 (en) |
KR (1) | KR101166575B1 (en) |
AU (1) | AU2003272405A1 (en) |
TW (3) | TWI378548B (en) |
WO (1) | WO2004027823A2 (en) |
Families Citing this family (24)
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US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
US7429787B2 (en) * | 2005-03-31 | 2008-09-30 | Stats Chippac Ltd. | Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides |
US7394148B2 (en) | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
SG130055A1 (en) | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
JP5522561B2 (en) * | 2005-08-31 | 2014-06-18 | マイクロン テクノロジー, インク. | Microelectronic device package, stacked microelectronic device package, and method of manufacturing microelectronic device |
US8198735B2 (en) | 2006-12-31 | 2012-06-12 | Stats Chippac Ltd. | Integrated circuit package with molded cavity |
US8124451B2 (en) | 2007-09-21 | 2012-02-28 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
KR20110124065A (en) | 2010-05-10 | 2011-11-16 | 하나 마이크론(주) | Stack type semiconductor package |
KR20110124063A (en) | 2010-05-10 | 2011-11-16 | 하나 마이크론(주) | Stack type semiconductor package |
KR101688005B1 (en) * | 2010-05-10 | 2016-12-20 | 삼성전자주식회사 | Semiconductor package having dual land and related device |
TWI406377B (en) * | 2010-12-27 | 2013-08-21 | Powertech Technology Inc | Ball grid array package with three-dimensional pin 1 mark and its manufacturing method |
US9165906B2 (en) | 2012-12-10 | 2015-10-20 | Invensas Corporation | High performance package on package |
JP6128993B2 (en) | 2013-06-28 | 2017-05-17 | キヤノン株式会社 | Multilayer semiconductor device, printed circuit board, electronic device, and method of manufacturing multilayer semiconductor device |
KR101563910B1 (en) * | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | EMI shielding device for semiconductor package and method for manufacturing the same |
US9995641B2 (en) * | 2013-10-30 | 2018-06-12 | Honeywell International Inc. | Force sensor with gap-controlled over-force protection |
JP6357371B2 (en) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | Lead frame, semiconductor device, and lead frame manufacturing method |
US9666730B2 (en) | 2014-08-18 | 2017-05-30 | Optiz, Inc. | Wire bond sensor package |
KR101961377B1 (en) * | 2015-07-31 | 2019-03-22 | 송영희 | Land Grid Array semiconductor package |
KR101799668B1 (en) * | 2016-04-07 | 2017-11-20 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and manufacturing method thereof |
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KR102283390B1 (en) | 2019-10-07 | 2021-07-29 | 제엠제코(주) | Semiconductor package for multi chip and method of fabricating the same |
KR102325217B1 (en) | 2020-05-18 | 2021-11-11 | 제엠제코(주) | Multi die stack semiconductor package |
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-
2003
- 2003-09-15 KR KR1020057004551A patent/KR101166575B1/en active IP Right Grant
- 2003-09-15 WO PCT/US2003/028919 patent/WO2004027823A2/en active Application Filing
- 2003-09-15 EP EP03754585A patent/EP1547141A4/en not_active Ceased
- 2003-09-15 AU AU2003272405A patent/AU2003272405A1/en not_active Abandoned
- 2003-09-15 JP JP2004568930A patent/JP4800625B2/en not_active Expired - Fee Related
- 2003-09-17 TW TW098139252A patent/TWI378548B/en not_active IP Right Cessation
- 2003-09-17 TW TW092125625A patent/TWI329918B/en active
- 2003-09-17 TW TW100113640A patent/TWI469301B/en not_active IP Right Cessation
-
2011
- 2011-06-21 JP JP2011137096A patent/JP5602685B2/en not_active Expired - Lifetime
-
2013
- 2013-06-12 JP JP2013123601A patent/JP5856103B2/en not_active Expired - Lifetime
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