CN102543939A - Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof - Google Patents
Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof Download PDFInfo
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- CN102543939A CN102543939A CN2012100120606A CN201210012060A CN102543939A CN 102543939 A CN102543939 A CN 102543939A CN 2012100120606 A CN2012100120606 A CN 2012100120606A CN 201210012060 A CN201210012060 A CN 201210012060A CN 102543939 A CN102543939 A CN 102543939A
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- scolder
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- lamination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Abstract
The invention discloses a laminated inverted chip packaging structure for superfine-pitch welding pads and a manufacturing method of the structure. According to the embodiment of the invention, the laminated inverted chip packaging structure comprises a substrate, a plurality of chips which are vertically laminated, and a plurality of conductive posts, wherein a plurality of welding pads are arranged on the substrate; a welding pad is arranged on each chip; the plurality of conductive posts are arranged between the chip and the substrate; the substrate welding pads are electrically connected with the chip welding pads through the conductive posts; and some of the conductive posts are vertically laminated together. By adopting the laminated inverted chip packaging structure for the superfine-pitch welding pads according to the embodiment of the invention, requirements on the superfine-pitch welding pads of the vertically-laminated inverted chip can be met at the same time.
Description
Technical field
The present invention relates to the structure and the manufacturing approach of the interconnection of a kind of Electronic Packaging chips and substrate, relate in particular to a kind of slim encapsulating structure of lamination flip-chip small size and manufacturing approach thereof of ultra fine-pitch pad.
Background technology
As shown in Figure 1; In traditional stacked package structure that comprises two-layer flip-chip; Interconnection between chip bonding pad and the substrate pads normally upper strata chip 2 is connected with substrate 100 pads through bigger spherical solder bump, and lower floor's chip 1 is connected with substrate pads through less spherical solder bump.
In the stacked package structure that overcomes traditional two-layer flip-chip; Solder bump can't be applicable to the problem of ultra fine-pitch pad; The conductive pole interconnection structure has appearred in recent years; Can on lower floor's chip 1, use this conductive pole interconnection structure, perhaps lower floor's chip 1 uses the conductive pole interconnection structure simultaneously with upper strata chip 2.
Iff uses the interconnection of this novel conductive pole on lower floor's chip 1, and upper strata chip 2 can't be applied to the ultra fine-pitch pad less than 150um when still using spherical solder bump interconnect.
If conductive pole interconnection was used in lower floor's chip 1 and 2 last times of upper strata chip simultaneously, is had problems.Because prior art generally can only be accomplished the conductive pole of about 70um height, deduct after the thickness of chip surface protection insulating barrier and substrate surface insulating barrier, the gap d between chip and the substrate will be less than 50um (referring to Fig. 3).But the space (d that need keep 10um simultaneously between lower floor's chip back and the upper strata chip surface at least
2) for connecting the perhaps filling of underfill.The existing chip thinning technology of volume production that can realize is generally 30um thickness, so the thickness T c of lower floor's chip 1 has 30um at least, causes the gap d between lower floor's chip 1 and the substrate 100
1Only remaining less than 10um, this structure is difficult to realize at present.
Summary of the invention
The object of the present invention is to provide a kind of flip-chip stacked package structure of ultra fine-pitch pad, can satisfy the requirement of the ultra fine-pitch pad of lamination flip-chip up and down simultaneously.
To achieve these goals, according to embodiments of the invention, a kind of lamination flip chip packaging structure is provided, wherein, said lamination flip chip packaging structure comprises: substrate, substrate are provided with a plurality of substrate pads; A plurality of chips of stacked on top are provided with pad on each chip; A plurality of conductive poles; Be arranged between bonding pads and the substrate; Be electrically connected through said a plurality of conductive poles between substrate pads and the chip bonding pad, a part of stacked on top in said a plurality of conductive poles together, the chip of the superiors is electrically connected with substrate through the multilayer conductive post.
The number of plies of the conductive pole that wherein, is provided with on the chip bonding pad is more than or equal to the number of plies of the conductive pole that is provided with on the chip bonding pad that is positioned at this chip below.
Wherein, undermost chip is electrically connected with substrate through one deck conductive pole.
Wherein, each layer chip all includes the pad of spacing less than 150um.
Said a plurality of conductive pole comprises first conductive pole, second conductive pole and the 3rd conductive pole, and second conductive pole is stacked on first conductive pole top, and the 3rd conductive pole is arranged on the undermost chip.
Be connected through scolder between first conductive pole and second conductive pole and between conductive pole and the substrate pads, scolder comprises first scolder, second scolder and the 3rd scolder.
Substrate pads is connected with an end of first conductive pole through first scolder, and substrate pads is passed through the 3rd scolder and is connected with the 3rd conductive pole one end, is connected through second scolder between first conductive pole and second conductive pole.
The fusing point of first scolder is higher more than 50 ℃ than the fusing point of second scolder and the 3rd scolder.
The material of first scolder and second scolder and the 3rd scolder all is a lead-free solder.
This encapsulating structure be used between each layer conductive pole connecting and being used for all scolders that conductive pole is connected with substrate pads, be minimum at fusing point with the set scolder in the direct-connected conductive pole of each layer chip lower end.
The positive landless zone passage electrically non-conductive material adhesion of the back side of lower floor's chip and upper strata chip.
Encapsulant is filled in the gap between chip and the substrate, and has coated each layer scolder and conductive pole.
The material of first conductive pole and second conductive pole and the 3rd conductive pole all is a copper.
Be provided with the UBM layer between a bonding pads and a part or the whole conductive pole.
According to a further aspect in the invention; A kind of method of making aforesaid lamination flip chip packaging structure is provided; Wherein, Said method comprises: after the carrier that will preset first conductive pole is connected on the substrate through Reflow Soldering, separate first conductive pole and carrier, first conductive pole is connected through first scolder be retained on the substrate pads.The landless that the orlop chip back that presets the 3rd conductive pole is mounted the second layer chip on the orlop chip is regional, then layers of chips is mounted on the substrate simultaneously, after Reflow Soldering, forms interconnection structure once more.
Wherein, on the surface of carrier protective layer is set, before separating first conductive pole and carrier, first conductive pole is plated on the protective layer of carrier.
Wherein, adhesion between first conductive pole and first scolder and the adhesion between first scolder and the substrate pads are greater than the adhesion between the protective layer of first conductive pole and carrier.
Use the flip-chip stacked package structure of ultra fine-pitch pad according to an embodiment of the invention, can satisfy the requirement of the ultra fine-pitch pad of lamination flip-chip up and down simultaneously.
Description of drawings
Through below in conjunction with the description carried out of accompanying drawing that an example exemplarily is shown, of the present invention above-mentionedly will become apparent with other purposes and characteristics, wherein:
Fig. 1 all uses the flip chip structure sketch map of spherical solder bump for traditional layers of chips;
Fig. 2 uses spherical solder bump for the upper strata chip, and lower floor's chip uses the conductive pole structural representation;
Fig. 3 all uses the structural representation of individual layer conductive pole for layers of chips up and down;
Fig. 4 is stacked package structural representation according to an embodiment of the invention;
Fig. 5 mounts the sketch map on the substrate for the carrier that will preset first conductive pole;
Fig. 6 is that the carrier that has preset first conductive pole forms the sketch map that is connected with substrate after refluxing for the first time;
The sketch map of Fig. 7 for carrier is separated with first conductive pole, wherein, first conductive pole is stayed on the substrate pads;
Fig. 8 for carrier with after first conductive pole separates, the sketch map at the first conductive pole top of substrate one side;
Fig. 9 for carrier with after first conductive pole separates, the sketch map of carrier one side;
The sketch map in the positive landless of the large chip that Figure 10 has preset second conductive pole for the little chip back that will preset the 3rd conductive pole mounts zone;
Figure 11 is for to mount the sketch map on the substrate with lower floor's chip and upper strata chip together;
Figure 12 is the back formation interconnection structure sketch map that refluxes for the first time;
The chip structure sketch map of Figure 13 for accomplishing after the plastic packaging engineering.
Embodiment
Can use the relation of coming easily element shown in the description figure or characteristic and other elements or characteristic such as spatial relationship terms such as " in ... below ", " lower floor ", " in ... top ", " upper stratas " in the present invention.Should be appreciated that the orientation of in accompanying drawing, describing that the spatial relationship term also is intended to comprise the different azimuth of device in using or operating.For example, if the device in accompanying drawing upset, then be described as be in other elements or characteristic " below " or " under " the orientation of element will be positioned in " top " of other elements or characteristic subsequently.Therefore, exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.Device can be positioned at other orientation (revolve and turn 90 degrees perhaps in other orientation), and then spatial relationship descriptor used herein should correspondingly be explained.
Below, specify embodiments of the invention with reference to accompanying drawing.
Fig. 4 is stacked package structural representation according to an embodiment of the invention.As shown in Figure 4, the stacked package structure comprises according to an embodiment of the invention: substrate 100, and substrate 100 is provided with a plurality of pads; Two chips 1,2 of stacked on top (be not limited to two, can have the upper and lower chip more than three that piles up according to encapsulating structure of the present invention) are provided with a plurality of pads on chip 1 and the chip 2; Conductive pole is arranged between chip 1,2 and the substrate 100, is electrically connected through said conductive pole between substrate pads and the chip bonding pad.
Further; According to one embodiment of present invention; Chip 1 more near substrate 100 (can chip 1 be called lower floor's chip, chip 2 is called the upper strata chip), only is provided with one deck the 3rd conductive pole 5 than chip 2 between chip 1 and the substrate 100; And the following of chip 2 can be provided with two-layer conductive pole, is respectively first conductive pole 3 and second conductive pole 4.
If this stacked package structure comprises more chip, the position leans on more the chip of top to be connected with substrate through the conductive pole of multilayer more.According to embodiments of the invention, the chip of the superiors is electrically connected with substrate through the multilayer conductive post at least.The number of plies of the conductive pole of arbitrary layer chip setting is more than or equal to the number of plies of the conductive pole of the chip setting that is positioned at this layer chip below.
The conductive pole cross sectional shape can be for square or circular, and have no special requirements.
Lower floor's chip 1 all includes the ultra fine-pitch pad of spacing less than 150um with upper strata chip 2.Substrate pads is connected with first conductive pole, 3 one ends through first scolder 6, and first conductive pole, 3 other ends are connected with second conductive pole 4 through second scolder 7, and second conductive pole, 4 other ends lean on the pad of last chip 2 to be connected with the position.
Substrate pads is connected with the 3rd conductive pole 5 one ends through the 3rd scolder 8, and the 3rd conductive pole 5 other ends are connected with the pad of lower floor chip 1.The positive landless zone passage electrically non-conductive material adhesion of the back side of lower floor's chip 1 and upper strata chip 2.
Encapsulant 12 has been filled in the gap between chip and the substrate, and has coated first scolder, 6, the first conductive poles, 3, the second scolders, 7, the second conductive poles, 4, the three scolders, 8, the three conductive poles 5.
In addition, can be distributed with soldered ball in the lower surface of substrate, to be electrically connected with other components and parts.
The material of the first conductive pole material 3 and second conductive pole 4 and the 3rd conductive pole 5 all can be Cu.
The first and second and the 3rd solder material can be unleaded (that is, lead content must reduce to the level that is lower than 1000ppm).
UBM layer 10 (salient point bottom metal layer, under bump metal) is arranged between the pad of upper strata chip 2 and/or lower floor's chip 1 and the partially conductive post.The UBM layer can guarantee the adhibit quality of flange and pad and prevent intermetallic counterdiffusion mutually.
Can be than the fusing point of second scolder 4 and the 3rd scolder 8 high 50 ℃ or more of the fusing point of first scolder 6.
Fig. 5-Figure 13 shows the manufacturing approach of the flip-chip stacked package structure of ultra fine-pitch pad according to an embodiment of the invention.
Fig. 5 mounts the sketch map on the substrate for the carrier that will preset first conductive pole; Fig. 6 is that the carrier that has preset first conductive pole forms the sketch map that is connected with substrate after refluxing for the first time; The sketch map of Fig. 7 for carrier is separated with first conductive pole, wherein, first conductive pole is stayed on the substrate pads.
As shown in Figure 5, the conductive pole carrier 9 that presets first conductive pole 3 and first scolder 6 is mounted on the substrate.Existing ripe flipchip-bumped manufacture craft can be implemented in and plates conductive pole and scolder on the carrier 9 one by one; Specifically; The protective layer that does not produce metallurgical binding with metal is set on the surface of carrier 9 in advance; Behind polymeric coating layers such as coating polyimide, carry out the flipchip-bumped manufacture craft again, can make and keep extremely low adhesion between the protective layer of first conductive pole 3 and carrier 9.Form the firm metallurgical binding between first scolder 6 and first conductive pole 3 through technologies such as Reflow Solderings again.
Then, as shown in Figure 6, after refluxing once more, make the carrier 9 that has first conductive pole 3 and first scolder 6 form scolder and be connected with substrate 100.
As shown in Figure 7, the carrier of separating 9 and first conductive pole 3.Specifically; Through behind the reflow soldering process, between first conductive pole 3 and first scolder 6, and between first scolder 6 and the substrate pads; All formed firm metallurgical binding; Adhesion between them is far longer than the adhesion between the protective layer of first conductive pole 3 and carrier 9, so just is easy to realize separating between first conductive pole 3 and the carrier 9, and the conductive pole 3 of winning is retained on the substrate pads.Fig. 8 for carrier with after first conductive pole 3 separates, the sketch map at first conductive pole, 3 tops of substrate one side, Fig. 9 for carrier 9 with after first conductive pole 3 separates, the sketch map of carrier 9 one sides.Fig. 8 and Fig. 9 only are examples, and the distribution of first conductive pole 3 is not limited to the shape shown in Fig. 8 and Fig. 9.
Figure 10 mounts the sketch map in upper strata chip 2 positive landless zones for the back side with lower floor's chip 1.Figure 11 is for to mount the sketch map on the substrate with lower floor's chip and upper strata chip together; Figure 12 is the back formation interconnection structure sketch map that refluxes for the first time; The chip structure sketch map of Figure 13 for carrying out accomplishing after plastic packaging (Mold) engineering.
Shown in Figure 10-13, the back side of the chip 1 that has preset the 3rd conductive pole 5 is mounted the landless zone in chip 2 fronts of having preset second conductive pole 4 through electrically non-conductive material 11.Upper strata chip 2 and lower floor's chip 1 with being mounted on together mount on the substrate that has first conductive pole 3, and second conductive pole 4 are alignd with first conductive pole 3, and after the backflow, the pad of chip 1, chip 2 and the pad of substrate form interconnection.
Also melt for fear of first scolder 6 in the process of this Reflow Soldering, thereby cause first conductive pole 3 crooked and can not align with second conductive pole 4, the fusing point that possibly make first scolder 6 is higher 50 ℃ or more than the fusing point of second scolder 7 and the 3rd scolder 8.
Under certain temperature and pressure condition, encapsulants such as epoxy resin 12 are injected at last, encapsulant 12 has been filled in the gap between chip and the substrate, and has coated first scolder 6; First conductive pole, 3, the second scolders, 7, the second conductive poles 4; The 3rd scolder 8; The 3rd conductive pole 5, thereby final molding are accomplished plastic packaging (Mold).
Make three layers or the stacked package structure of multilayer chiop more if desired, the first more conductive pole then need be set on substrate.With four layers of chip is example; On outer first conductive pole, pile up the 4th conductive pole; The 3rd layer of chip that inner the 4th conductive pole is about to be used for being provided with the 5th conductive pole is connected; Above outer the 4th conductive pole, pile up the 6th conductive pole again, the 4th layer of chip that the 6th conductive pole is about to be used for being provided with the 7th conductive pole is connected.On the other hand; The ground floor chip that is provided with the 3rd conductive pole, the second layer chip that is provided with second conductive pole, the 4th layer of chip that is provided with the 3rd layer of chip of the 5th conductive pole and is provided with the 7th conductive pole are bonded together through electrically non-conductive material, four layers of chip that will bond together then be provided with first conductive pole, the 4th conductive pole and the substrate pads of the 6th conductive pole and be connected through reflux technique.Know according to foregoing reason, with the direct-connected conductive pole of each layer chip on the fusing point of set scolder in all scolders, be minimum because they are in the last reflow process.
The stacked package structure of multilayer more.
In addition, can be distributed with soldered ball in the lower surface of substrate, to be electrically connected with other components and parts.
Though described exemplary embodiment of the present invention above in detail, have common practise person in the technical field under the present invention and do not breaking away from the spirit and scope of the present invention, can make various modifications, retouching and modification to embodiments of the invention.But should be appreciated that In the view of those skilled in the art these modifications, retouching and modification will fall in the spirit and scope of the exemplary embodiment of the present invention that claim limits.
At last, only if point out here or other and the obvious contradiction of context, otherwise the step of all methods described herein can be carried out with the order of any appropriate.
Claims (17)
1. lamination flip chip packaging structure, wherein, said lamination flip chip packaging structure comprises:
Substrate, substrate are provided with a plurality of substrate pads;
A plurality of chips of stacked on top are provided with pad on each chip;
A plurality of conductive poles; Be arranged between bonding pads and the substrate; Be electrically connected through said a plurality of conductive poles between substrate pads and the chip bonding pad, a part of stacked on top in said a plurality of conductive poles together, the chip of the superiors is electrically connected with substrate through the multilayer conductive post.
2. lamination flip chip packaging structure according to claim 1, wherein, the number of plies of the conductive pole that is provided with on the chip bonding pad is more than or equal to the number of plies of the conductive pole that is provided with on the chip bonding pad that is positioned at this chip below.
3. lamination flip chip packaging structure according to claim 1 and 2, wherein, undermost chip is electrically connected with substrate through one deck conductive pole.
4. lamination flip chip packaging structure according to claim 1 and 2, wherein, each layer chip all includes the pad of spacing less than 150um.
5. lamination flip chip packaging structure according to claim 1 and 2; Said a plurality of conductive pole comprises first conductive pole, second conductive pole and the 3rd conductive pole; Second conductive pole is stacked on first conductive pole top, and the 3rd conductive pole is arranged on the undermost chip.
6. lamination flip chip packaging structure according to claim 5, wherein,
Be connected through scolder between first conductive pole and second conductive pole and between conductive pole and the substrate pads, scolder comprises first scolder, second scolder and the 3rd scolder.
7. lamination flip chip packaging structure according to claim 6, wherein,
Substrate pads is connected with an end of first conductive pole through first scolder, and substrate pads is passed through the 3rd scolder and is connected with the 3rd conductive pole one end, is connected through second scolder between first conductive pole and second conductive pole.
8. according to claim 6 or 7 described lamination flip chip packaging structures, wherein,
The fusing point of first scolder is higher more than 50 ℃ than the fusing point of second scolder and the 3rd scolder.
9. according to claim 6 or 7 described lamination flip chip packaging structures, wherein,
The material of first scolder and second scolder and the 3rd scolder all is a lead-free solder.
10. lamination flip chip packaging structure according to claim 1 and 2, wherein,
This encapsulating structure be used between each layer conductive pole connecting and being used for all scolders that conductive pole is connected with substrate pads, be minimum at fusing point with the set scolder in the direct-connected conductive pole of each layer chip lower end.
11. lamination flip chip packaging structure according to claim 1 and 2, wherein,
The positive landless zone passage electrically non-conductive material adhesion of the back side of lower floor's chip and upper strata chip.
12. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Encapsulant is filled in the gap between chip and the substrate, and has coated each layer scolder and conductive pole.
13. lamination flip chip packaging structure according to claim 1 and 2, wherein,
The material of first conductive pole and second conductive pole and the 3rd conductive pole all is a copper.
14. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Be provided with the UBM layer between a bonding pads and a part or the whole conductive pole.
15. the method for each described lamination flip chip packaging structure among manufacturing such as the claim 1-14, wherein, said method comprises:
After being connected on the substrate through Reflow Soldering the carrier that presets first conductive pole, separate first conductive pole and carrier, first conductive pole connected through first scolder be retained on the substrate pads,
The orlop chip back that presets the 3rd conductive pole is mounted the landless zone of the second layer chip on the orlop chip; Mount layers of chips on the substrate simultaneously then; Second conductive pole on the second layer chip is alignd with first conductive pole, after Reflow Soldering, make chip and substrate form interconnection once more.
16. method according to claim 15 wherein, is provided with protective layer on the surface of carrier, before separating first conductive pole and carrier, first conductive pole is plated on the protective layer of carrier.
17. method according to claim 16, wherein, adhesion between first conductive pole and first scolder and the adhesion between first scolder and the substrate pads are greater than the adhesion between the protective layer of first conductive pole and carrier.
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| CN201210012060.6A CN102543939B (en) | 2012-01-05 | 2012-01-05 | The lamination flip chip packaging structure of ultra fine-pitch pad and manufacture method thereof |
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