CN101989593A - Packaging substrate as well as manufacturing method and packaging structure thereof - Google Patents
Packaging substrate as well as manufacturing method and packaging structure thereof Download PDFInfo
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- CN101989593A CN101989593A CN 200910165563 CN200910165563A CN101989593A CN 101989593 A CN101989593 A CN 101989593A CN 200910165563 CN200910165563 CN 200910165563 CN 200910165563 A CN200910165563 A CN 200910165563A CN 101989593 A CN101989593 A CN 101989593A
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- electric contact
- contact mat
- metal coupling
- substrate body
- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a packaging substrate as well as a manufacturing method and a packaging structure thereof, providing a substrate body. At least one surface of the substrate body is provided with multiple electric contact pads and lines; insulating layers for covering are formed on the electric contact pads, the lines and the surface of the substrate body; the thickness of the insulating layer is less than the thickness of the electric contact pad; multiple insulating layer open pores correspondingly exposed out of each electric contact pad are formed; a first metal lug is formed on the upper surface exposed out of each electric contact pad so as to be beneficial to the easy control of the welding flux quantity and further beneficial to packaging of thin intervals; a welding preventing layer is not required to be formed on the substrate; and the electric contact pads and the lines are not required to carry out a coursing and manufacturing process so as to maintain a good shape, thus the substrate has good yield and reliability.
Description
Technical field
The present invention relates to a kind of base plate for packaging and method for making thereof and encapsulating structure, particularly relate to a kind of base plate for packaging and encapsulating structure and method for making thereof that does not need on substrate, to form welding resisting layer.
Background technology
In existing crystal covering type (flip chip) semiconductor packaging, be on semiconductor chip, to be provided with a plurality of electronic padses, respectively be provided with metal coupling on this electronic pads, and provide a base plate for packaging with a plurality of electric contact mats, and electrically connect described metal coupling and electric contact mat with correspondence by scolder.
Engage (Wire Bond) technology than traditional routing, Flip Chip is characterised in that the electric connection between semiconductor chip and base plate for packaging is with metal coupling for it but not general gold thread, and the advantage of this kind Flip Chip is to improve packaging density to reduce the potted element size; Simultaneously, this kind Flip Chip need not use the longer gold thread of length, and can improve the performance that electrically connects to reduce impedance.
Because the miniaturization of increasing product design trend, therefore, Flip Chip is also several towards height output/input (I/O), the trend development of thin space.Yet along with dwindling of metal coupling spacing (pitch), the reliability of base plate for packaging and yield are difficult for keeping original level.
Seeing also Figure 1A to Fig. 1 D, is the cross-sectional schematic of the method for making of a kind of existing encapsulating structure of explanation.
Shown in Figure 1A, a substrate body 10 is provided, its at least one surperficial 10a has a plurality of electric contact mats 112 and circuit 111.
Shown in Figure 1B, on this substrate body 10, form welding resisting layer (solder mask) 12, be formed with a welding resisting layer perforate 120 that exposes outside these electric contact mats 112 and part circuit 111 in this welding resisting layer 12.
Shown in Fig. 1 C, respectively forming scolder 14 on this electric contact mat 112.
Shown in Fig. 1 D, above this substrate body 10, connect and put semiconductor chip 20 with acting surface 20a, and the acting surface 20a of this semiconductor chip 20 has a plurality of electronic padses 21, respectively be provided with metal coupling 22 on this electronic pads 21, making these metal couplings 22 be electrically connected to respectively this electric contact mat 112 with correspondence by scolder 14 '.
Yet, in the method for making of existing encapsulating structure, when on this electric contact mat 112 respectively, forming scolder 14, and the amount of difficult this scolder 14 of precisely control, often make the amount too much (for example scolder 14 on Fig. 1 C the right) and cause the bridge joint phenomenon of this scolder 14, the perhaps amount of this scolder 14 very few (for example scolder 14 on Fig. 1 C left side) and cause associativity not enough and electrically connect poor effect, problem when this follow-up this semiconductor chip 20 of will deriving encapsulates, for example bridge to next door (as the scolder 14 ' on Fig. 1 D the right) or bad connection (as the scolder 14 ' on Fig. 1 D left side), cause problem generations such as reliability.
Moreover described metal coupling 22 is located at this die terminals, and its cost is higher, and because the scolder 14 on the base plate for packaging only has the thickness of several microns (μ m), formed contact often occurs following bad and reliability issues when the application of high I/O number; In addition, before forming this welding resisting layer 12 on this substrate body 10, usually must carry out the alligatoring manufacturing process, to improve the associativity between this substrate body 10 and this welding resisting layer 12, yet this alligatoring manufacturing process causes this electric contact mat 112 and circuit 111 distortion easily, and then influence whole electrically (especially when high frequency), and will cause the electric connection difficulty of this semiconductor chip 20.
Therefore, how a kind of base plate for packaging and method for making thereof and encapsulating structure are provided, amount of solder of the prior art is wayward, metal coupling is formed on die terminals and must form welding resisting layer on substrate to avoid, and necessary first alligatoring circuit or electric contact mat are with the adhesion of increase with welding resisting layer, thereby cause the linear distortion of circuit, and yield and reliability under the degradation problem, the real present industry urgency problem to be overcome that become.
Summary of the invention
In view of the defective of described prior art, a purpose of the present invention provides a kind of base plate for packaging and method for making and encapsulating structure, can avoid that amount of solder is wayward, degradation problem under yield and the reliability.
Another purpose of the present invention provides a kind of base plate for packaging and method for making and encapsulating structure, and can avoid metal coupling to be brought in by chip entirely provides, and does not need to form on substrate welding resisting layer, to avoid circuit to produce deformation, to reach degradation problem under yield and the reliability.
For reaching described purpose and other purpose, the invention provides a kind of base plate for packaging, comprising: substrate body, its at least one surface has a plurality of electric contact mats and circuit; Insulating barrier is located on the surface of this substrate body, described electric contact mat and the circuit, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this electric contact mat; And a plurality of first metal couplings, correspondence is located at the upper surface of the electric contact mat in this insulating layer perforating respectively, and protrudes in this insulating barrier.
According to described base plate for packaging, described insulating layer perforating can corresponding expose outside respectively part upper surface or whole upper surface of this electric contact mat.
According to described structure, also can comprise scolder or surface-treated layer, be located on this first metal coupling; The material that forms this scolder can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it, and the material that forms this surface-treated layer can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/ElectrolessPalladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
The present invention also provides another kind of base plate for packaging, comprising: substrate body, and its at least one surface has a plurality of electric contact mats and circuit; A plurality of first metal couplings, correspondence are located at respectively on this electric contact mat; And insulating barrier, be located on the surface of this substrate body, described electric contact mat, circuit and first metal coupling, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this first metal coupling.
According to described base plate for packaging, described insulating layer perforating can corresponding expose outside respectively part upper surface or whole upper surface of this first metal coupling.
According to described structure, also can comprise scolder or surface-treated layer, be located on this first metal coupling; The material that forms this scolder can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it, and the material that forms this surface-treated layer can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/ElectrolessPalladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
The present invention provides a kind of method for making of base plate for packaging again, comprising: a substrate body is provided, and its at least one surface has a plurality of electric contact mats and circuit; On described electric contact mat, circuit and this substrate body surface, form insulating barrier, and the thickness of this insulating barrier is less than the thickness of described electric contact mat; In this insulating barrier, form a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this electric contact mat; And form first metal coupling at the upper surface that this electric contact mat respectively exposes.
According to described method for making, described insulating layer perforating can corresponding expose outside respectively part upper surface or whole upper surface of this electric contact mat.
According to the method for making of described base plate for packaging, also can be included in and form scolder or surface-treated layer on this first metal coupling; The material that forms this scolder can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it, and the material that forms this surface-treated layer can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
The present invention also provides the method for making of another kind of base plate for packaging, comprising: a substrate body is provided, and its at least one surface has conductive layer; Form first resistance layer on this conductive layer, this first resistance layer has the open region of a plurality of patternings; Form line layer in these open regions, this line layer comprises a plurality of electric contact mats and circuit; Form second resistance layer on this first resistance layer and line layer, this second resistance layer has a plurality of correspondences and exposes outside the respectively resistance layer perforate of this electric contact mat; Respectively forming first metal coupling in this resistance layer perforate; The conductive layer that removes this second resistance layer, first resistance layer and covered; On described first metal coupling, electric contact mat, circuit and substrate body, form insulating barrier, and the thickness of this insulating barrier is less than the thickness of described electric contact mat; And a plurality of correspondences of formation expose outside the respectively insulating layer perforating of the upper surface of this first metal coupling in this insulating barrier.
According to described method for making, described insulating layer perforating can corresponding expose outside respectively part upper surface or whole upper surface of this first metal coupling.
According to the method for making of described base plate for packaging, also can be included in the first metal coupling upper surface that this insulating layer perforating respectively exposes outside and form scolder or surface-treated layer; The material that forms this scolder can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it, and the material that forms this surface-treated layer can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
The invention provides a kind of encapsulating structure, comprising: substrate body, its at least one surface has a plurality of electric contact mats and circuit; Insulating barrier is located on the surface of this substrate body, described electric contact mat and the circuit, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this electric contact mat; A plurality of first metal couplings, correspondence are located on the surface of the electric contact mat in this insulating layer perforating respectively, and protrude in this insulating barrier; And semiconductor chip, has an acting surface, and this acting surface has a plurality of electronic padses, respectively be provided with second metal coupling on this electronic pads, these second metal couplings are electrically connected to respectively this first metal coupling by scolder with correspondence, and the material that forms this scolder can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it.
According to described encapsulating structure, described insulating layer perforating can corresponding expose outside respectively part upper surface or whole upper surface of this electric contact mat.
According to described structure, also can comprise underfill material again, be located between this substrate body and the semiconductor chip; Perhaps, also can comprise mold compound, be located between this substrate body and the semiconductor chip, and coat this semiconductor chip.
The present invention also provides another kind of encapsulating structure, comprising: substrate body, and its at least one surface has a plurality of electric contact mats and circuit; A plurality of first metal couplings, correspondence are located at respectively on this electric contact mat; Insulating barrier, be located on the surface of this substrate body, described electric contact mat, circuit and first metal coupling, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this first metal coupling; And semiconductor chip, has an acting surface, and this acting surface has a plurality of electronic padses, respectively be provided with second metal coupling on this electronic pads, these second metal couplings are electrically connected to respectively this first metal coupling by scolder with correspondence, and the material that forms this scolder can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it.
According to described encapsulating structure, described insulating layer perforating can corresponding expose outside respectively part upper surface or whole upper surface of this first metal coupling.
According to described structure, also can comprise underfill material again, be located between this substrate body and the semiconductor chip; Perhaps, also can comprise mold compound, be located between this substrate body and the semiconductor chip, and coat this semiconductor chip.
As from the foregoing, base plate for packaging of the present invention and method for making thereof and encapsulating structure, mainly be on this electric contact mat, circuit and substrate body surface, to form insulating barrier earlier, in this insulating barrier, form insulating layer perforating again, to expose outside the upper surface of this electric contact mat, then, form first metal coupling and scolder on the electric contact mat in insulating layer perforating, at last, by scolder to connect semiconductor chip.
Therefore, in base plate for packaging of the present invention and method for making and encapsulating structure, this scolder is difficult for producing the bridge joint phenomenon, and then helps the encapsulation of thin space; And this substrate body is provided with first metal coupling, can adjust the structure of this first metal coupling with elasticity at different situations, and can obtain stable reliability and encapsulation quality, and simultaneously, cost is also lower relatively; In addition, the present invention does not need to form welding resisting layer on substrate, thereby can minimizing and underfill material, semiconductor chip, mold compound between because thermal coefficient of expansion (coefficient of thermal expansion, not not matching and the stress that produces CTE), and this electric contact mat or circuit need not carry out the alligatoring manufacturing process, and can have good circuit shape and metal coupling shape.
Description of drawings
Figure 1A to Fig. 1 D is the cross-sectional schematic of the method for making of existing encapsulating structure;
Fig. 2 A to Fig. 2 F is the cross-sectional schematic of first embodiment of base plate for packaging of the present invention and method for making and encapsulating structure; Wherein, Fig. 2 C ' is another example of Fig. 2 C, and Fig. 2 D ' is another example of Fig. 2 D, and Fig. 2 E ' is another example of Fig. 2 E, and Fig. 2 F ' is another example of Fig. 2 F;
Fig. 3 A to Fig. 3 H is the cross-sectional schematic of second embodiment of base plate for packaging of the present invention and method for making and encapsulating structure; Wherein, Fig. 3 F ' is another example of Fig. 3 F, and Fig. 3 G ' is another example of Fig. 3 G, and Fig. 3 H ' is another example of Fig. 3 H.
The main element symbol description:
10,30,50 substrate body
10a, 30a, 50a surface
111,311,531 circuits
112,312,532 electric contact mats
12 welding resisting layers
120 welding resisting layer perforates
14,14 ', 34a, 34 ', 57a, 57 ' scolder
20,40 semiconductor chips
20a, the 40a acting surface
21,41 electronic padses
22 metal couplings
312a, the 55a upper surface
32,56 insulating barriers
320,560 insulating layer perforatings
33,55 first metal couplings
34b, the 57b surface-treated layer
42 second metal couplings
43 underfill materials
44 mold compounds
51 conductive layers
52 first resistance layers
520 open regions
53 line layers
54 second resistance layers
540 resistance layer perforates
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
First embodiment
See also Fig. 2 A to Fig. 2 F, be the cross-sectional schematic of first embodiment of base plate for packaging of the present invention and method for making and encapsulating structure.
Shown in Fig. 2 A, at first, provide a substrate body 30, its at least one surperficial 30a has a plurality of electric contact mats 312 and circuit 311, and this electric contact mat 312 and circuit 311 can be copper product.
Shown in Fig. 2 B, on the surperficial 30a of these electric contact mats 312, circuit 311 and this substrate body 30, form insulating barrier 32, and the thickness of this insulating barrier 32 is less than the thickness of described electric contact mat 312 and circuit 311; This insulating barrier 32 can be the organic resin that good combination power is arranged with copper, and these insulating barrier 32 better thickness can be 0.5 to 8 micron (μ m); In addition, the method that forms this insulating barrier 32 can be sprinkling (spray), liquid soaks (dip), coating (coating) or printing.
Shown in Fig. 2 C, in this insulating barrier 32, form a plurality of correspondences and expose outside the respectively insulating layer perforating 320 of the part upper surface 312a of this electric contact mat 312; Because this insulating barrier 32 is thin than existing welding resisting layer, form this insulating layer perforating 320 so can use the laser burning to melt (laser ablation), plasma (plasma) or sandblast (pumice) mode.Also can shown in Fig. 2 C ', in this insulating barrier 32, form a plurality of correspondences and expose outside the respectively insulating layer perforating 320 of whole upper surface 312a of this electric contact mat 312.
Shown in Fig. 2 D and Fig. 2 D ', continue respectively from Fig. 2 C and Fig. 2 C ', the upper surface 312a that exposes at this electric contact mat 312 respectively forms first metal coupling 33; The mode that forms this first metal coupling 33 can be electroplates or electroless plating.Step only explains with the structure shown in Fig. 2 D afterwards.
Shown in Fig. 2 E and Fig. 2 E ', on this first metal coupling 33, form scolder 34a, shown in Fig. 2 E; Perhaps, on this first metal coupling 33, form surface-treated layer 34b, shown in Fig. 2 E '; Step only explains with the structure shown in Fig. 2 E afterwards.
In the present embodiment, the material of described scolder 34a can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it, and the material of described surface-treated layer 34b can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
Shown in Fig. 2 F and Fig. 2 F ', above this substrate body 30, connect again and put semiconductor chip 40 with acting surface 40a, the acting surface 40a of this semiconductor chip 40 has a plurality of electronic padses 41, respectively be provided with second metal coupling 42 on this electronic pads 41, these second metal couplings 42 are electrically connected to respectively this first metal coupling 33 by scolder 34 ' with correspondence; Then, between this substrate body 30 surperficial 30a and semiconductor chip 40, form underfill material 43, shown in Fig. 2 F; Perhaps, between this substrate body 30 surperficial 30a and semiconductor chip 40, form mold compound (molding compound) 44, and this mold compound 44 and coat this semiconductor chip 40, shown in Fig. 2 F '.
The present invention also provides a kind of base plate for packaging, comprising: substrate body 30, and its at least one surperficial 30a has a plurality of electric contact mats 312 and circuit 311; Insulating barrier 32, be located on surperficial 30a, described electric contact mat 312 and the circuit 311 of this substrate body 30, and the thickness of this insulating barrier 32 is less than the thickness of described electric contact mat 312, and has a plurality of correspondences and expose outside the respectively insulating layer perforating 320 of the upper surface 312a of this electric contact mat 312; And a plurality of first metal couplings 33, correspondence is located on the surface of the electric contact mat 312 in this insulating layer perforating 320 respectively, and protrudes in this insulating barrier 32.
According to described base plate for packaging, this insulating layer perforating 320 can expose outside part upper surface 312a or whole upper surface 312a of this electric contact mat 312.
In described structure, also can comprise scolder 34a or surface-treated layer 34b, be located on this first metal coupling 33; The material that forms this surface-treated layer 34b can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
The present invention also can comprise the semiconductor chip 40 with acting surface 40a, have a plurality of electronic padses 41 at this acting surface 40a, respectively be provided with second metal coupling 42 on this electronic pads 41, these second metal couplings 42 are electrically connected to respectively this first metal coupling 33 by scolder 34 ' with correspondence; Form this scolder 34a, 34 ' material can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it.
In described structure, also can comprise underfill material 43, be located between this substrate body 30 and the semiconductor chip 40; Perhaps, also can comprise mold compound 44, be located between this substrate body 30 and the semiconductor chip 40, and coat this semiconductor chip 40.
Second embodiment
See also Fig. 3 A to Fig. 3 H, be the cross-sectional schematic of second embodiment of base plate for packaging of the present invention and method for making and encapsulating structure.
As shown in Figure 3A, at first, provide a substrate body 50, its at least one surperficial 50a has conductive layer 51.
Shown in Fig. 3 B, on this conductive layer 51, form first resistance layer 52, have the open region 520 of a plurality of patternings in this first resistance layer 52; Then, electroplate forming line layer 53 in these open regions 520, and this line layer 53 comprises a plurality of electric contact mats 532 and circuit 531 by this conductive layer 51, and this line layer 53 can be copper product.
Shown in Fig. 3 C, on this first resistance layer 52 and line layer 53, form second resistance layer 54, and a plurality of correspondences of formation expose outside the respectively resistance layer perforate 540 of this electric contact mat 532 in this second resistance layer 54.
Shown in Fig. 3 D, respectively forming first metal coupling 55 in this resistance layer perforate 540; The mode that forms this first metal coupling 55 can be electroplates or electroless plating.
Shown in Fig. 3 E, the conductive layer 51 that removes this second resistance layer 54, first resistance layer 52 and covered is with the surface, the line layer 53 that expose this substrate body 50 and be formed on first metal coupling 55 on this electric contact mat 532; Afterwards, on the surperficial 50a of described first metal coupling 55, electric contact mat 532, circuit 531 and substrate body 50, form insulating barrier 56, and the thickness of this insulating barrier 56 is less than the thickness of described electric contact mat 532; This insulating barrier 56 can be the organic resin that good combination power is arranged with copper, and these insulating barrier 56 better thickness can be 0.5 to 8 micron (μ m); In addition, the method that forms this insulating barrier 56 can be sprinkling (spray), liquid soaks (dip), coating (coating) or printing.
Shown in Fig. 3 F, in this insulating barrier 56, form a plurality of insulating layer perforatings 560, expose outside the respectively part upper surface 55a of this first metal coupling 55 with correspondence; Because this insulating barrier 56 is thin than existing welding resisting layer, form this insulating layer perforating 560 so can use the laser burning to melt (laser ablation), plasma (plasma) or sandblast (pumice) mode.Also can shown in Fig. 3 F ', in this insulating barrier 56, form a plurality of insulating layer perforatings 560, expose outside respectively whole upper surface 55a of this first metal coupling 55 with correspondence.Step only explains with the structure shown in Fig. 3 F afterwards.
Shown in Fig. 3 G and Fig. 3 G ', the upper surface 55a of first metal coupling 55 that is exposed at this insulating layer perforating 560 respectively forms scolder 57a, shown in Fig. 3 G; Perhaps, on the upper surface 55a of first metal coupling 55 that this insulating layer perforating 560 respectively exposes, form surface-treated layer 57b, shown in Fig. 3 G '; Step only explains with the structure shown in Fig. 3 G afterwards.
In the present embodiment, the material of described scolder 57a can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it, and the material of described surface-treated layer 57b can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
Shown in Fig. 3 H and Fig. 3 H ', above this substrate body 50, connect again and put semiconductor chip 40 with acting surface 40a, the acting surface 40a of this semiconductor chip 40 has a plurality of electronic padses 41, respectively be provided with second metal coupling 42 on this electronic pads 41, these second metal couplings 42 are electrically connected to respectively this first metal coupling 55 by scolder 57 ' with correspondence; Then, between this substrate body 50 surperficial 50a and semiconductor chip 40, form underfill material 43, shown in Fig. 3 H; Perhaps, between this substrate body 50 surperficial 50a and semiconductor chip 40, form mold compound 44, and this mold compound 44 and coat this semiconductor chip 40, shown in Fig. 3 H '.
The present invention also provides another kind of base plate for packaging, comprising: substrate body 50, and its at least one surperficial 50a has a plurality of electric contact mats 532 and circuit 531; A plurality of first metal couplings 55, correspondence are located on the surface of this electric contact mat 532 respectively; And insulating barrier 56, be located on surperficial 50a, described electric contact mat 532, circuit 531 and first metal coupling 55 of this substrate body 50, and the thickness of this insulating barrier 56 is less than the thickness of described electric contact mat 532, and has a plurality of correspondences and expose outside the respectively insulating layer perforating 560 of the upper surface 55a of this first metal coupling 55.
According to described base plate for packaging, this insulating layer perforating 560 can expose outside part upper surface 55a or whole upper surface 55a of first metal coupling 55.
In described structure, also can comprise scolder 57a or surface-treated layer 57b, be located on this first metal coupling 55; The material that forms this surface-treated layer 57b can be nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), with wherein one of gold (Au).
The present invention also can comprise the semiconductor chip 40 with acting surface 40a, and this acting surface 40a has a plurality of electronic padses 41, respectively be provided with second metal coupling 42 on this electronic pads 41, these second metal couplings 42 are electrically connected to respectively this first metal coupling 55 by scolder 57 ' with correspondence; Form this scolder 57a, 57 ' material can be tin (Sn), plumbous (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), forms wherein one of group's alloy with it.
In described structure, also can comprise underfill material 43, be located between this substrate body 50 and the semiconductor chip 40; Perhaps, also can comprise mold compound 44, be located between this substrate body 50 and the semiconductor chip 40, and coat this semiconductor chip 40.
In sum, base plate for packaging of the present invention and method for making thereof and encapsulating structure mainly are to form insulating barrier earlier on electric contact mat, circuit and substrate body surface, form insulating layer perforating again in insulating barrier; Then, form first metal coupling and scolder on the electric contact mat in this insulating layer perforating; At last, by this scolder connecting semiconductor chip, thereby avoiding this scolder to produce the bridge joint phenomenon, and help the encapsulation of thin space; And be formed with first metal coupling on this substrate body, can be at different situations with this first metal coupling of Flexible Design, thereby obtain stable reliability and encapsulation quality easily, cost is also low relatively; In addition, the present invention does not need to form welding resisting layer on substrate, this can minimizing and underfill material, semiconductor chip, mold compound between owing to the stress that does not match and produce of thermal coefficient of expansion (CTE), and because electric contact mat or circuit must not carry out the alligatoring manufacturing process, so can form good circuit shape and metal coupling shape.
Described embodiment is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and described embodiment is modified and changes.Therefore, the scope of the present invention should be foundation with the scope of claims.
Claims (10)
1. a base plate for packaging is characterized in that, comprising:
Substrate body, its at least one surface has a plurality of electric contact mats and circuit;
Insulating barrier is located on the surface of this substrate body, described electric contact mat and the circuit, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this electric contact mat; And
A plurality of first metal couplings, correspondence are located at the upper surface of the electric contact mat in this insulating layer perforating respectively, and protrude in this insulating barrier.
2. base plate for packaging according to claim 1 is characterized in that: described insulating layer perforating correspondence exposes outside respectively part upper surface or whole upper surface of this electric contact mat.
3. base plate for packaging according to claim 1 is characterized in that: also comprise scolder or surface-treated layer, be located on this first metal coupling.
4. a base plate for packaging is characterized in that, comprising:
Substrate body, its at least one surface has a plurality of electric contact mats and circuit;
A plurality of first metal couplings, correspondence are located at respectively on this electric contact mat; And
Insulating barrier, be located on the surface of this substrate body, described electric contact mat, circuit and first metal coupling, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this first metal coupling.
5. base plate for packaging according to claim 4 is characterized in that: described insulating layer perforating correspondence exposes outside respectively part upper surface or whole upper surface of this first metal coupling.
6. base plate for packaging according to claim 4 is characterized in that: also comprise scolder or surface-treated layer, be located on this first metal coupling.
7. an encapsulating structure is characterized in that, comprising:
Substrate body, its at least one surface has a plurality of electric contact mats and circuit;
Insulating barrier is located on the surface of this substrate body, described electric contact mat and the circuit, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this electric contact mat;
A plurality of first metal couplings, correspondence are located on the surface of the electric contact mat in this insulating layer perforating respectively, and protrude in this insulating barrier; And
Semiconductor chip has an acting surface, and this acting surface has a plurality of electronic padses, respectively is being provided with second metal coupling on this electronic pads, and described second metal coupling is electrically connected to respectively this first metal coupling by scolder with correspondence.
8. encapsulating structure according to claim 7 is characterized in that: described insulating layer perforating correspondence exposes outside respectively part upper surface or whole upper surface of this electric contact mat.
9. an encapsulating structure is characterized in that, comprising:
Substrate body, its at least one surface has a plurality of electric contact mats and circuit;
A plurality of first metal couplings, correspondence are located at respectively on this electric contact mat;
Insulating barrier, be located on the surface of this substrate body, described electric contact mat, circuit and first metal coupling, and the thickness of this insulating barrier is less than the thickness of described electric contact mat, and has a plurality of correspondences and expose outside the respectively insulating layer perforating of the upper surface of this first metal coupling; And
Semiconductor chip has acting surface, and this acting surface has a plurality of electronic padses, respectively is being provided with second metal coupling on this electronic pads, and described second metal coupling is electrically connected to respectively this first metal coupling by scolder with correspondence.
10. encapsulating structure according to claim 9 is characterized in that: described insulating layer perforating correspondence exposes outside respectively part upper surface or whole upper surface of this first metal coupling.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910165563 CN101989593B (en) | 2009-07-30 | 2009-07-30 | Packaging substrate as well as manufacturing method and packaging structure thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910165563 CN101989593B (en) | 2009-07-30 | 2009-07-30 | Packaging substrate as well as manufacturing method and packaging structure thereof |
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| CN101989593A true CN101989593A (en) | 2011-03-23 |
| CN101989593B CN101989593B (en) | 2012-12-12 |
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| CN105845585A (en) * | 2016-04-28 | 2016-08-10 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging method and chip packaging structure |
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| JP3598564B2 (en) * | 1995-03-16 | 2004-12-08 | 富士通株式会社 | Bump forming method |
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| JP2006032724A (en) * | 2004-07-16 | 2006-02-02 | Nippon Steel Corp | Wafer level package and its manufacturing method |
| CN1296286C (en) * | 2005-01-10 | 2007-01-24 | 侯解民 | Method and device used for recovering floating oil on water surface |
| JP2009147124A (en) * | 2007-12-14 | 2009-07-02 | Mitsubishi Cable Ind Ltd | Welding structure and method of manufacturing the same, and electronic circuit board with the same |
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| CN104681531B (en) * | 2013-11-27 | 2019-01-15 | 矽品精密工业股份有限公司 | Package substrate and method for fabricating the same |
| CN107004612A (en) * | 2014-12-12 | 2017-08-01 | 高通股份有限公司 | The integrated device including photosensitive filler is encapsulated between substrate and tube core |
| CN105845585A (en) * | 2016-04-28 | 2016-08-10 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging method and chip packaging structure |
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| Publication number | Publication date |
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| CN101989593B (en) | 2012-12-12 |
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