CN111883445A - Stacked electronic assembly and manufacturing method thereof - Google Patents
Stacked electronic assembly and manufacturing method thereof Download PDFInfo
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- CN111883445A CN111883445A CN202010801606.0A CN202010801606A CN111883445A CN 111883445 A CN111883445 A CN 111883445A CN 202010801606 A CN202010801606 A CN 202010801606A CN 111883445 A CN111883445 A CN 111883445A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/145—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
- H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Nanotechnology (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
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Abstract
The invention provides a stacked electronic assembly and a manufacturing method thereof. The invention forms a polymer point formed by laser activation material in advance, then ablates and activates the polymer point to form a groove structure and metal nano particles, the groove is used for accommodating the metal particles and other conductive columns which are aligned and bonded, and the metal nano particles realize the bonding of the upper conductive column and the lower conductive column, so that the height difference can be offset, and the bonding reliability can be ensured. The bonding of the metal nanoparticles is stronger than conventional solder bonding.
Description
Technical Field
The invention relates to the field of semiconductor device packaging, in particular to a stacked electronic component and a manufacturing method thereof.
Background
With the increasing integration level, more semiconductor chips need to be integrated on the package substrate. In order to save lateral space of the package substrate, a plurality of chips may be disposed to be stacked. While this stacked arrangement makes the connection posts on the outside thereof more dense, the accuracy of interconnection and the bonding strength thereof face greater challenges. Due to the different heights of the bonding conductive pillars on the package substrate, the connection often occurs with the cold joint of individual connection pillars, resulting in the open circuit of the electrical connection.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for manufacturing a stacked electronic component, comprising the steps of:
(1) providing a carrier plate, and dropping a laser activated polymer material on the carrier plate to form a plurality of hemispherical polymer dots;
(2) forming a first photoresist layer covering the polymer dots on the carrier plate, etching the first photoresist layer to form a plurality of first through holes, and filling a conductive material in the first through holes to form a plurality of first conductive columns and a plurality of first sub-conductive columns;
(3) bonding a first chip to first ends of the first plurality of conductive pillars;
(4) forming a second photoresist layer covering the first chip on the first photoresist layer, etching the second photoresist layer to form a plurality of second through holes, filling a conductive material in the second through holes to form a plurality of second sub-conductive columns, wherein the plurality of second conductive columns are connected with the plurality of first sub-conductive columns in a one-to-one correspondence manner to form a plurality of second conductive columns together;
(5) bonding a second chip to the plurality of second conductive pillars;
(6) removing the carrier plate to expose the polymer dots;
(7) laser ablating and activating the polymer dots such that the first photoresist layer has hemispherical recesses at the second ends of the first and second plurality of conductive pillars, and the recesses have activated metal nanoparticles therein;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
The diameters of the first conductive pillars and the second conductive pillars are smaller than the diameter of the polymer dot, and a recessed structure is arranged at the second ends of the first conductive pillars and the second conductive pillars, and the recessed structure is formed by conforming to the polymer dot.
And a step (9) of forming a filling layer between the packaging substrate and the first photoresist layer, wherein the filling layer wraps the plurality of third conductive pillars.
Wherein the heights of the third conductive pillars are different, and in step (8), heating the metal nanoparticles forms a metal sintered layer between the third conductive pillars and the first conductive pillars, and the metal sintered layer has a different thickness.
In step (7), the metal nanoparticles do not fill the grooves.
According to the above manufacturing method, the present invention also provides a stacked electronic component including:
a package assembly, the package assembly comprising: a photoresist layer; a plurality of first conductive pillars and a plurality of second conductive pillars in the photoresist layer and a first chip bonded to first ends of the plurality of first conductive pillars; a second chip bonded to first ends of the plurality of second conductive pillars; wherein the photoresist layer has a hemispherical recess at the second ends of the first and second conductive pillars;
and the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are jointed with the first conductive columns and the second conductive columns by heating the metal nanoparticles in the grooves.
Wherein the heights of the third conductive pillars are different, and heating the metal nanoparticles forms a metal sintered layer between the third conductive pillars and the first and second conductive pillars, and the thicknesses of the metal sintered layer are different.
Wherein a portion of the plurality of third conductive pillars is inserted into the recess.
The aperture of the first conductive columns and the aperture of the second conductive columns are smaller than the diameter of the groove, and the second ends of the first conductive columns and the second conductive columns are provided with a recessed structure.
The packaging substrate further comprises a filling layer between the packaging substrate and the first photoresist layer, and the filling layer wraps the plurality of third conductive posts.
The invention forms a polymer point formed by laser activation material in advance, then ablates and activates the polymer point to form a groove structure and metal nano particles, the groove is used for accommodating the metal particles and other conductive columns which are aligned and bonded, and the metal nano particles realize the bonding of the upper conductive column and the lower conductive column, so that the height difference can be offset, and the bonding reliability can be ensured. The bonding of the metal nanoparticles is stronger than conventional solder bonding.
Drawings
FIG. 1 is a cross-sectional view of a stacked electronic assembly of the present invention;
fig. 2 is an enlarged view of the bond between the conductive pillars of fig. 1;
fig. 3-11 are schematic diagrams of a method of fabricating a stacked electronic assembly of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Referring to fig. 1 and 2, the stacked electronic component package assembly of the present invention includes an upper package assembly and a lower package substrate 10. The package assembly is a stacked chip package assembly electrically connected to the lower package substrate 10 by a plurality of conductive pillars.
The package assembly comprises at least two stacked first chips 6 and second chips 7, wherein the second chips 7 have a larger size than the first chips 6. The first chip 6 and the second chip 7 may be any possible functional chips including active chips such as MOS, JFET, IGBT, etc. or passive chips such as resistors, inductors, capacitors.
The first chip 6 is sealed in the photoresist layer 3, and the second chip 7 is disposed on the photoresist layer 3. In the photoresist layer 3, there are a plurality of first conductive pillars 4 and a plurality of second conductive pillars 5, wherein the first chip 6 is bonded to the top end of the first conductive pillar 4, and the second chip 7 is bonded to the top end of the second conductive pillar 5.
The first conductive pillar 4 and the second conductive pillar 5 are made of the same metal material, such as Cu, Al, W, etc., and are formed by a conventional method, such as electroplating. The height of the first conductive pillar 4 is smaller than that of the second conductive pillar 5, and the second conductive pillar 5 is outside the first conductive pillar 4.
As the most important part of the present invention, the photoresist layer 3 has a plurality of grooves 8 on the bottom thereof, and the plurality of grooves 8 have a hemispherical shape, and a specific manufacturing method thereof is explained in detail below. The plurality of grooves 8 are respectively disposed at the lower ends of the first conductive posts 4 and the second conductive posts 5, and the bottoms of the plurality of grooves 8 expose the first conductive posts 4 and the second conductive posts 5. In said grooves 8 there are metal nanoparticles 9, which metal nanoparticles 9 are formed by laser activation of a polymer material. The polymer material includes a resin and a metal complex, such as a copper complex, a silver complex, etc., which can be ablated and activated by laser, remove the organic material thereof, and allow the metal complex to form metal nanoparticles 9.
The package substrate 10 has a plurality of third conductive pillars 11 and 12, the third conductive pillars 11 are disposed corresponding to the plurality of first conductive pillars 4, the third conductive pillars 12 are disposed corresponding to the plurality of second conductive pillars 5, and the bonding between the third conductive pillars 11 and 12 and the first conductive pillars 4 and the bonding between the third conductive pillars 11 and 12 and the second conductive pillars 5 are achieved by heating the metal nanoparticles in the grooves 8.
Wherein, the heights of the plurality of third conductive pillars 11, 12 may be different, for example, the height difference may be 0.5-1 micrometer. Heating the metal nanoparticles 9 forms a metal sintered layer between the plurality of third conductive pillars 11, 12 and the plurality of first conductive pillars 4, 5, and the thickness of the metal sintered layer is different, so that the third conductive pillars 11, 12 with different heights can be effectively bonded to the first conductive pillars 4 or the second conductive pillars 5, and poor bonding caused by the height difference can be offset.
Referring to fig. 2, the apertures R1 of the first conductive pillars 4 and the second conductive pillars 5 are smaller than the diameter R2 of the groove 8, so that a part of the third conductive pillars 11 and 12 can be easily inserted into the groove 8, which facilitates alignment and offsetting of the height difference. The depth of the third conductive posts 11 and 12 inserted into the groove 8 is h, and the size of h is 1-2 micrometers. And the second ends of the plurality of first conductive pillars 4 and second conductive pillars 5 have a recessed structure, and the recessed structure can retain enough metal sintering layer to ensure the reliability of the electrical connection.
In addition, a filling layer 13 is further included between the package substrate and the first photoresist layer, and the filling layer 13 wraps the plurality of third conductive pillars 11 and 12.
In addition, the present invention also provides a method of manufacturing a stacked electronic assembly, comprising the steps of:
(1) providing a carrier plate, and dropping a laser activated polymer material on the carrier plate to form a plurality of hemispherical polymer dots;
(2) forming a first photoresist layer covering the polymer dots on the carrier plate, etching the first photoresist layer to form a plurality of first through holes, and filling a conductive material in the first through holes to form a plurality of first conductive columns and a plurality of first sub-conductive columns;
(3) bonding a first chip to first ends of the first plurality of conductive pillars;
(4) forming a second photoresist layer covering the first chip on the first photoresist layer, etching the second photoresist layer to form a plurality of second through holes, filling a conductive material in the second through holes to form a plurality of second sub-conductive columns, wherein the plurality of second conductive columns are connected with the plurality of first sub-conductive columns in a one-to-one correspondence manner to form a plurality of second conductive columns together;
(5) bonding a second chip to the plurality of second conductive pillars;
(6) removing the carrier plate to expose the polymer dots;
(7) laser ablating and activating the polymer dots such that the first photoresist layer has hemispherical recesses at the second ends of the first and second plurality of conductive pillars, and the recesses have activated metal nanoparticles therein;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
The diameters of the first conductive pillars and the second conductive pillars are smaller than the diameter of the polymer dot, and a recessed structure is arranged at the second ends of the first conductive pillars and the second conductive pillars, and the recessed structure is formed by conforming to the polymer dot.
And a step (9) of forming a filling layer between the packaging substrate and the first photoresist layer, wherein the filling layer wraps the plurality of third conductive pillars.
Wherein the heights of the third conductive pillars are different, and in step (8), heating the metal nanoparticles forms a metal sintered layer between the third conductive pillars and the first conductive pillars, and the metal sintered layer has a different thickness.
In step (7), the metal nanoparticles do not fill the grooves.
The method of fabricating the stacked electronic assembly provided by the present invention is described in detail below with reference to fig. 3-11.
First, referring to fig. 3, a carrier plate 1 is provided, and the carrier plate 1 may be a rigid plate such as a glass plate, a ceramic plate, a silicon plate, etc. A plurality of polymer dots 2 are formed on the carrier plate 1 by means of dropping, the material of the polymer dots 2 is a laser activated polymer material, wherein the polymer dots 2 are hemispherical due to surface tension after dropping, and then are cured.
Next, referring to fig. 4, a first photoresist layer 31 covering the polymer dots 2 is formed on the carrier 1, and the first photoresist layer 31 is etched to form a plurality of first through holes, wherein the polymer dots 2 are exposed at the bottoms of the plurality of first through holes. Then, a plurality of first conductive pillars 4 and a plurality of first sub-conductive pillars 51 are formed by filling a conductive material in the first via holes. The first photoresist layer 31 may be polished and planarized by a CMP process.
Referring to fig. 5, the first chip 6 is bonded to the upper ends of the plurality of first conductive pillars 4. The first chip 6 is a flip chip, which may be bonded to the first conductive pillar 4 via solder (not shown).
Referring to fig. 6, a second photoresist layer 32 is formed on the first photoresist layer 31 to cover the first chip 6, and the second photoresist layer 32 is etched to form a plurality of second through holes, where the plurality of second through holes are arranged in one-to-one correspondence with the first sub-conductive pillars 51. The second through holes are filled with a conductive material to form a plurality of second sub-conductive pillars 52, the plurality of second conductive pillars 52 and the plurality of first sub-conductive pillars 51 are connected in a one-to-one correspondence, which together form the plurality of second conductive pillars 5 in fig. 1, and the first photoresist layer 31 and the second photoresist layer 32 form the photoresist layer 3 in fig. 1.
Then, referring to fig. 7, a second chip 7 is bonded to the plurality of second conductive pillars 5. The second chip 7 is a flip chip, which may be bonded to the second conductive pillars 5 via solder (not shown).
Referring to fig. 8, the carrier plate 1 is removed to expose the polymer dots 2.
Referring to fig. 9, the polymer dots 2 are laser ablated and activated such that the photoresist layer 3 has hemispherical recesses 8 at the lower ends of the first and second conductive pillars 4, 5, and the recesses 8 have activated metal nanoparticles 9 therein. Due to ablation, the metal nanoparticles 9 do not fill the grooves 8. And a recess structure is formed at the lower ends of the plurality of first conductive pillars 4 and second conductive pillars 5, the recess structure being formed by conforming to the polymer dots 2.
Then, referring to fig. 10, a package substrate 10 is provided, where the package substrate 10 has a plurality of third conductive pillars 11 and 12, the third conductive pillars 11 and 12 correspond to the first conductive pillars 4 and the second conductive pillars 5 one to one, and the bonding of the third conductive pillars 11 and 12 to the first conductive pillars 4 and the second conductive pillars 5 is realized by heating the metal nanoparticles 9.
Referring to fig. 11, a filling layer 13 is formed between the package substrate 10 and the photoresist layer 3, and the filling layer 13 wraps the plurality of third conductive pillars 11 and 12.
The invention forms a polymer point formed by laser activation material in advance, then ablates and activates the polymer point to form a groove structure and metal nano particles, the groove is used for accommodating the metal particles and other conductive columns which are aligned and bonded, and the metal nano particles realize the bonding of the upper conductive column and the lower conductive column, so that the height difference can be offset, and the bonding reliability can be ensured. The bonding of the metal nanoparticles is stronger than conventional solder bonding.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.
Claims (10)
1. A method of manufacturing a stacked electronic assembly, comprising the steps of:
(1) providing a carrier plate, and dropping a laser activated polymer material on the carrier plate to form a plurality of hemispherical polymer dots;
(2) forming a first photoresist layer covering the polymer dots on the carrier plate, etching the first photoresist layer to form a plurality of first through holes, and filling a conductive material in the first through holes to form a plurality of first conductive columns and a plurality of first sub-conductive columns;
(3) bonding a first chip to first ends of the first plurality of conductive pillars;
(4) forming a second photoresist layer covering the first chip on the first photoresist layer, etching the second photoresist layer to form a plurality of second through holes, filling a conductive material in the second through holes to form a plurality of second sub-conductive columns, wherein the plurality of second conductive columns are connected with the plurality of first sub-conductive columns in a one-to-one correspondence manner to form a plurality of second conductive columns together;
(5) bonding a second chip to the plurality of second conductive pillars;
(6) removing the carrier plate to expose the polymer dots;
(7) laser ablating and activating the polymer dots such that the first photoresist layer has hemispherical recesses at the second ends of the first and second plurality of conductive pillars, and the recesses have activated metal nanoparticles therein;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
2. The method of manufacturing a stacked electronic assembly of claim 1, wherein: the diameters of the first conductive pillars and the second conductive pillars are smaller than the diameter of the polymer dot, and a recessed structure is arranged at the second ends of the first conductive pillars and the second conductive pillars, and the recessed structure is formed by conforming to the polymer dot.
3. The method of manufacturing a stacked electronic assembly of claim 1, wherein: and a step (9) of forming a filling layer between the packaging substrate and the first photoresist layer, wherein the filling layer wraps the plurality of third conductive pillars.
4. The method of manufacturing a stacked electronic assembly of claim 1, wherein: the third conductive pillars have different heights, and in step (8), heating the metal nanoparticles forms a metal sintered layer between the third conductive pillars and the first and second conductive pillars, the metal sintered layer having different thicknesses.
5. The method of manufacturing a stacked electronic assembly of claim 1, wherein: in step (7), the metal nanoparticles do not fill the grooves.
6. A stacked electronic assembly, comprising:
a package assembly, the package assembly comprising: a photoresist layer; a plurality of first conductive pillars and a plurality of second conductive pillars in the photoresist layer and a first chip bonded to first ends of the plurality of first conductive pillars; a second chip bonded to first ends of the plurality of second conductive pillars; wherein the photoresist layer has a hemispherical recess at the second ends of the first and second conductive pillars;
and the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are jointed with the first conductive columns and the second conductive columns by heating the metal nanoparticles in the grooves.
7. The stacked electronic assembly of claim 6, wherein: the heights of the third conductive pillars are different, and heating the metal nanoparticles forms a metal sintered layer between the third conductive pillars and the first and second conductive pillars, the metal sintered layer having a different thickness.
8. The stacked electronic assembly of claim 6, wherein: a portion of the plurality of third conductive posts is inserted into the recess.
9. The stacked electronic assembly of claim 6, wherein: the aperture of the first conductive columns and the aperture of the second conductive columns are smaller than the diameter of the groove, and the second ends of the first conductive columns and the second conductive columns are provided with a recessed structure.
10. The stacked electronic assembly of claim 6, wherein: the packaging substrate further comprises a filling layer between the packaging substrate and the first photoresist layer, and the filling layer wraps the plurality of third conductive posts.
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| CN202010801606.0A CN111883445B (en) | 2020-08-11 | 2020-08-11 | Stacked electronic assembly and manufacturing method thereof |
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| CN111883445A true CN111883445A (en) | 2020-11-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078118A (en) * | 2021-03-25 | 2021-07-06 | 福唐激光(苏州)科技有限公司 | Method for realizing POP (point of presence protocol) connection by laser and POP structure thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543939A (en) * | 2012-01-05 | 2012-07-04 | 三星半导体(中国)研究开发有限公司 | Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof |
| CN106486444A (en) * | 2015-08-31 | 2017-03-08 | 中芯长电半导体（江阴）有限公司 | Projection cube structure, package assembling and forming method thereof |
| US20170194279A1 (en) * | 2015-07-10 | 2017-07-06 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
-
2020
- 2020-08-11 CN CN202010801606.0A patent/CN111883445B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543939A (en) * | 2012-01-05 | 2012-07-04 | 三星半导体(中国)研究开发有限公司 | Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof |
| US20170194279A1 (en) * | 2015-07-10 | 2017-07-06 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| CN106486444A (en) * | 2015-08-31 | 2017-03-08 | 中芯长电半导体（江阴）有限公司 | Projection cube structure, package assembling and forming method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078118A (en) * | 2021-03-25 | 2021-07-06 | 福唐激光(苏州)科技有限公司 | Method for realizing POP (point of presence protocol) connection by laser and POP structure thereof |
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| CN111883445B (en) | 2022-07-19 |
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