JP2014192171A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce the occurrence of voids in gaps among a plurality of semiconductor chips and a gap between a wiring board and a semiconductor chip.SOLUTION: A semiconductor device comprises: N (N is a positive integer)-stage semiconductor chips 21-24, 30 laminated on a wiring board 10; and an encapsulation resin 50 which is formed on the wiring board, and covers the semiconductor chips, and fills gaps among the N-stage semiconductor chips and a gap between the wiring board and the bottom stage semiconductor chip. The wiring board and at least the semiconductor chips to the (N-1)th stage among the n-stage semiconductor chips have through holes and the encapsulation resin is arranged in each through hole.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art In recent years, semiconductor devices having a structure in which a plurality of semiconductor chips are stacked have been provided in order to meet the demand for downsizing with the spread of small electronic devices such as portable terminals.

  In Patent Document 1, a plurality of semiconductor chips are stacked and a chip stack is formed by filling an underfill material in a gap between the semiconductor chips, and then the chip stack is mounted on a wiring board. A technique for forming a sealing resin on a wiring board so as to cover the substrate is disclosed.

  On the other hand, Patent Document 2 discloses a technique for resin-sealing a plurality of semiconductor chips stacked on a wiring board without filling an underfill material between semiconductor chips.

  Further, Patent Document 3 discloses a technique for sealing an IC flip-chip mounted on a circuit board using a transfer molding resin having a filler size of 10 μm or less.

JP 2010-251347 A JP 2007-036104 A JP 2000-294692 A

  In the case of the technique of Patent Document 1, filling of the chip stack with the underfill material is performed by a capillary phenomenon, so that time is required for filling, the processing efficiency is poor, and the assembly cost of the semiconductor device is increased.

  On the other hand, according to the technique of Patent Document 2, since there is no step of filling the underfill material between the semiconductor chips in advance, the assembly cost of the semiconductor device can be reduced. There is a risk of voids.

  A semiconductor device according to an aspect of the present invention includes a wiring board, an N (N is a positive integer) stage semiconductor chip stacked on the wiring board, and the N stage semiconductor chip formed on the wiring board. A sealing resin that covers and fills a gap between the N-stage semiconductor chip and a gap between the wiring board and the lowermost semiconductor chip, and includes the wiring board and the N-stage semiconductor chip. At least (N-1) stages of semiconductor chips have through holes, and the sealing resin is disposed in the through holes. The sealing resin may contain a filler. In this case, it is desirable that the filler has a size of 10 μm or less.

  According to another aspect of the present invention, a step of mounting a chip stack composed of stacked N (N is a positive integer) semiconductor chips on a wiring board, and the chip mounted on the wiring board Covering the laminate and sealing with a molten resin so as to fill a gap between the N-stage semiconductor chips and a gap between the wiring board and the lowermost semiconductor chip, and the wiring board. And at least (N-1) stages of the N-stage semiconductor chips, through holes are provided, so that the gap between the N-stage semiconductor chips and the gap between the N-stage semiconductor chips during the sealing step with the molten resin A method of manufacturing a semiconductor device is provided in which bubbles generated in a gap between a wiring board and the lowermost semiconductor chip are exhausted through the through hole.

  As described above, through holes are provided in the wiring substrate and the plurality of semiconductor chips stacked on the wiring substrate, and the sealing resin is disposed in the through holes, so that the gaps between the plurality of semiconductor chips and the wiring substrate and the semiconductor are arranged. The generation of voids in the gap between the chips can be reduced, and the reliability of the semiconductor device can be improved. In particular, by setting the filler contained in the sealing resin to a size of 10 μm or less, the sealing resin can be satisfactorily filled without clogging the gaps and through holes between the semiconductor chips.

It is sectional drawing which shows schematic structure of the CoC type semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view for demonstrating the bump and through-hole which are formed in the semiconductor chip (memory chip, IF chip) used for the semiconductor device shown in FIG. FIG. 10 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a semiconductor chip stacking process, which is a part of the assembly process of the semiconductor device shown in FIG. 1. FIG. 5 is a cross-sectional view for explaining a resin sealing process of a chip stack, which is a part of the assembly process of the semiconductor device, following FIG. 4. It is sectional drawing for demonstrating the reason that the production | generation of a void is reduced in the resin sealing process of FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of a CoC (Chip on Chip) type semiconductor device according to the first embodiment of the present invention. FIG. 2 shows a semiconductor chip used in the semiconductor device shown in FIG. It is a top view for demonstrating the bump and through-hole which are formed.

  In the semiconductor device according to the first embodiment, as shown in FIG. 1, a chip stacked body in which a plurality of semiconductor chips are stacked is mounted on a wiring substrate 10. As for the wiring board 10, the insulating film (solder resist) 10-2 is formed in both surfaces of the insulating base material 10-1. Here, the chip stack includes four memory chips 21 to 24 and an IF chip 30 for controlling these four memory chips. The uppermost memory chip 24 is formed with a plurality of surface bumps 24-1 having the same arrangement as the memory circuit having the same configuration as the other memory chips 21 to 23. However, as shown in FIG. It differs from other memory chips in that the through electrode 23-3 and the back bump 23-2 are not formed.

  As for each memory chip, for the memory chip 23, for example, a predetermined memory circuit is formed on one surface of a silicon substrate. A plurality of electrode pads electrically connected to the memory circuit are formed in a predetermined arrangement on one surface side of the silicon substrate. An insulating protective film is formed on the circuit layer on which the memory circuit is formed to protect the circuit formation surface. The protective film is provided with an opening to expose the electrode pad. Furthermore, a plurality of surface bumps 23-1 formed on the plurality of electrode pads are formed on one surface of the silicon substrate. The surface bump 23-1 is a columnar body made of Cu, for example, and is formed so as to protrude from the surface of the memory chip. An Ni plating layer for preventing Cu diffusion and an Au plating layer for preventing oxidation are formed on the surface bump 23-1. For example, as shown in FIG. 2A, the surface bumps 23-1 are arranged in one row at a substantially central portion of one surface of the memory chip 23, and are arranged on two sides parallel to the row of the surface bumps 23-1. A plurality of dummy bumps 23-4 are arranged along each of them.

  A plurality of back surface bumps (23-2 in FIG. 1) are formed on the other surface of the silicon substrate in the memory chip 23, and each of the plurality of back surface bumps has a through electrode (see FIG. 1) corresponding to the corresponding front surface bump 23-1. 23-3). The back bump is a columnar body made of Cu, for example, and is formed so as to protrude from the back surface of the memory chip. An Sn / Ag solder plating layer is formed on the surface of the back bump. A plurality of dummy bumps 23-6 (FIG. 1) are also arranged on the other surface of the silicon substrate. Like the rear surface bumps, the dummy bumps 23-4 on the front surface side are electrically connected to the front surface via the through electrodes 23-7 (FIG. 1). Connected.

  A through hole 23-5 is formed at a substantially central portion between the surface bump row and the dummy bump row in the memory chip 23. Since the through hole 23-5 is formed at the same time as the through hole in forming the through electrode 23-3 (FIG. 1), it has the same diameter as the through hole in forming the through electrode, for example, 15 μm.

  As described above, the memory chip 24 located at the top is substantially the same memory chip as the other memory chips, and has a plurality of surface bumps 24-1 and dummy bumps 24-4 formed on one surface of the silicon substrate. However, the through electrode penetrating the silicon substrate is not formed, and the back surface bump is not formed on the other surface. The uppermost memory chip 24 is configured to have a thickness of 100 μm, for example, and is configured to have a thickness larger than the thicknesses of the other memory chips 21 to 23, for example, 50 μm. Similarly to the other memory chips 21 to 23, the uppermost memory chip 24 has a through hole 24-5 formed at a substantially central portion between the surface bump row and the dummy bump row.

  A void (bubble) generated between the uppermost memory chip 24 and the adjacent memory chip 23 can escape from the through hole 23-5 of the adjacent memory chip 23. Therefore, when the number of stacked layers of memory chips including IF chips is N (N is a positive integer), as shown in FIG. 3, through-holes are provided in at least (N−1) stages of memory chips, The N-stage, that is, the uppermost memory chip 24 may be configured not to provide a through hole. Further, it is preferable that the through holes of at least (N−1) stages of the N-stage semiconductor chips are arranged at positions overlapping each other in plan view, but the present invention is not limited to this.

  Returning to FIG. 1, IF chips 30 are stacked between the wiring substrate 10 and the plurality of memory chips. The IF chip 30 is formed with a control circuit that controls each memory chip, and has a smaller size than the memory chip.

  As shown in FIG. 2B, in the IF chip 30, the back surface bump 30-2 on the other surface side is arranged corresponding to the surface bump (for example, 23-1) of the memory chip (for example, 23). . A through electrode 30-3 (FIG. 1) reaching the front surface side is connected to the back bump 30-2. The plurality of surface bumps 30-1 in the IF chip 30 are arranged in two rows at a wide pitch of 200 μm or more in order to be mounted on the connection pads 11 (FIG. 1) arranged in two rows on the wiring substrate 10. The wiring is rewired so as to be connected to the through electrode by wiring on the surface circuit layer (indicated by a broken line). The IF chip 30 has a through hole 30-5 at a position corresponding to a through hole (for example, 23-5) of the memory chip. The through hole 30-5 of the IF chip 30 is configured similarly to the through hole of the memory chip.

  Returning to FIG. 1, a through hole 10-5 is also formed in the wiring board 10 on which the chip stack is mounted. The through hole 10-5 of the wiring board 10 is formed in each memory chip of the chip stack. 21 to 24 and are arranged in the vicinity of the through holes formed in the IF chip 30.

  A sealing resin 50 is formed on one surface of the wiring substrate 10, and the chip stack is covered with the sealing resin 50. For the sealing resin 50, for example, a mold underfill material containing a filler of 10 μm or less is used, and includes a gap between the wiring substrate 10 and the chip stack and between the memory chips (between the memory chip and the IF chip). ), The through-holes of the respective memory chips and the through-holes of the wiring board are also satisfactorily filled. As an example of dimensions, the front surface bump and the back surface bump each have a height of about 10 μm, and the gap between the memory chips is about 20 μm.

  As described above, the semiconductor device according to the first embodiment includes a wiring board, a plurality of semiconductor chips stacked on the wiring board, and the plurality of semiconductor chips formed on the wiring board and covering the plurality of semiconductor chips. And a through hole is disposed in the wiring substrate and the plurality of semiconductor chips. In the semiconductor device having such a configuration, through holes formed in a plurality of semiconductor chips even when a void is generated in a gap between the wiring substrate and the chip stack and a gap between the plurality of semiconductor chips during resin molding. Since voids can be exhausted outside the package through the through holes of the wiring board, residual voids can be reduced. Thereby, the reliability of the semiconductor device can be improved. Furthermore, since a step of filling an underfill material between semiconductor chips in advance is not necessary, the assembly cost of the semiconductor device can be reduced. In addition, when the gap between the chips is set to 20 μm, the filler contained in the sealing resin is configured to have a size of less than half, for example, 10 μm or less, thereby filling the gap between the semiconductor chips. The sealing resin can be satisfactorily filled. In addition, since the underfill material supplied in advance between the semiconductor chips can be eliminated, there is no resin accumulation in the fillet portion formed on the side surface of the chip stack, and the semiconductor chip is applied due to curing shrinkage of the underfill material. Stress can be reduced.

  4 to 6 are cross-sectional views illustrating the assembly process of the semiconductor device according to the first embodiment.

  First, with reference to FIG. 4, a process of stacking memory chips (semiconductor chips) will be described.

  In FIG. 4A, the memory chip 24 which is the uppermost stage of the chip stack is mounted on the bonding stage 100 with the surface bump 24-1 on the upper side. The memory chip 24 is held on the bonding stage 100 by a vacuum chuck that passes through the suction hole 100-1.

  In FIG. 4B, the second-stage memory chip 23 from the top of the chip stack is held and stacked on the memory chip 24 by a vacuum chuck through the suction hole 200-1 by the bonding tool 200. At the time of stacking, the back surface bump 23-2 side of the memory chip 23 is faced down, the back surface bump 23-2 is applied to the front surface bump 24-1 of the memory chip 24 by flip chip bonding, and the dummy bump 23-6 is connected to the dummy bump 24 of the memory chip 24. -4 respectively. In this way, FIG. 4B shows a state in which the memory chips 21 are stacked in the order of the memory chips 24-23-22-21.

  In FIG. 4C, the IF chip 30 which is the lowest stage of the chip stack is held and stacked on the memory chip 21 by the vacuum chuck by the bonding tool 200 as described above.

  FIG. 4D shows the chip stack obtained in the above-described stacking process, and it is not necessary to fill the underfill material in advance between the memory chips (including between the memory chip and the IF chip).

  Next, with reference to FIG. 5, the resin sealing process of the chip stack following FIG. 4 will be described.

  First, as shown in FIG. 5A, a wiring board 10 'on which a chip stack is mounted is prepared. The wiring board 10 ′ is, for example, a glass epoxy wiring board, and has a plurality of product formation regions AR arranged in a matrix. FIG. 5 (a) shows one product formation area AR and a part of the product formation areas on both sides thereof for convenience. In the following, one product formation area AR and a chip stack mounted thereon will be mainly described. explain.

  A predetermined wiring pattern is formed in each product formation area AR, and the wiring 12 is partially covered with an insulating film (for example, solder resist, 10-1 and 10-2 in FIG. 1). A dicing line DL is formed between adjacent product formation regions AR. A plurality of connection pads 11, 11 ′ are formed in a portion exposed from the insulating film of the wiring 12 on one surface side of the product formation region AR. Here, two rows of connection pads 11 are arranged in parallel so as to correspond to two rows of surface bumps 30-1 of the IF chip 30, and connection pads 11 ′ are formed for connection by the wiring 12. A plurality of lands 13 are formed in a portion exposed from the insulating film of the wiring 12 on the other surface of the product formation region AR. The connection pad 11 ′ and the land 13 corresponding to the connection pad 11 ′ are electrically connected by the wiring 12.

  Next, as shown in FIG. 5B, the wiring board 10 'is transferred to a bonding process. In this bonding step, for example, the chip stack is sucked and held on the back surface side of the uppermost memory chip 24 by a bonding tool (not shown) of a bonding apparatus (not shown). Then, the chip stack is flip-chip bonded to each product formation area AR of the wiring substrate 10 ′ by applying a load at a high temperature, for example, about 300 ° C. with a bonding tool. As a result, as shown in FIG. 5B, the chip stack is mounted in each product formation area AR of the wiring board 10 ′, and the surface bump 30-1 of the IF chip 30 and the connection pad 11 of the wiring board 10 ′. Are electrically connected. In addition, you may comprise the joining of a chip laminated body so that not only a load but an ultrasonic wave may be applied.

  Next, as shown in FIG. 5C, the wiring board 10 'on which the chip stack is mounted is transferred to a molding (resin sealing) process. In this molding process, the wiring board 10 'is set in a molding die (not shown) including an upper mold and a lower mold of a transfer mold apparatus (not shown). A cavity is formed in the upper mold of the molding die so as to collectively cover a plurality of chip mounting portions, and a chip stack on the wiring substrate 10 ′ is disposed in the cavity. Then, the sealing resin 50 melted by heating is injected into the cavity from the gate portion of the molding die, and the mounting surface side of the chip stack on the wiring substrate 10 ′ is sealed. As the sealing resin 50, for example, a thermosetting resin such as an epoxy resin is used. Then, with the cavity on one side of the wiring substrate 10 ′ filled with the sealing resin 50, the sealing resin 50 is cured by curing at a predetermined temperature, for example, about 180 ° C., and FIG. ), A layer of the sealing resin 50 that collectively covers the plurality of product formation regions AR of the wiring board 10 ′ is formed. Thereafter, the wiring substrate 10 ′ on which the sealing resin 50 layer is formed is baked at a predetermined temperature, whereby the sealing resin 50 is completely cured.

  Subsequently, referring to FIG. 5D, the wiring board 10 ′ on which the layer of the sealing resin 50 is formed is transferred to the ball mounting process, and the land 13 formed on the other surface of the wiring board 10 ′ is transferred. A conductive metal ball, for example, a solder ball 15 is mounted to form an external terminal. In this ball mounting process, a mounting tool (not shown) of a ball mounter (not shown) in which a plurality of suction holes are formed in accordance with the plurality of lands 13 arranged on the wiring board 10 'is used to remove the metal from the metal. The solder balls 15 to be formed are sucked and held by a mounting tool, and flux is transferred and formed on the sucked and held solder balls 15 to be collectively mounted on a plurality of lands 13 on the wiring board 10 ′. Then, after mounting the solder balls 15 in all the product formation areas AR, the external terminals are formed by reflowing the wiring board 10 '.

  Next, as shown in FIG. 5E, the wiring board 10 ′ on which the solder balls 15 are mounted is transferred to a substrate dicing process, and the wiring board 10 ′ is cut and separated into individual product formation regions AR. . In this substrate dicing process, a dicing tape (not shown) is attached to the layer side of the sealing resin 50 of the wiring substrate 10 ', and the wiring substrate 10' is supported by the dicing tape. Thereafter, the product is cut into vertical and horizontal directions by a dicing blade (not shown) of a dicing apparatus (not shown) and separated into product formation areas AR. Then, after cutting and separating the wiring substrate 10 ′, a plurality of CoC type semiconductor devices as shown in FIG. 5E are obtained by picking up the resin sealing body from the dicing tape.

  FIG. 6 is a cross-sectional view for explaining the reason why the generation of voids is reduced in the resin sealing step of FIG.

  As shown in FIG. 6A, when resin sealing is performed, when a sealing resin 50 in a molten state is injected into the cavity between the upper mold 300-1 and the lower mold 300-2 of the molding die, they are adjacent to each other. It is assumed that voids are generated between the memory chips, between the memory chip and the IF chip, and between the IF chip and the wiring substrate 10 ′.

  In this case, as shown in FIG. 6B, voids (bubbles) are formed in the through holes (for example, 21-5 and 30-5) formed in the respective memory chips and IF chips and in the wiring board 10 ′. The air can be exhausted outside the sealed package through the formed through hole 10-5.

  As a result, as shown in FIG. 6C, it is possible to reduce voids remaining in the gap between the wiring substrate 10 'and the chip stack and between the memory chips. In addition, since it is possible to eliminate the process of filling the underfill between the plurality of memory chips of the chip stack, the assembly cost of the semiconductor device can be reduced.

  As mentioned above, although this invention was demonstrated based on preferable embodiment, this invention is not limited to the said embodiment, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary. For example, in the above embodiment, the case where two through holes are formed and arranged in the wiring board and the plurality of memory chips (including IF chips) has been described, but one or three or more through holes are formed and arranged. You may comprise as follows. Further, the case where the formation positions of the through holes of the memory chip and the through holes of the wiring board are deviated from each other has been described.

  Furthermore, in the above embodiment, a chip stack including four memory chips and an IF chip has been described. However, any semiconductor chip such as a chip stack of a plurality of memory chips or a chip stack of a memory chip and a logic chip can be used. You may apply to a combination. Moreover, you may apply to the chip laminated body of four steps or less, or six steps or more.

10, 10 'wiring substrate 11, 11' connection pad 12 wiring 13 land 15 solder ball 21-24 memory chip 21-1, 23-1, 30-1, 24-1 surface bump 23-2, 30-2 back surface bump 23-3, 23-7, 30-3 Through electrode 21-4, 23-4, 23-6, 24-4 Dummy bump 10-5, 23-5, 30-5 Through hole 30 IF chip 50 Sealing resin 100 Bonding stage 200 Bonding tool 300-1 Upper mold 300-2 Lower mold

Claims (5)

A wiring board;
N (N is a positive integer) stage semiconductor chips stacked on the wiring board;
A sealing resin which is formed on the wiring board and covers the N-stage semiconductor chip and fills a gap between the N-stage semiconductor chips and a gap between the wiring board and the lowermost semiconductor chip. Become
Of the wiring substrate and the N-stage semiconductor chips, at least (N-1) -stage semiconductor chips have through holes, and the sealing resin is disposed in the through holes. .   The semiconductor device according to claim 1, wherein the sealing resin contains a filler, and the filler is configured to have a size of 10 μm or less.   3. The semiconductor device according to claim 1, wherein the through holes of at least (N−1) stages of the N stages of semiconductor chips are arranged at positions overlapping each other in plan view. . A step of mounting a chip laminated body composed of N (N is a positive integer) stacked semiconductor chips on a wiring board;
Covering the chip stack mounted on the wiring board and sealing with a molten resin so as to fill a gap between the N-stage semiconductor chips and a gap between the wiring board and the lowermost semiconductor chip Including the steps of:
By providing through holes in at least the (N-1) -stage semiconductor chips of the wiring board and the N-stage semiconductor chips, the N-stage semiconductor chips are sealed in the sealing step with the molten resin. A method of manufacturing a semiconductor device, wherein air bubbles generated in the gap and the gap between the wiring board and the lowermost semiconductor chip are exhausted through the through hole.   The method for manufacturing a semiconductor device according to claim 4, wherein the molten resin containing a filler is used, and the filler is configured to have a size of 10 μm or less.

Images