CN111883444A - Multi-chip stack package and manufacturing method thereof - Google Patents

Multi-chip stack package and manufacturing method thereof Download PDF

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Publication number
CN111883444A
CN111883444A CN202010800942.3A CN202010800942A CN111883444A CN 111883444 A CN111883444 A CN 111883444A CN 202010800942 A CN202010800942 A CN 202010800942A CN 111883444 A CN111883444 A CN 111883444A
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conductive
chip
layer
polymer layer
polymer
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CN111883444B (en
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侯新飞
秦岭
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Shandong Ruixin Semiconductor Technology Co ltd
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Ji Nannan Knows Information Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Nanotechnology (AREA)
  • Composite Materials (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention provides a multi-chip stack package and a manufacturing method thereof. According to the invention, the laser activated polymer material is formed among the conductive posts, and then the laser activated polymer material is ablated and activated to form the metal nano particles, so that the metal nano particles realize the joint of the upper conductive post and the lower conductive post, the height difference can be offset, and the joint reliability can be ensured. The bonding of the metal nanoparticles is stronger than conventional solder bonding. In another embodiment, the metal nanoparticles are not connected with the polymer layer on the side wall of the metal column, so that the metal side protection and the side climbing prevention of the metal nanoparticles can be realized while saving materials.

Description

Multi-chip stack package and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor device packaging, in particular to a multi-chip stacked package and a manufacturing method thereof.
Background
With the increasing integration level, more semiconductor chips need to be integrated on the package substrate. In order to save lateral space of the package substrate, a plurality of chips may be disposed to be stacked. While this stacked arrangement makes the connection posts on the outside thereof more dense, the accuracy of interconnection and the bonding strength thereof face greater challenges. Due to the different heights of the bonding conductive pillars on the package substrate, the connection often occurs with the cold joint of individual connection pillars, resulting in the open circuit of the electrical connection.
Disclosure of Invention
Based on solving the above problems, the present invention provides a method for manufacturing a multi-chip stacked package, comprising the steps of:
(1) providing a first chip having a first dimension in a lateral direction;
(2) securing a second chip on the first chip, the second chip having a second dimension in a lateral direction, wherein the first dimension is greater than the second dimension;
(3) forming a first photoresist layer and a first sub-conductive post in the first photoresist layer on the first chip, wherein the bottom surface of the first photoresist layer is flush with the bottom surface of the second chip, and the first sub-conductive post is arranged at the periphery of the second chip;
(4) forming a second photoresist layer on the first photoresist layer, and a second sub-conductive pillar and a second conductive pillar in the second photoresist layer, wherein the second conductive pillar is electrically connected to the second chip, and the first sub-conductive pillar and the second sub-conductive pillar correspond to each other up and down to form a first conductive pillar;
(5) removing the second photoresist layer to expose the second sub-conductive posts and the second conductive posts;
(6) forming a laser-activatable polymer layer at least at the bottom ends of the first and second conductive pillars;
(7) laser ablating and activating the polymer layer such that metal nanoparticles are formed at the bottom ends of the first and second conductive pillars;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
In the step (6), the forming of the polymer layer specifically includes: depositing a laser-activatable polymer on the first photoresist layer to form the polymer layer covering the first and second conductive pillars.
In step (7), laser ablating and activating the polymer layer specifically comprises: and (3) utilizing laser to conduct ablation and activation on the polymer layers of the bottom end parts of the first conductive column and the second conductive column, so that the polymer layers of the bottom end parts are activated into metal nanoparticles.
In the step (6), the forming of the polymer layer specifically includes: and infiltrating at least a part of the first conductive pillar and the second conductive pillar into the liquid of the laser-activatable polymer by adopting an infiltration method, so that the polymer layer is formed at the bottom end and at least part of the side wall of the first conductive pillar and the second conductive pillar.
Wherein laser ablating and activating the polymer layer specifically comprises: and (3) utilizing laser to conduct ablation and activation on the polymer layers of the bottom end parts of the first conductive column and the second conductive column, so that the polymer layers of the bottom end parts are activated into metal nanoparticles, and the metal nanoparticles are not connected with the polymer layers on the side walls of the first metal column and the second metal column.
The present invention also provides a multi-chip stack package, comprising:
a first chip having a first dimension in a lateral direction;
a second chip fixed on the first chip, wherein the second chip has a second size in the transverse direction, and the first size is larger than the second size;
the first light resistance layer is arranged on the first chip and around the second chip;
the first conductive column is arranged on the first chip and partially extends out of the first photoresist layer;
the second conductive column is arranged on the second chip, and the bottom ends of the first conductive column and the second conductive column are flush;
the metal nano particles are arranged at the bottom ends of the first conductive column and the second conductive column;
and the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are jointed with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
Also included is a polymer layer formed from a laser-activatable polymer material, the polymer layer encapsulating sidewalls of the first and second conductive posts.
An underfill layer is also included.
The bottom filling layer is filled between the packaging substrate and the first light resistance layer and wraps the polymer layer.
Wherein the underfill layer is filled between the polymer layer and the package substrate.
According to the invention, the laser activated polymer material is formed among the conductive posts, and then the laser activated polymer material is ablated and activated to form the metal nano particles, so that the metal nano particles realize the joint of the upper conductive post and the lower conductive post, the height difference can be offset, and the joint reliability can be ensured. The bonding of the metal nanoparticles is stronger than conventional solder bonding. In another embodiment, the metal nanoparticles are not connected with the polymer layer on the side wall of the metal column, so that the metal side protection and the side climbing prevention of the metal nanoparticles can be realized while saving materials.
Drawings
FIG. 1 is a cross-sectional view of a first embodiment of a multi-chip stack package;
FIGS. 2-7 are schematic diagrams of a method of manufacturing a multi-chip stack package of the first embodiment;
FIG. 8 is a cross-sectional view of a second embodiment of a multi-chip stack package;
fig. 9-16 are schematic diagrams of a method of manufacturing a multi-chip stack package of a second embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
First embodiment
Referring to fig. 1, the multi-chip stack package of the present invention includes an upper package assembly and a lower package substrate 18. The package assembly is a stacked chip package assembly that is electrically connected to the underlying package substrate 18 by a plurality of conductive posts.
The package assembly comprises at least two stacked first chips 10 and second chips 11, wherein the size of the first chip 10 is larger than the size of the second chip 11. The first chip 10 and the second chip 11 may be any possible functional chips, including active chips, such as MOS, JFET, IGBT, etc., or passive chips, such as resistors, inductors, capacitors.
The second chip 11 is stacked under the first chip 10 and fixedly bonded by an adhesive layer 12. The second chip 11 is sealed in the photoresist layer 15, and the first chip 10 is disposed on the photoresist layer 15. A plurality of conductive pillars 13 are electrically connected to the first chip 10, and are all located around the second chip 11. A plurality of conductive posts extend from the photoresist layer 15 to form a portion having a connecting terminal.
The conductive pillars 14 are electrically connected to the second chip 11, and the bottom ends of the conductive pillars 13 and 14 are flush. The conductive posts 13 and a portion of the conductive posts 14 are encapsulated by a laser activatable polymeric material to form a polymeric layer 16.
The first conductive pillar 4 and the second conductive pillar 5 are made of the same metal material, such as Cu, Al, W, etc., and are formed by a conventional method, such as electroplating.
As the most important part of the present invention, the polymer layer 16 includes a resin and a metal complex, such as a copper complex, a silver complex, etc., which can be ablated and activated by laser, remove the organic material thereof, and allow the metal complex to form metal nanoparticles 17. During fabrication, the bottom ends of polymer layer 16 are slightly lower than the bottom ends of conductive pillars 13 and 14, and then laser activation is performed, so that the material in direct contact with the bottom ends of conductive pillars 13 and 14 becomes metal nanoparticles 17.
The package substrate 18 has a plurality of conductive pillars 19, the conductive pillars 19 are disposed corresponding to the conductive pillars 13 and 14, and the conductive pillars 19 and the conductive pillars 13 and 14 are respectively bonded by heating the metal nanoparticles at the bottom ends of the conductive pillars 13 and 14.
The heights of the conductive pillars 19 may be different, for example, the height difference may be 0.5 to 1 μm. Heating the metal nanoparticles 17 forms a metal sintered layer between the conductive pillars 19 and the conductive pillars 13 and 14, and the thickness of the metal sintered layer is different, so that the conductive pillars 19 with different heights can be effectively bonded to the conductive pillars 13 or 14, and poor bonding caused by the height difference can be offset.
In addition, an underfill layer 20 is further included between the package substrate 18 and the polymer layer 16, and the underfill layer 20 wraps the conductive pillars 19.
In addition, the embodiment also provides a manufacturing method of the multi-chip stack package, which comprises the following steps:
(1) providing a first chip having a first dimension in a lateral direction;
(2) securing a second chip on the first chip, the second chip having a second dimension in a lateral direction, wherein the first dimension is greater than the second dimension;
(3) forming a first photoresist layer and a first sub-conductive post in the first photoresist layer on the first chip, wherein the bottom surface of the first photoresist layer is flush with the bottom surface of the second chip, and the first sub-conductive post is arranged at the periphery of the second chip;
(4) forming a second photoresist layer on the first photoresist layer, and a second sub-conductive pillar and a second conductive pillar in the second photoresist layer, wherein the second conductive pillar is electrically connected to the second chip, and the first sub-conductive pillar and the second sub-conductive pillar correspond to each other up and down to form a first conductive pillar;
(5) removing the second photoresist layer to expose the second sub-conductive posts and the second conductive posts;
(6) forming a laser-activatable polymer layer at least at the bottom ends of the first and second conductive pillars;
(7) laser ablating and activating the polymer layer such that metal nanoparticles are formed at the bottom ends of the first and second conductive pillars;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
The method for manufacturing the multi-chip stacked package provided by the present invention is described in detail below with reference to fig. 2-8.
First, referring to fig. 2, a first chip 10 and a second chip 11 are provided, the first chip 10 having a first size in a lateral direction, the second chip 11 having a second size, wherein the first size is larger than the second size. The second chip 11 is fixed to the bottom surface of the first chip 10 by an adhesive layer 12.
Next, referring to fig. 3, a photoresist layer 15 and a first sub-conductive pillar 131 in the photoresist layer 15 are formed on the first chip 10, a bottom surface of the photoresist layer 15 is flush with a bottom surface of the second chip 11, and the first sub-conductive pillar 131 is disposed at a periphery of the second chip 11.
Referring to fig. 4, another photoresist layer 9 and the second sub-conductive pillars 132 and the conductive pillars 14 in the another photoresist layer 9 are formed on the photoresist layer 15, wherein the conductive pillars 14 are electrically connected to the second chip 11, and the conductive pillars 13 are correspondingly formed above and below the first sub-conductive pillars 131 and the second sub-conductive pillars 132.
Referring to fig. 5, the another photoresist layer 9 is removed to expose the second sub-conductive pillars 132 and the conductive pillars 14. It should be noted that the material of the photoresist layer 15 is different from that of the other photoresist layer 9, so that the photoresist layer 15 can be remained when the photoresist layer 9 is removed to achieve the purpose of saving material.
Referring to fig. 6, a laser-activatable polymer layer 16 is deposited over the photoresist layer 15 to form the polymer layer 16 overlying the conductive pillars 13 and 14.
Referring then to fig. 7, the polymer layer 16 of the bottom end portions of the conductive pillars 13 and 14 is ablated and activated by laser, so that the polymer layer 16 of the bottom end portions is activated into metal nanoparticles 17.
Then, referring to fig. 8, a package substrate 18 is provided, where the package substrate 18 has a plurality of conductive pillars 19, the third conductive pillars 19 correspond to the conductive pillars 13 and 14 one by one, and the bonding of the conductive pillars 19 with the conductive pillars 13 and 14 is achieved by heating the metal nanoparticles 17. And an underfill layer 20 is formed between the package substrate 18 and the polymer layer 16, wherein the underfill layer 20 encapsulates the conductive pillars 19.
In the embodiment, the laser activated polymer material is formed among the plurality of conductive posts, and then the laser activated polymer material is ablated and activated to form the metal nanoparticles, so that the metal nanoparticles can realize the bonding of the upper conductive post and the lower conductive post, can offset the height difference, and can ensure the reliability of the bonding. The bonding of the metal nanoparticles is stronger than conventional solder bonding.
Second embodiment
Referring to fig. 9, the multi-chip stack package of this embodiment is similar to the first embodiment except that a polymer layer 21 of a laser-activatable polymer material is formed only on the sidewalls of the conductive posts 13 protruding from the photoresist layer 15 and the sidewalls of the conductive posts 14, and an underfill layer 20 is interposed between the photoresist layer 15 and the package substrate 18 and completely encapsulates the polymer layer 21.
In this embodiment, the metal nanoparticles 22 at the bottom ends of the conductive pillars 13 and 14 are also formed by laser activating the polymer layer 21, except that after activation, the metal nanoparticles 22 are not connected to the polymer layer 21 on the side walls of the metal pillars 13 and 14, because the polymer layer 21 is thin, and due to the difference in wettability, the metal nanoparticles do not climb along the side walls of the metal pillars 13 and 14 after sintering.
In addition, the manufacturing method of the embodiment also comprises the following steps:
(1) providing a first chip having a first dimension in a lateral direction;
(2) securing a second chip on the first chip, the second chip having a second dimension in a lateral direction, wherein the first dimension is greater than the second dimension;
(3) forming a first photoresist layer and a first sub-conductive post in the first photoresist layer on the first chip, wherein the bottom surface of the first photoresist layer is flush with the bottom surface of the second chip, and the first sub-conductive post is arranged at the periphery of the second chip;
(4) forming a second photoresist layer on the first photoresist layer, and a second sub-conductive pillar and a second conductive pillar in the second photoresist layer, wherein the second conductive pillar is electrically connected to the second chip, and the first sub-conductive pillar and the second sub-conductive pillar correspond to each other up and down to form a first conductive pillar;
(5) removing the second photoresist layer to expose the second sub-conductive posts and the second conductive posts;
(6) forming a laser-activatable polymer layer at least at the bottom ends of the first and second conductive pillars;
(7) laser ablating and activating the polymer layer such that metal nanoparticles are formed at the bottom ends of the first and second conductive pillars;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
Referring specifically to fig. 10-16, unlike the first embodiment, referring to fig. 14, in step (6), forming the polymer layer 21 specifically includes: at least a portion of conductive pillars 13 and 14 are immersed in the liquid of the laser-activatable polymer, so that polymer layer 21 is formed at the bottom ends and at least a portion of the sidewalls of conductive pillars 13 and 14.
Referring to fig. 15, in step (7), laser ablating and activating the polymer layer 21 specifically includes: the polymer layer 21 at the bottom end portions of the conductive pillars 13 and 14 is ablated and activated by laser, so that the polymer layer 21 at the bottom end portions is activated into metal nanoparticles 22, and the metal nanoparticles 22 are not connected with the polymer layer on the side walls of the conductive pillars 13 and 14, which is caused by the co-flow of the homogeneous material due to laser ablation.
And finally, after the conductive pillars 19 on the package substrate 18 are bonded, the underfill layer 20 is filled between the photoresist layer 15 and the package substrate 18.
In this embodiment, the metal nanoparticles are not connected to the polymer layer on the sidewall of the metal pillar, which can save material and achieve metal side protection and prevent the side climbing of the metal nanoparticles, which is better than the first embodiment.
In addition, the metal nano-particle forming method of the invention can avoid the complex process of the traditional electroplating method (without electricity or with electricity), and can prevent the electroplating corrosion of the metal column.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.

Claims (10)

1. A method of manufacturing a multi-chip stack package, comprising the steps of:
(1) providing a first chip having a first dimension in a lateral direction;
(2) securing a second chip on the first chip, the second chip having a second dimension in a lateral direction, wherein the first dimension is greater than the second dimension;
(3) forming a first photoresist layer and a first sub-conductive post in the first photoresist layer on the first chip, wherein the bottom surface of the first photoresist layer is flush with the bottom surface of the second chip, and the first sub-conductive post is arranged at the periphery of the second chip;
(4) forming a second photoresist layer on the first photoresist layer, and a second sub-conductive pillar and a second conductive pillar in the second photoresist layer, wherein the second conductive pillar is electrically connected to the second chip, and the first sub-conductive pillar and the second sub-conductive pillar correspond to each other up and down to form a first conductive pillar;
(5) removing the second photoresist layer to expose the second sub-conductive posts and the second conductive posts;
(6) forming a laser-activatable polymer layer at least at the bottom ends of the first and second conductive pillars;
(7) laser ablating and activating the polymer layer such that metal nanoparticles are formed at the bottom ends of the first and second conductive pillars;
(8) providing a packaging substrate, wherein the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are connected with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
2. The method of manufacturing a multi-chip stack package of claim 1, wherein: in the step (6), the forming of the polymer layer specifically includes: depositing a laser-activatable polymer layer on the first photoresist layer to form the polymer layer covering the first and second conductive pillars.
3. The method of manufacturing a multi-chip stack package of claim 2, wherein: in step (7), laser ablating and activating the polymer layer specifically comprises: and (3) utilizing laser to conduct ablation and activation on the polymer layers of the bottom end parts of the first conductive column and the second conductive column, so that the polymer layers of the bottom end parts are activated into metal nanoparticles.
4. The method of manufacturing a multi-chip stack package of claim 1, wherein: in the step (6), the forming of the polymer layer specifically includes: and infiltrating at least a part of the first conductive pillar and the second conductive pillar into the liquid of the laser-activatable polymer by adopting an infiltration method, so that the polymer layer is formed at the bottom end and at least part of the side wall of the first conductive pillar and the second conductive pillar.
5. The method of manufacturing a multi-chip stack package of claim 4, wherein: in step (7), laser ablating and activating the polymer layer specifically comprises: and (3) utilizing laser to conduct ablation and activation on the polymer layers of the bottom end parts of the first conductive column and the second conductive column, so that the polymer layers of the bottom end parts are activated into metal nanoparticles, and the metal nanoparticles are not connected with the polymer layers on the side walls of the first metal column and the second metal column.
6. A multi-chip stack package, comprising:
a first chip having a first dimension in a lateral direction;
a second chip fixed on the first chip, wherein the second chip has a second size in the transverse direction, and the first size is larger than the second size;
the first light resistance layer is arranged on the first chip and around the second chip;
the first conductive column is arranged on the first chip and partially extends out of the first photoresist layer;
the second conductive column is arranged on the second chip, and the bottom ends of the first conductive column and the second conductive column are flush;
the metal nano particles are arranged at the bottom ends of the first conductive column and the second conductive column;
and the packaging substrate is provided with a plurality of third conductive columns, the third conductive columns correspond to the first conductive columns and the second conductive columns one by one, and the third conductive columns are jointed with the first conductive columns and the second conductive columns by heating the metal nanoparticles.
7. The multi-chip stack package of claim 6, wherein: also included is a polymer layer formed from a laser-activatable polymer material, the polymer layer encapsulating sidewalls of the first and second conductive posts.
8. The multi-chip stack package of claim 6, wherein: an underfill layer is also included.
9. The multi-chip stack package of claim 8, wherein: the bottom filling layer is filled between the packaging substrate and the first light resistance layer and wraps the polymer layer.
10. The multi-chip stack package of claim 6, wherein: wherein the underfill layer is filled between the polymer layer and the package substrate.
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CN102543939A (en) * 2012-01-05 2012-07-04 三星半导体(中国)研究开发有限公司 Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof
CN107230644A (en) * 2016-03-25 2017-10-03 胡迪群 Metal column with metal sponge
CN107924878A (en) * 2015-07-10 2018-04-17 英帆萨斯公司 Structures and methods for low temperature engagement

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CN102543939A (en) * 2012-01-05 2012-07-04 三星半导体(中国)研究开发有限公司 Laminated inverted chip packaging structure for superfine-pitch welding pads and manufacturing method thereof
CN107924878A (en) * 2015-07-10 2018-04-17 英帆萨斯公司 Structures and methods for low temperature engagement
CN107230644A (en) * 2016-03-25 2017-10-03 胡迪群 Metal column with metal sponge

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* Cited by examiner, † Cited by third party
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CN113078118A (en) * 2021-03-25 2021-07-06 福唐激光(苏州)科技有限公司 Method for realizing POP (point of presence protocol) connection by laser and POP structure thereof

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