CN109801894A - Chip-packaging structure and packaging method - Google Patents
Chip-packaging structure and packaging method Download PDFInfo
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- CN109801894A CN109801894A CN201811626564.0A CN201811626564A CN109801894A CN 109801894 A CN109801894 A CN 109801894A CN 201811626564 A CN201811626564 A CN 201811626564A CN 109801894 A CN109801894 A CN 109801894A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000011521 glass Substances 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000000605 extraction Methods 0.000 claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 2
- 238000006263 metalation reaction Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 101
- 238000005538 encapsulation Methods 0.000 description 7
- 241000218202 Coptis Species 0.000 description 3
- 235000002991 Coptis groenlandica Nutrition 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ICXAPFWGVRTEKV-UHFFFAOYSA-N 2-[4-(1,3-benzoxazol-2-yl)phenyl]-1,3-benzoxazole Chemical compound C1=CC=C2OC(C3=CC=C(C=C3)C=3OC4=CC=CC=C4N=3)=NC2=C1 ICXAPFWGVRTEKV-UHFFFAOYSA-N 0.000 description 1
- PEPBFCOIJRULGJ-UHFFFAOYSA-N 3h-1,2,3-benzodioxazole Chemical compound C1=CC=C2NOOC2=C1 PEPBFCOIJRULGJ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229920000265 Polyparaphenylene Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polyparaphenylene Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of chip-packaging structure and packaging methods, comprising: the first chip and the second chip of the opposite fitting in bottom surface；Multiple conductive columns are distributed in around the first chip；Lead is connected between the second chip front side and the first face of metal terminal；Encapsulated layer, encapsulate the first chip, the second chip, lead, conductive column, with first surface and with the opposed second surface of first surface, first surface exposure the first chip front and conductive column the second face, second surface exposure the second chip front side predeterminable area；Layer is drawn, is arranged on the first surface of encapsulated layer, is electrically connected respectively with the front of the first face of conductive column and/or the first chip.It is connected between the chip of stacking, no setting is required, and substrate is transferred, and chip is drawn pad by lead and conductive column at the middle and upper levels, can satisfy being fanned out to for stacked chips pin, the predeterminable area that the second chip front side of exposure is formed on encapsulated layer, preferably meets the application of certain chip.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, and in particular to a kind of chip-packaging structure and packaging method.
Background technique
With the development of semi-conductor industry, for the lasting need to more inexpensive, higher performance, bigger integrated circuit density
It asks, stacked package (Package on Package, POP) technology is more more and more universal；Especially as mobile communication equipment
It rises, the integrated standard configuration for more almost becoming high-end product of system on chip (SoC) technology and memory technology.
It is formed by stacking currently, POP generallys use upper layer and lower layer encapsulation, encapsulates interior chip and pass through gold thread bonding bottom packaging body
Onto substrate, likewise, the substrate between two encapsulated layers is bonded by the chip in the encapsulation of upper layer again by gold thread, then entirely
It is packaged into the packaging body of an entirety.However in encapsulation process, the packaging body of stacked on top requires to stack envelope using substrate
The whole height of dress is higher, it is difficult to meet the needs of miniaturization of electronic products.
Summary of the invention
Therefore, the present invention provides a kind of chip-packaging structure, reduces the buckling deformation of packaging body.
According in a first aspect, including at least the embodiment of the invention provides a kind of chip-packaging structure: bottom surface is opposite to be bonded
The first chip and the second chip；Multiple metal terminals are distributed in around first chip, the one side of the metal terminal with
The front of first chip is in same plane；Lead, be connected to second chip front side and metal terminal another side it
Between；Encapsulated layer encapsulates first chip, the second chip, lead and metal terminal, has first surface and with described first
The opposed second surface in surface, the first surface is with the one side of the metal terminal and the front of first chip same
One plane；Draw layer, be arranged on the first surface of the encapsulated layer, respectively with the first chip of one side of the metal terminal
Front electrical connection.
Optionally, the extraction layer includes: the first rewiring layer, and the wiring layer is formed in the first table of the encapsulated layer
Face is electrically connected with the one side of first chip front side and part metals terminal.Via hole.
Optionally, the extraction layer further include: the surface of the wiring layer is arranged in dielectric layer, has multiple via holes；The
Double wiring layer, setting reroute layer, the metal end with described first respectively in the dielectric layer surface, by the via hole
At least one of the one side of son and the front of first chip are electrically connected.
Optionally, layer is drawn further include: pin is distributed in described second and reroutes on layer.
Optionally, the front of the one side of the first surface exposure metal terminal of the encapsulated layer and the first chip.
Optionally, the encapsulated layer includes plastic packaging layer.
It optionally, include appointing in welding layer, sinter layer or adhesive layer between first chip and second chip
It anticipates one kind.
According to second aspect, the embodiment of the invention provides a kind of chip packaging methods, comprising: provides a slide glass；Institute
It states and stacks gradually the second chip of the first chip of upside-down mounting and formal dress on slide glass；Multiple metal ends are set around first chip
Son；The connecting lead wire between the positive and corresponding metal terminal of second chip；Encapsulation is formed on the slide glass
Layer, to encapsulate first chip, second chip, the lead and the metal terminal；Remove the slide glass and in institute
State the one side formation extraction layer that encapsulated layer removes the slide glass.
Optionally, described to remove the slide glass and form extraction layer packet in the one side that the encapsulated layer removes the slide glass
It includes: removing the slide glass and form the first rewiring layer in the one side that the encapsulated layer removes the slide glass；In first weight
Dielectric layer is formed on wiring layer；Via hole is formed on the dielectric layer；Second is formed on the dielectric layer and reroutes layer, is passed through
The via hole reroutes in layer, the one side of the metal terminal and the front of first chip extremely with described first respectively
One of few electrical connection；Corresponding position forms multiple pins on the second rewiring layer.
Optionally, encapsulated layer is formed on the slide glass includes: in a manner of injection molding in first chip, described second
Region where chip and the metal terminal forms encapsulated layer.
Technical solution of the present invention has the advantages that
Chip-packaging structure in compared with the prior art connects between the chip of stacking, and no setting is required, and substrate is turned
It connecing, chip is drawn pad by lead and conductive column at the middle and upper levels, it can satisfy being fanned out to for stacked chips pin, in addition,
The predeterminable area that the second chip front side of exposure is formed on encapsulated layer, can preferably meet the application of certain chip.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the exemplary structure chart in chip assembling structure provided in an embodiment of the present invention section；
Fig. 2~Figure 13 is that the packaging method of chip-packaging structure provided in an embodiment of the present invention specifically shows flow chart.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments
It can be combined with each other at conflict.
The embodiment of the present invention provides a kind of chip-packaging structure, as shown in Figure 1, the structure includes: the opposite fitting in bottom surface
First chip 10 and the second chip 20；Multiple conductive columns 30 are distributed in around first chip 10, and the of the conductive column 30
On one side with the front of first chip 10 in same plane；Lead 40 is connected to 20 front of the second chip and conductive column
Between 30 another side；First encapsulated layer 51, encapsulates first chip 10 and conductive column 30, the second encapsulated layer 52, encapsulating the
Two chips 20, lead 40, the first encapsulated layer 51 and the second encapsulated layer 52 form encapsulated layer 50, encapsulated layer 50 have first surface and
With the opposed second surface of the first surface, the front of the first surface exposure first chip 10 and conductive column 30
The second face, the second surface exposure positive predeterminable area of second chip 20 draws layer 60, is arranged in the encapsulation
On the first surface of layer 50, it is electrically connected respectively with the front of first the first chip of face 10 of the conductive column 30.In the present embodiment
In, alleged second chip 10 can be detection chip, for example, can be temperature sensing chip, photodetection chip etc. detects core
Piece, alleged predeterminable area are search coverage.In the present embodiment, encapsulated layer exposure detecting layer need to carry on the back the front of the second chip
It is packaged to the first chip.
Chip-packaging structure in compared with the prior art connects between the chip of stacking, and no setting is required, and substrate is turned
It connecing, chip is drawn pad by lead and conductive column at the middle and upper levels, it can satisfy being fanned out to for stacked chips pin, in addition,
The predeterminable area that the second chip front side of exposure is formed on encapsulated layer, can preferably meet the application of certain chip.
As optional embodiment, the encapsulated layer 50 includes the first encapsulated layer 51, encapsulates first chip 10, and sudden and violent
Reveal the back side of first chip 10.Second encapsulated layer 52 is arranged on first encapsulated layer 51, encapsulates second chip
20, and the exposure positive predeterminable area of second chip 20.Encapsulated layer 50 is divided for layer in the present embodiment, encapsulates respectively
One chip 10 and the second chip 20, can conveniently make conductive column 30.
The conductive column 30 runs through first encapsulated layer 51, and the first face of the conductive column 30 is in first encapsulated layer
The surface of one side towards first chip back has extension.The surface of the extension has to be adapted to the lead
Coating 32.In the present embodiment, alleged conductive column 10 can fill blind hole 31 by metal and obtain, can also will be preforming
Conductive column installation, then be packaged.The coating on the surface of alleged extension can be Ni/Pd/Au coating.It can be in wire bonding
When not only improve the bonding force of lead, the electric conductivity of lead and conductive column can also be improved.
In the present embodiment, the first chip 10 and the second chip 20 can be stacked in a manner of the opposite fitting in bottom surface, in addition,
As optional embodiment, it can also include multiple chips, layer chip is set between the first chip 10 and the second chip 20, specifically
, transition zone can be set between each chip, which does not cover adjacent chips front pad, above the first chip 10
The front pad of the chip of stacking passes through lead 40 and is connected to conductive column 30.In the present embodiment, the first chip 10 and second
The connection type of chip 20 can be conductive adhesive, and solder welding can also be fit together in the form of sintering.
As optional embodiment, drawing layer 60 includes: first medium layer 61, and the first face of the encapsulated layer 60 is arranged in
On, there is the first through hole 62 opposite with 30 second face of conductive column, the pad of the first chip 10；Layer 63 is rerouted, it is described
Wiring layer is formed in the one side that the first medium layer deviates from the encapsulated layer 50, passes through the first through hole 62 and the conduction
The electrical connection of the pad of second face of column 30 and the first chip 10；Second dielectric layer 64, setting deviate from institute in the rewiring layer 63
The one side of first medium layer 61 is stated, there is the second through-hole 65；Pin 66 is distributed in the second through-hole 65.In the present embodiment, alleged
First medium layer 61 and second dielectric layer 63 can be polyparaphenylene's benzo dioxazole fiber (Poly-p-phenylene
Benzobisoxazole, PBO), the organic dielectric materials such as polyimide material, alleged pin 66 can be spherical pin, can also
Think pillar-shaped leads.
A kind of chip packaging method is present embodiments provided, in conjunction with Fig. 2-Figure 10, by the detailed encapsulating structure of introducing
The production method of manufacturing process, the encapsulating structure may include steps of:
Step S1: provide a slide glass 100, the slide glass 100 have first surface and with opposed second table of first surface
The first chip of upside-down mounting 10 is folded in face on first surface.
In the present embodiment, slide glass 100 can be silicon substrate or glass substrate, in the present embodiment, the first chip 10
The first surface of slide glass 100 can be inverted in by way of attachment.Structure shown in Fig. 2 is formed by executing step S1.
S2. the first encapsulated layer 51 is made, the first chip 10 is encapsulated, the first chip 10 back is thinned to the first encapsulated layer 51
Face.First encapsulated layer 51 is away from the back side of one side exposure first chip 10 of the slide glass 100.By executing step
S2 forms structure shown in Fig. 3.
S3. the blind hole 31 for running through first encapsulated layer is formed on first encapsulated layer 51.In the present embodiment, may be used
To make the blind hole by photoetching or laser, structure shown in Fig. 4 is formed by executing step S3.
S4. metal fills blind hole 31, and the surface of the one side away from the slide glass in first encapsulated layer 51 is formed
Extension.In the present embodiment, blind hole 31 can be electroplated, plating metal emits the upper surface for being plating to the first encapsulated layer.By holding
Row step S4 forms structure shown in fig. 5.
S5. the coating 32 being adapted to the lead is plated in the extension surface metalation.It in the present embodiment, can be right
Ni/Pd/Au layers are plated to the metallization for plating out the first encapsulated layer upper surface is emitted.Structure shown in fig. 6 is formed by executing step S5.
S6. second chip 20 described in the back side formal dress of first chip 10.In the present embodiment, the second chip 20 can
To be attached to 10 back side of the first chip by welding or bonding.Structure shown in Fig. 7 is formed by executing step S6.
S7. it connects and draws between the front pad of second chip 20 and the conductive column 30 corresponding with the pad
Line 40.It in the present embodiment, connecting lead wire, the lead can be able to be gold thread or aluminum steel by way of bonding.Pass through execution
Step S7 forms structure shown in Fig. 8.
S8. the second encapsulated layer 52 is made on first encapsulated layer 51, at described 52 layers of second encapsulation away from described the
The predeterminable area of second chip 20 described in the one side face of one encapsulated layer 51 opens up groove 53, the exposure predeterminable area.Pass through
It executes step S8 and forms structure shown in Fig. 9.
S9. it removes the slide glass 100 and is formed in the one side that the encapsulated layer 50 removes the slide glass and draw layer 60.Pass through
It executes step S9 and forms structure shown in Fig. 10.Specific step S9 may include steps of:
S91. first medium layer 61 is formed in the one side that the encapsulated layer 50 removes the slide glass, and in first medium layer 61
It is upper to form the first through hole 62 opposite with 30 second face of conductive column, the pad of the first chip 10.By executing step S91 shape
At structure shown in Figure 11.
S92. it is formed in the first medium layer 61 away from the one side of the encapsulated layer and reroutes layer 63, pass through described first
Through-hole 62 is electrically connected with the pad in the second face of the conductive column 30 and the first chip 10.Figure 12 is formed by executing step S92
Shown in structure.
S93. second dielectric layer 64 is formed away from the one side of the first medium layer 61 in the rewiring layer 63, and the
The second through-hole 65 is formed on second medium layer 64, which, which is connected to, reroutes layer 63.First medium layer 61 and second dielectric layer 63
Can be made by spin coating PI/PBO class organic dielectric material mode, first through hole 62 and the second through-hole 64 can by photoetching or
The mode of laser boring is realized.Structure shown in Figure 13 is formed by executing step S92.
S94. the multiple pins 66 of shape in the second through-hole.Structure shown in Fig. 10 is formed by executing step S94.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And thus amplify out it is obvious variation or
It changes still within the protection scope of the invention.
Claims (9)
1. a kind of chip-packaging structure, which is characterized in that include at least:
The first chip and the second chip of the opposite fitting in bottom surface；
Multiple conductive columns are distributed in around first chip；
Lead is connected between second chip front side and the first face of metal terminal；
Encapsulated layer encapsulates first chip, the second chip, lead, conductive column, have first surface and with the first surface
Opposed second surface, the front of the first surface exposure first chip and the second face of the conductive column, it is described
The predeterminable area of second surface exposure second chip front side；
Draw layer, be arranged on the first surface of the encapsulated layer, respectively with the first face of the conductive column and/or the first chip
Front electrical connection.
2. chip-packaging structure as described in claim 1, which is characterized in that the encapsulated layer includes the first encapsulated layer, encapsulating
First chip, and the back side of exposure first chip.
Second encapsulated layer is arranged on first encapsulated layer, encapsulates second chip, and exposure second chip front side
Predeterminable area.
3. chip-packaging structure as claimed in claim 2, which is characterized in that
The conductive column runs through first encapsulated layer, and the first face of the conductive column is in first package level to described the
The surface of the one side of one chip back has extension.
4. chip-packaging structure as claimed in claim 3, which is characterized in that
The surface of the extension has the coating being adapted to the lead.
5. chip-packaging structure as described in claim 1, which is characterized in that
Second chip is detection chip, and the predeterminable area is search coverage.
6. chip-packaging structure according to claim 1, which is characterized in that the extraction layer includes: first medium layer, if
It sets on the first face of the encapsulated layer, there is the first through hole opposite with second face of conductive column, the pad of the first chip；
Layer is rerouted, the layer that reroutes is formed in the one side that the first medium layer deviates from the encapsulated layer, by described logical
Hole is electrically connected with the pad in the second face of the conductive column and the first chip；
Second dielectric layer is arranged in the one side that the rewiring layer deviates from the first medium layer, has the second through-hole；
Pin is distributed in the second through-hole.
7. a kind of chip packaging method characterized by comprising
One slide glass and the first chip of upside-down mounting on the slide glass are provided, the first encapsulated layer is made, first encapsulated layer deviates from institute
State the back side of one side exposure first chip of slide glass；
The conductive column for running through first encapsulated layer is formed on first encapsulated layer；
The second chip described in the back side formal dress of first chip, and the front pad of second chip and with the weldering
Connecting lead wire between the corresponding conductive column of disk；
The second encapsulated layer is made on first encapsulated layer；
The predeterminable area fluting of the second chip described in one side face of second encapsulated layer away from first encapsulated layer, cruelly
Reveal the predeterminable area；
It removes the slide glass and is formed in the one side that first encapsulated layer removes the slide glass and draw layer.
8. packaging method as claimed in claim 7, which is characterized in that described to be formed on first encapsulated layer through described
The conductive column of first encapsulated layer includes:
The blind hole for running through first encapsulated layer is formed on first encapsulated layer；
Metal fills the blind hole, and forms extension on the surface of the one side away from the slide glass of first encapsulated layer；
The coating being adapted to the lead is plated in the extension surface metalation.
9. packaging method as claimed in claim 8, which is characterized in that
First medium layer is formed in the one side that the encapsulated layer removes the slide glass；
It is formed in the first medium layer away from the one side of the encapsulated layer and reroutes layer；
Second dielectric layer is formed away from the one side of the first medium layer in the rewiring layer；
The multiple pins of shape in the second through-hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811626564.0A CN109801894A (en) | 2018-12-28 | 2018-12-28 | Chip-packaging structure and packaging method |
Applications Claiming Priority (1)
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