JP2003347477A - Substrate, substrate for semiconductor package, semiconductor device and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate which is a substrate for a semiconductor package or the like and can form a smaller semiconductor package without changing a minimum wiring pitch and the number of terminals of BGA and CSP, and changing wiring rule of a wiring board. <P>SOLUTION: This substrate is provided with an insulating resin layer, metal pillars for interlayer connection which are embedded in the insulating resin layer and penetrate as far as both surfaces of the insulating resin layer, and circuits which are formed at least on a single side surface of the insulating resin layer, at positions just above the metal pillars. The metal pillars are formed by etching a metal foil, and pads for connection are formed on the circuits just above the metal pillars. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate used for a semiconductor device, a substrate for a semiconductor package, a semiconductor device using the substrate, and a semiconductor package.

[0002]

2. Description of the Related Art Along with demands for miniaturization and high performance of electronic equipment, the degree of integration of semiconductors has been improved, and the density and miniaturization of semiconductor packages on which the semiconductors are mounted have been progressing.
Until now, surface mount type semiconductor packages have been transitioning from conventional lead frame type SOPs and GFPs to BGAs and CSPs using wiring boards. Is desired. BGA and C of such area array mounting type
The minimum external dimensions of the SP substrate are determined by the number of external connection terminals, the terminal pitch, the minimum wiring rule of the substrate, and the wiring rules that allow the formation of a wiring board on which this is mounted. In other words, it means that the wiring pitch becomes smaller as the number of terminals increases, and the minimum outer dimension is determined by the minimum pitch of the wiring that can be formed.

[0003] In a conventional semiconductor package substrate in which interlayer connection is performed by through-hole plating or laser via hole filling plating, it is difficult to arrange connection pads on the substrate directly above the interlayer connection portion. A connection pad is formed at the end of the circuit that is routed from. This wiring of the circuit is one factor that hinders downsizing of the substrate. Current minimum wiring pitch is typically 50 μm
When the pitch of the external connection terminals of the BGA or CSP is 0.5 mm, the outer dimensions of the 400 terminals are about 12 mm square.

FIG. 2 is a cross-sectional view of a conventional semiconductor package using a semiconductor package substrate using a through-hole plating connection. The semiconductor chip 5 is mounted on the insulating resin layer 6 on which the through-hole plating connection portion 4 is formed, and is sealed with the sealing material 8. On the upper surface and the lower surface of the insulating resin layer 6, a circuit 11 connected to the through-hole plating connection portion 4 is provided. The upper and lower circuits 11 are plated with Ni / Au 9. The lower surface of the substrate is coated with a solder resist 12 exposing the solder ball pads, and solder bumps 10 are provided on the solder ball pads. In such a semiconductor package substrate, a connection pad for wire bonding with the semiconductor chip 5 using the gold wire 7 cannot be provided directly above the through-hole plating connection portion 4. And the connection pad 2 is arranged at the tip, that is, at the circuit portion on the insulating resin.

[0005] JP-A-2002-043467 discloses that
A semiconductor package is described in which a metal bump (metal column) formed by half-etching one surface of a metal foil is embedded with a resin and used for wiring for interlayer connection of a substrate. FIG.
FIG. 1 shows a sectional view of the semiconductor package. The wiring for interlayer connection of the substrate of the semiconductor package is a metal column 3. However, the connection to the semiconductor chip 5 by wire bonding is not performed on the circuit 11 immediately above the metal pillar 3, but that portion is covered with a solder resist 12 and
The connection is performed by a connection pad 2 on an insulating resin provided at an end portion of the device 1.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a substrate such as a substrate for a semiconductor package, which forms a smaller semiconductor package without changing the minimum wiring pitch and the number of terminals of BGA and CSP and the wiring rules of the wiring board. Provided are a substrate, a semiconductor package substrate, and a semiconductor device and a semiconductor package using the same.

[0007]

Means for Solving the Problems In the case of a substrate for wiring for interlayer connection by embedding a bump formed by etching a metal foil with a resin, a conventional substrate for CSP or BGA with interlayer connection by through-hole plating is used. In contrast, the interlayer connection is completely filled with metal. When the interlayer connection is completely filled with metal as described above, the present inventors can provide a connection pad immediately above the interlayer connection, and in the CSP or BGA, change the minimum wiring pitch. It was found that the size could be reduced by a simple change in the design of the wiring pattern without any modification, and based on this finding, the present invention was completed. That is, the present invention relates to the following substrate, semiconductor device, and semiconductor package.

(1) An insulating resin layer, a metal pillar for interlayer connection embedded in the insulating resin layer and penetrating to both sides of the insulating resin layer, and formed on at least one surface of the insulating resin layer immediately above the metal pillar. A substrate having a circuit, wherein the metal pillar and the circuit are formed by etching a metal foil, and the connection pad is provided on the circuit immediately above the metal pillar. (2) The substrate according to (1), wherein the circuit is a metal layer formed on one surface of the insulating resin layer immediately above the metal pillar.

(3) The metal pillar is made of a first metal, the circuit is made of a second metal having different etching conditions from the first metal, and the metal foil is made of a first metal layer and a second metal layer. Wherein the insulating resin layer, the circuit, and the metal pillar selectively etch the first metal layer of the metal foil to form the first metal layer on the second metal layer. Form bumps,
Forming an insulating resin layer on the surface of the second metal layer on which the first metal bumps are formed, such that the first metal bumps are exposed in the insulating resin while exposing the front end surfaces thereof; The substrate according to (2), which is formed by selectively etching a second metal layer to form a circuit.

(4) The metal pillar is composed of a first metal layer and a second metal layer having different etching conditions from the first metal layer, and the circuit has a third metal layer having different etching conditions from the second metal. A metal foil having a first metal layer, a second metal layer, and a third metal layer as a second metal layer as an intermediate layer; And a metal post selectively etches a first metal layer of the metal foil to form a first metal bump on the second metal layer, and then forms a second metal layer of the metal foil. Selectively etching to form a metal bump composed of a first metal layer and a second metal layer to be metal pillars, and then forming a first bump on a surface of the metal foil on which the metal bump is formed. A metal bump composed of a metal layer and a second metal layer is exposed so that its tip end surface is embedded in the insulating resin. Forming a layer of edge resin, then the third
(2) The substrate according to (2), which is formed by selectively etching the metal layer to form a circuit.

(5) The metal pillar is made of the first metal, and the circuit is made of a second metal layer having different etching conditions from the first metal and a third metal layer having different etching conditions from the second metal. Wherein the metal foil has a first metal layer, a second metal layer, and a third metal layer with a second metal layer as an intermediate layer, and the insulating resin layer, the circuit, and the metal pillar Selectively etching the first metal layer of the metal foil to form a first metal bump serving as a metal pillar on the second metal layer;
Forming an insulating resin layer on the surface of the second metal layer on which the first metal bump is formed, so that the first metal bump is exposed in the insulating resin while exposing the tip end surface; And then the third
The substrate according to (2), wherein the substrate is formed by selectively etching the metal layer and the second metal layer to form a circuit. (6) An insulating resin layer, a metal pillar for interlayer connection embedded in the insulating resin layer and penetrating to both sides of the insulating resin layer, and a circuit formed on at least one surface of the insulating resin layer immediately above the metal pillar. And a metal pillar and a circuit formed by etching a metal foil, wherein a connection pad is provided on a circuit immediately above the metal pillar.

(7) A connection pad and a semiconductor, comprising the substrate according to any one of (1) to (5) and a semiconductor chip mounted on the substrate, the connection pad being provided on a circuit immediately above a metal column of the substrate. A semiconductor device in which connection pads of a chip are connected by wire bonding. (8) A connection between a semiconductor chip mounted on the substrate and the semiconductor chip mounted on the substrate according to any one of (1) to (5), and a connection pad provided on a circuit immediately above a metal pillar of the substrate and the semiconductor chip. A semiconductor device in which pads for connection are connected by flip chip bonding. (9) A connection comprising the substrate according to any one of (1) to (5) and an electronic component mounted on the substrate, wherein an external connection terminal of the electronic component is provided on a circuit immediately above a metal pillar of the substrate. And a semiconductor device connected on the connection pad. (10) A semiconductor package formed by sealing the semiconductor chip mounting surface side of the semiconductor device according to (7). (11) A semiconductor package obtained by sealing the semiconductor chip mounting surface side of the semiconductor device according to (8).

[0013]

FIG. 1 is a sectional view of an embodiment of the substrate of the present invention. A plurality of metal pillars 3 for interlayer connection are embedded in the insulating resin layer 6 and penetrate to both surfaces of the insulating resin layer 6. A circuit 11 made of a metal layer is formed on one surface of the insulating resin layer 6 immediately above each metal pillar 3, and the connection pad 1 is provided on the circuit 11 directly above the metal pillar 3. That is, the circuit 11 immediately above the metal pillar 3 is used as a connection pad. An end surface of the metal column 3 opposite to the surface on which the circuit 11 is formed forms a circuit that becomes a pad for external connection (for example, a pad for solder bump) using a solder bump or the like. If necessary, Ni / Au may be provided on the end surface (circuit) of the metal pillar 3 exposed on the surface of the circuit 11 and the opposite surface of the substrate.
(Nickel / gold) plating 9, nickel / solder plating,
Plating such as copper plating and silver plating is performed. The metal pillar 3 and the circuit 11 are formed by etching a metal foil, and the interlayer connection part is completely filled with the metal composed of the metal pillar 3. As shown in FIG.
The substrate of the present invention has a plurality of interlayer connection portions made of metal pillars, but may have only one. The circuit may be provided on only one side of the interlayer insulating resin layer, or may be provided on both sides. It may be located just above the metal pillar, or may have a shape protruding from the surface of the metal pillar to the surface of the insulating resin layer.
Further, a circuit may be provided in which a connection pad is provided at a tip portion of the circuit, which is routed from immediately above an interlayer connection portion such as a metal pillar or through-hole plating. The metal foil used for forming the metal pillar by etching may be a single-layer metal foil made of one kind of metal layer, or a two- or more-layer metal foil having two or more kinds of metal layers. Is also good.

The circuit directly above the metal column may be a metal layer formed on the metal column, or may be an exposed surface of the metal column. When the circuit is an exposed surface of the metal pillar, the substrate of the present invention is, for example, using a metal foil composed of a metal layer and a carrier layer composed of an insulating resin film or an insulating resin plate, etching the metal foil on the carrier layer A metal pillar is formed, and then a tip of the metal pillar is exposed to provide an insulating resin layer so as to be embedded in the insulating resin, and then the carrier layer is peeled off. When the carrier layer is a metal layer, the carrier layer may be removed by etching after embedding the metal pillars in the insulating resin. When the circuit is a metal layer formed on a metal pillar, the circuit and the metal pillar may be formed by etching a single-layer or multi-layer metal foil, or the circuit and the metal pillar may be formed separately. May be. For example, a circuit may be formed by forming a metal pillar from one single-layer or multi-layer metal foil and embedding it in an insulating resin, and then laminating another metal foil on the insulating resin layer and etching.

When the circuit is a metal layer formed on a metal pillar, for example, the circuit and the metal pillar are
It can be formed by etching a sheet of metal foil. For example, the substrate of the present invention comprises a first metal layer,
It can be manufactured using a metal foil made of a second metal layer having different etching conditions from the first metal layer and an insulating resin. First, the first metal layer of this metal foil is
Is selectively removed by etching until the metal layer is exposed to form a first metal bump serving as a metal pillar on the second metal layer. Next, an insulating resin layer is formed on the surface of the second metal layer on which the first metal bump is formed, such that the tip end surface of the first metal bump is exposed and embedded in the insulating resin. I do. The second metal layer is then selectively etched away to form a circuit just above the metal pillar. The metals having different etching conditions mean a metal having a high erosion property and a metal having a low erosion property with respect to one kind of etching solution, or a metal having an erosion property with respect to different etching solutions. As the metal foil, a carrier layer such as a reinforcing insulating resin film or an insulating resin plate that can be peeled off after the insulating resin layer is formed may be provided on the second metal layer.

Further, as the metal foil, a first metal layer;
A first metal layer having a different etching condition from the first metal layer and a third metal layer having a different etching condition from the second metal layer on the second metal layer; May be formed by forming a metal pillar composed of the first metal layer and the second metal layer and a circuit composed of the third metal layer. In this case, first
As before, the first metal layer of the metal foil is selectively etched to form a first metal bump on the second metal layer, and then the second metal layer of the metal foil is removed. Selective etching is performed to form a metal bump serving as a metal pillar including a first metal layer and a second metal layer. Next, an insulating resin layer is formed on the surface of the metal foil on which the metal bumps are formed, so that the metal bumps are exposed in the insulating resin while exposing the tip surfaces thereof, and then the third metal layer is formed. A circuit is formed by selective etching.

Alternatively, as the metal foil, a first metal layer, a second metal layer having different etching conditions from the first metal, and a second metal layer on the second metal layer having different etching conditions. Using a different third metal layer, a metal pillar made of the first metal and a circuit composed of the second metal layer and the third metal layer may be formed. In this case, first, the first metal layer of the metal foil is selectively etched to form a first metal bump serving as a metal pillar on the second metal layer,
Next, an insulating resin layer is formed on the surface of the second metal layer on which the first metal bumps are formed, such that the first metal bumps are exposed in the insulating resin while exposing the front end surfaces. I do. Next, a circuit is formed by selectively etching the third metal layer and the second metal layer, respectively.

In any of the methods, a circuit having a connection bump at the tip thereof, which is drawn from immediately above the metal pillar, may be further formed. Further, before forming the insulating resin layer, it is preferable to perform a surface treatment on the surface of the metal foil on which the metal bumps are formed so as to improve the adhesion to the insulating resin. Examples of the surface treatment include a chemical phosphorus-based treatment, a chemical phosphoric acid-based treatment, a chemical formic acid-based treatment, and electrolytic application of metal particles.

As the first metal, one selected from copper, copper alloy, iron / nickel alloy, and the like can be used.
As the second metal, when the first metal is copper or a copper alloy, nickel, a nickel alloy, titanium, chromium,
Tin, zinc, gold, etc. can be used, and the first metal is iron.
In the case of a nickel alloy, titanium, chromium, tin, or the like can be used. As the third metal, a material selected from copper, a copper alloy, an iron / nickel alloy, or the like can be used.

The thickness of the first metal layer forming the metal pillar is preferably 12 to 100 μm,
If it exceeds m, the etching accuracy when forming a metal bump is low, and it may be difficult to form a fine pattern. If it is less than 12 μm, the strength of the metal column becomes insufficient or the insulating resin There is a possibility that the insulation property may be reduced. More preferably, it is 18 to 70 μm. The thickness of the second metal layer is preferably 0.05 to 50 μm, and if it exceeds 50 μm, the etching accuracy at the time of circuit formation may be low, and it may be difficult to form a fine pattern. If the thickness is less than 0.05 μm, the third metal layer may be eroded due to pits or chips generated in the second metal layer when the first metal layer is etched. More preferably, it is 0.1 to 35 μm. Third
The thickness of the metal layer is preferably 1 to 50 μm, and if it exceeds 50 μm, the etching accuracy may be reduced at the time of forming a circuit, and it may be difficult to form a fine pattern. Then, when the first metal is etched, pits or chips generated in the second metal layer may erode the third metal layer. More preferably, it is 5 to 12 μm.

For the carrier layer, an insulating resin plate, an insulating film, or a metal foil can be used. As the insulating resin plate, for example, epoxy resin, polyimide resin,
A material selected from a silicone resin, a phenol resin and the like can be used. As the insulating film, a film selected from a polyimide resin, a polyethylene phthalate resin, a polyphenylene sulfide film, or the like can be used. As metal foil, copper foil, copper alloy foil, iron,
A material selected from a nickel alloy or the like can be used. Examples of the insulating resin material used for the insulating resin layer include thermosetting epoxy resin, polyimide resin, silicone resin, polyamide imide resin, polyphenylene sulfide resin, photosensitive polyimide resin, acrylic epoxy resin, ethylene, propylene, styrene, and butadiene. And the like, a thermoplastic elastomer, a liquid crystal polymer and the like.
Normally, the thickness of the insulating resin layer is the same as the height of a metal column formed by etching the first metal layer. The shape of the metal column is not particularly limited as long as it is a solid metal column.
Cylinder with a radius of 10 to 750 µm, width of short side 20 µm
These are the above squares and the like.

The substrate of the present invention may have only one insulating resin layer, or may have a multi-layer wiring board having a plurality of conductive circuit layers laminated below the insulating resin layer via an insulating layer. It may be. The substrate of the present invention can be used in the manufacture of various semiconductor devices, for example, as an interposer used for a semiconductor package, or as a wiring board such as a motherboard on which electronic components of the semiconductor package are mounted.

For example, a semiconductor chip is mounted on the substrate of the present invention, and the connection pads provided on the circuit and the connection pads of the semiconductor chip are electrically connected to the connection pads provided on the circuit just above the metal pillars of the substrate. The semiconductor device of the invention can be obtained. When the connection is made by wire bonding, for example, after a semiconductor chip is fixed on a substrate with a die bonding material or the like and mounted, a connection pad provided on a circuit directly above a metal pillar of the substrate and a connection pad of the semiconductor chip Are bonded with a conductor wire such as a gold wire, an aluminum wire, and a copper wire. When connection is made by flip chip bonding, gold, solder, lead, copper, tin, silver bumps formed on the connection pads of the semiconductor chip, and their respective alloys, conductive paste mixed with metal and resin, A metal bump such as an anisotropic conductive film or a bump made by coating an inorganic or organic ball with a metal is directly connected to a connection pad provided on a circuit just above a metal pillar of a substrate.

The semiconductor package of the present invention is obtained by sealing the semiconductor chip mounting surface side of the semiconductor device with a sealing material. The sealing can be performed by molding using an insulating resin, transfer molding, potting, casting, resin sealing by screen printing, or the like. As an insulating resin used for resin sealing, an epoxy resin, a silicone resin, a phenol resin, an epoxy-modified phenol resin, or the like can be used.

FIG. 4 is a sectional view showing an example of the semiconductor package of the present invention. The metal pillar 3 is embedded in the insulating resin layer 6 of the substrate and penetrates to both surfaces of the insulating resin layer 6. A circuit 11 made of a metal layer is formed directly on the metal pillar 3 and on one surface of the insulating resin layer 6. The surface of the metal column 3 exposed on the lower surface side of the insulating resin layer 6 and the surface of the circuit 11 have Ni /
Au plating 9 is applied. The connection pads (not shown) of the semiconductor chip 5 mounted on the substrate and the connection pads 1 provided on the circuit immediately above the metal pillar 3 are wire-bonded with gold wires. The surface of the substrate on which the semiconductor chip 5 is mounted is sealed with a sealing material 8.

As shown in FIG. 4, if connection pads are provided in the circuit immediately above the metal pillars, it is not necessary to provide pads for connection between the wiring and the chip that are routed avoiding the interlayer connection portion, so that the package is not required. The size can be reduced. Another advantage is that the pitch of the other wirings can be increased by the area of the unnecessary wiring for wiring without reducing the size. Further, it can be estimated that the surface area of the resin on the substrate increases, and that the adhesiveness to the encapsulating material, the underfill material, and the solder resist is improved. As another advantage, when a wire bonding method or a flip chip connection method using ultrasonic waves is used as a connection method, a circuit immediately above a metal pillar formed by etching is filled with metal under the circuit. Therefore, the lower part of the other circuit is harder than the resin part and the ultrasonic wave is easily transmitted. Therefore, the result that the bonding property is good is obtained.

With regard to miniaturization, the total area is reduced by the number of terminals bonded to the connection pads on the circuit immediately above the metal pillars, and the wiring at the time of design can have a margin. The method of implementing the present invention is very simple, and pads may be provided on a circuit immediately above a bump when designing a wiring pattern. Further, the present invention provides a semiconductor device using the substrate of the present invention as a wiring board such as a motherboard.
This semiconductor device has a substrate and an electronic component mounted on the substrate, and an external connection terminal of the electronic component is provided on a connection pad provided on a circuit immediately above a metal pillar of the substrate, and on the connection pad. It is connected. Examples of the electronic component include a semiconductor package and a semiconductor chip. The same advantages as described above can be obtained when connecting to such electronic components as a semiconductor package and a semiconductor chip. Also in this semiconductor device, the electronic component mounting surface side may be sealed.

[0028]

EXAMPLES Hereinafter, the present invention will be described more specifically with reference to Examples of the present invention and Comparative Examples thereof, but the present invention is not limited to these Examples. Example 1 A 0.5 mm pitch semiconductor package substrate having a cross section shown in FIG. 1 was produced by the following method. 70 μm of a three-layer metal foil (manufactured by Nihon Denki Co., Ltd.) consisting of a copper layer having a thickness of 70 μm, a nickel layer having a thickness of 0.2 μm, and a copper layer having a thickness of 10 μm.
The copper layer is patterned by using a photo dry film H-K350 (manufactured by Hitachi Chemical Co., Ltd.), and an A process solution manufactured by Meltex Co. (ammonia copper complex salt: 20 to 30% by weight, ammonium chloride: 10 to 20% by weight) % And 1 to 10% by weight of ammonia). Copper was selectively etched with an alkaline etching solution composed of a stock solution to form 200 copper bumps of φ250 μm. In addition, the nickel layer is selectively etched away, leaving just above the copper bumps,
A metal column 3 composed of a copper layer and a nickel layer was formed. An etching solution composed of a stock solution of Melstrip N-950 (containing 8% by weight of sulfuric acid, 5% by weight of nitric acid, and 3.5% by weight of hydrogen peroxide) manufactured by Meltex Corporation was used for etching the nickel layer. Next, on the surface of the three-layer metal foil on which the metal pillars are formed, a chemical phosphorus-based treatment (a treatment solution manufactured by Ebara Densan Co., Ltd., an NBD II treatment solution (7.5 wt. %, Phosphoric acid 3.8% by weight and hydrogen peroxide 4.
(A treatment by an NBD II treatment system using 0% by weight) was performed under the conditions of a line speed of 1.75 m / min and a spray pressure of 9.8 × 10 ⁴ Pa (1.0 kgf / cm ² ). An insulating resin KS6600 (manufactured by Hitachi Chemical Co., Ltd.), which is a liquid silicon-modified polyamide-imide resin 6, is printed on a surface of the metal foil on which the metal pillars are formed by a printing machine VE.
-500 (manufactured by Toray Engineering Co., Ltd.) was printed and the metal pillars were buried.
The insulating resin layer 6 was formed by performing three-step curing at 20 ° C. for 20 minutes and polishing until the end face of the metal pillar embedded with commercial abrasive paper appeared. Next, a copper layer having a thickness of 10 μm of the metal foil was coated with an A process solution manufactured by Meltex Co. (ammonia copper complex salt 20 to 30% by weight, ammonium chloride 10 to 20%).
(Containing 1% to 10% by weight of ammonia and 1 to 10% by weight of ammonia) by selective etching with an alkaline etching solution composed of a stock solution to form a copper circuit 11 of φ300 μm on the metal column 3.
Then, the circuit surface and electrolytic nickel / gold plating (Ni /
Au plating 9) (made by Daiwa Electric Industry Co., Ltd.)
A 0.5 mm pitch semiconductor package substrate having a sectional structure as shown in FIG. 3 was manufactured. In this substrate, all the 200 connection pads for wire bonding between the semiconductor chip 5 and the substrate were used as the circuits 11 on the metal columns 3.
Solder bumps 10 are formed on the lower end surfaces of the metal columns 3 via Ni / Au plating 9. FIG. 5A shows this FIG.
2 is a partial plan view showing a wiring pattern of a semiconductor device manufactured using the substrate shown in FIG. Size 8.5 on this substrate
A semiconductor chip 5 having a size of 8.5 mm × 8.5 mm and a thickness of 0.3 mm is mounted, and a connection pad 1 provided on a circuit 11 immediately above a metal pillar 3 and a connection pad (not shown) of the semiconductor chip are
Connect with gold wire 7. At this time, for comparison, similarly to the conventional semiconductor package substrate, a circuit was formed that was routed from immediately above all of the 200 metal columns, and a substrate provided with connection pads on the circuit on the insulating resin at the tip was also used. Got ready. FIG. 5B is a partial plan view of a wiring pattern of a semiconductor device manufactured using this substrate. The connection pads (not shown) of the semiconductor chip 5 mounted on the substrate are connected to the connection pads 2 provided on the tip of the insulating resin of the circuit 13 routed from directly above all the metal pillars 3 by wire bonding. Is done. As a result, as shown in FIG. 5, the substrate size was 15 × 15 mm in the conventional circuit design, but was 13 × 13 mm when all the 200 connection pads were directly above the metal pillars. This is 25%
This means that it has been downsized. Furthermore, wire bonder HW
2100 (manufactured by Kyushu Matsushita Electric Co., Ltd.) has a wire bonding defect rate of 0.009% at a portion bonded directly above a metal pillar formed by etching, and a connection formed on a circuit on insulating resin by circuit routing. Pad 0.
Fewer than 03%.

Example 2 The number of metal pillars for interlayer connection was increased to 384, of which
A connection pad was provided on the circuit immediately above the 160 metal pillars, and the circuit was routed from the remaining 224 metal pillars, and connection pads were provided at the tips, as in Example 1.
A semiconductor package substrate was manufactured in the same manner as in Example 1 using the layered metal foil and the liquid resin. FIG. 6A is a partial plan view of a wiring pattern of a semiconductor device manufactured by mounting a semiconductor chip on this substrate and performing wire bonding. Further, for comparison, a substrate was manufactured in which all connection pads were formed on a circuit on an insulating resin by circuit pattern routing. FIG. 6B is a partial plan view of a wiring pattern of a semiconductor device manufactured by mounting a semiconductor chip on this comparative substrate and performing wire bonding. As a result, the size of the semiconductor package substrate 120 wire-bonded immediately above the metal pillar for interlayer connection is 14 × 14 mm for the comparison substrate, whereas the size of the substrate for this example is 12 × 12 mm. Was completed.

[0030]

As described above, a metal pillar for interlayer connection is formed by embedding a bump formed by etching a metal foil with an insulating resin, and a connection pad is provided in a circuit immediately above the substrate to form a substrate. This makes it possible to provide a small semiconductor package substrate and a wiring board by simply changing the wiring pattern.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of one embodiment of a substrate according to the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor package using a semiconductor package substrate that is interlayer-connected by through-hole plating.

FIG. 3 is a cross-sectional view of a semiconductor package using a conventional semiconductor package substrate.

FIG. 4 is a cross-sectional view illustrating one embodiment of a semiconductor package using the substrate of the present invention.

FIG. 5 is a partial plan view of a wiring pattern of a semiconductor device manufactured using the substrate manufactured in Example 1. (A) shows a wiring pattern when the substrate of the present invention is used, and (b) shows a wiring pattern when a conventional substrate is used.

FIG. 6 is a partial plan view of a wiring pattern of a semiconductor device manufactured using the substrate manufactured in Example 2. (A) shows a wiring pattern when the substrate of the present invention is used, and (b) shows a wiring pattern when a conventional substrate is used.

[Explanation of symbols]

1 Connection pads provided on a circuit directly above a metal pillar 2 Connection pads provided on circuits on insulating resin 3 metal pillar (etched bump connection) 4 Through-hole plating connection 5 Semiconductor chip 6 Insulating resin layer 7 Gold wire 8 Sealing material 9 Ni / Au plating 10 Solder bump 11 circuits 12 Solder resist 13 circuits

Continuation of front page    (72) Inventor Kazuhisa Suzuki             Hitachi Chemical, 1500 Ogawa, Shimodate City, Ibaraki Prefecture             Industrial Co., Ltd. (72) Inventor Mitsuo Kikuchi             Hitachi Chemical, 1500 Ogawa, Shimodate City, Ibaraki Prefecture             Industrial Co., Ltd.

Claims (11)

[Claims] 1. An insulating resin layer, a metal pillar for interlayer connection embedded in the insulating resin layer and penetrating to both sides of the insulating resin layer, and a circuit formed on at least one surface of the insulating resin layer immediately above the metal pillar. Wherein the metal pillar is formed by etching a metal foil, and the connection pad is provided on a circuit immediately above the metal pillar. 2. The substrate according to claim 1, wherein the circuit is a metal layer formed on one surface of the insulating resin layer immediately above the metal pillar. 3. The metal pillar is made of a first metal, the circuit is made of a second metal having different etching conditions from the first metal, and the metal foil is made of a first metal layer and a second metal layer. Wherein the insulating resin layer, the circuit, and the metal pillar selectively etch the first metal layer of the metal foil and form a first metal bump on the second metal layer as a metal pillar. Is formed on the surface of the second metal layer on which the first metal bumps are formed, such that the first metal bumps are exposed in the distal end surface and embedded in the insulating resin. 3. The substrate according to claim 2, wherein the substrate is formed by forming a circuit, and then selectively etching the second metal layer to form a circuit. 4. The metal pillar comprises a first metal layer, a second metal layer having different etching conditions from the first metal layer,
The circuit is composed of a third metal layer having different etching conditions from the second metal, and the metal foil is formed of the first metal layer, the second metal layer, and the third metal layer. As an intermediate layer, and the insulating resin layer, the circuit, and the metal pillar selectively etch the first metal layer of the metal foil to form a first metal bump on the second metal layer. And then selectively etching the second metal layer of the metal foil to form a metal bump consisting of a first metal layer and a second metal layer to be metal pillars, On the surface on which the metal bumps are formed, a metal bump composed of a first metal layer and a second metal layer is exposed so that its tip end surface is exposed and embedded in the insulating resin. Formed by forming and then selectively etching a third metal layer to form a circuit Substrate of a second aspect. 5. The circuit according to claim 1, wherein the metal pillar is made of a first metal, and the circuit is made of a second metal layer having different etching conditions from the first metal and a third metal layer having different etching conditions from the second metal. The metal foil has a first metal layer, a second metal layer, and a third metal layer as a second metal layer as an intermediate layer, and the insulating resin layer, the circuit, and the metal pillars are: The first metal layer of the metal foil is selectively etched to form a first metal bump serving as a metal pillar on the second metal layer,
On the surface of the first metal layer on which the first metal bumps are formed,
An insulating resin layer is formed so that the first metal bumps are exposed in the insulating resin while exposing the tip surfaces, and then the third metal layer and the second metal layer are selectively etched, respectively. 3. The substrate according to claim 2, wherein the substrate is formed by forming a circuit. 6. An insulating resin layer, a metal pillar for interlayer connection embedded in the insulating resin layer and penetrating to both sides of the insulating resin layer, and a circuit formed on at least one surface of the insulating resin layer immediately above the metal pillar. A semiconductor package substrate comprising: a metal pillar formed by etching a metal foil; and a connection pad provided on a circuit immediately above the metal pillar. 7. A connection between a semiconductor chip mounted on the substrate and the semiconductor chip mounted on the substrate, the connection pad being provided on a circuit immediately above a metal pillar of the substrate and a connection of the semiconductor chip. A semiconductor device in which pads are connected by wire bonding. 8. A connection between a semiconductor chip mounted on the substrate and a connection pad provided on a circuit immediately above a metal pillar of the substrate and a connection between the semiconductor chip and the semiconductor chip mounted on the substrate. A semiconductor device in which pads are connected by flip chip bonding. 9. A connection comprising the substrate according to claim 1 and an electronic component mounted on the substrate, wherein an external connection terminal of the electronic component is provided on a circuit immediately above a metal pillar of the substrate. And a semiconductor device connected on the connection pad. 10. A semiconductor package formed by sealing the semiconductor chip mounting surface side of the semiconductor device according to claim 7. 11. A semiconductor package formed by sealing the semiconductor chip mounting surface side of the semiconductor device according to claim 8.