TW201318122A - 封裝基板、封裝基板製程、半導體元件之封裝結構及其製程 - Google Patents
封裝基板、封裝基板製程、半導體元件之封裝結構及其製程 Download PDFInfo
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- TW201318122A TW201318122A TW101138782A TW101138782A TW201318122A TW 201318122 A TW201318122 A TW 201318122A TW 101138782 A TW101138782 A TW 101138782A TW 101138782 A TW101138782 A TW 101138782A TW 201318122 A TW201318122 A TW 201318122A
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- Prior art keywords
- layer
- conductive
- conductive layer
- dielectric layer
- substrate
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- 238000004519 manufacturing process Methods 0.000 title 2
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
一種封裝基板,包括一介電層、一第一導電層、一第二導電層以及一接合墊。介電層具有一上表面以及一下表面。第一導電層內埋於介電層中,並顯露一第一表面於上表面。第一表面切齊上表面。第二導電層內埋於介電層中與第一導電層接觸,並顯露一第二表面於下表面。第二表面切齊於下表面。接合墊部分地或全部地內埋於第一導電層與介電層中,以使接合墊之周圍同時被第一導電層與介電層之側壁限制於凹穴內。
Description
本發明是有關於一種封裝結構及製程,且特別是有關於一種封裝基板、封裝基板製程、半導體元件之封裝結構及其製程。
隨著電子產品的普遍應用於日常生活中,半導體元件需求量與日遽增。由於半導體元件走向輕薄化之設計,當半導體元件尺寸縮小時,I/O腳數不減反增,使得線路間距與線路寬度縮小化,並朝微小間距(fine pitch)的設計發展,例如50μm間距,甚至35μm以下間距。
然而,在半導體元件覆晶組裝於封裝基板之過程中,常會因焊錫高溫迴焊,而使兩相鄰之導電凸塊間發生橋接(bridging)短路的現象。此外,焊錫因無防銲層覆蓋在線路層上,以限制其流動,使得焊錫高溫迴焊時,容易沿著線路層向外擴散(overspreading),造成覆晶後的半導體元件與封裝基板間的高度減少,且因高度減少而難以將底膠層填入於半導體元件與封裝基板之間,造成封裝的可靠度下降等問題。
本發明係有關於一種封裝基板、封裝基板製程、半導體元件之封裝結構及其製程,可在符合微小間距的設計下,提高半導體元件的封裝可靠度。
根據本發明之一方面,提出一種封裝基板,包括一介電層、一第一導電層以及一第二導電層。介電層具有一上表面以及一下表面。第一導電層內埋於介電層中,並顯露一第一表面於上表面。第一表面切齊上表面或內凹於上表面。第二導電層內埋於介電層中與第一導電層接觸,並顯露一第二表面於下表面。第二表面切齊於下表面或內凹於下表面。
根據本發明之另一方面,提出一種封裝基板製程,包括下列步驟。提供一導電基板。形成一第一光阻層於導電基板上,第一光阻層經圖案化而形成多個第一開口,以顯露出部分導電基板。形成一第一導電層於此些第一開口中。形成一第二光阻層於第一光阻層以及第一導電層上,第二光阻層經圖案化而形成多個第二開口,以顯露出部分第一導電層。形成一第二導電層於此些第二開口中,並與第一導電層接觸。移除第一及第二光阻層。形成一介電層於導電基板上,介電層覆蓋第一導電層、第二導電層以及部分導電基板。移除部分介電層,以顯露出第二導電層之一表面於介電層之下表面,第二導電層之表面切齊於介電層之下表面。形成一第三光阻層於導電基板以及介電層上,第三光阻層經圖案化而形成一第三開口,以顯露出部分導電基板。移除部分導電基板,以形成一第四開口,並顯露第一導電層之一表面與介電層之上表面於第四開口中,第一導電層之表面切齊於介電層之上表面。移除第三光阻層。形成一第四光阻層於導電基板、介電層、第一導電層以及第二導電層上,第四光阻層經圖案化而形成一第
五開口,以顯露出第一導電層之部分表面。形成一接合墊於第五開口中。移除第四光阻層。此外,更可形成一焊接層於第二導電層上,焊接層覆蓋第二導電層之表面。
根據本發明之另一方面,提出一種半導體元件之封裝結構,包括一封裝基板、一半導體元件、一底膠層以及一封膠層。封裝基板包括一介電層、一第一導電層以及一第二導電層。介電層具有一上表面以及一下表面。第一導電層內埋於介電層中,並顯露一第一表面於上表面。第一表面切齊上表面或內凹於上表面。第二導電層內埋於介電層中與第一導電層接觸,並顯露一第二表面於下表面。第二表面切齊於下表面或內凹於下表面。半導體元件配置於封裝基板上,半導體元件具有一導電凸塊。導電凸塊支撐於半導體元件與封裝基板之間。
根據本發明之另一方面,提出一種半導體元件之封裝製程,包括下列步驟。提供一導電基板。形成一第一光阻層於導電基板上,第一光阻層經圖案化而形成多個第一開口,以顯露出部分導電基板。形成一第一導電層於此些第一開口中。形成一第二光阻層於第一光阻層以及第一導電層上,第二光阻層經圖案化而形成多個第二開口,以顯露出部分第一導電層。形成一第二導電層於此些第二開口中,並與第一導電層接觸。移除第一及第二光阻層。形成一介電層於導電基板上,介電層覆蓋第一導電層、第二導電層以及部分導電基板。移除部分介電層,以顯露出第二導電層之一表面於介電層之下表面,第二導電層之表面切齊於介電層之下表面。形成一第三光阻層於導電基板、介
電層、第一導電層以及第二導電層上,第三光阻層經圖案化而形成一第三開口,以顯露出部分導電基板。移除部分導電基板,以形成一第四開口,並顯露第一導電層之一表面與介電層之上表面於第四開口中。第一導電層之表面切齊於介電層之上表面。移除第三光阻層。形成一第四光阻層於導電基板、介電層、第一導電層以及第二導電層上,第四光阻層經圖案化而形成一第五開口,以顯露出第一導電層之部分表面。形成一接合墊於第五開口中。移除第四光阻層。形成一焊接層於第二導電層上,焊接層覆蓋第二導電層之表面,以形成由介電層、第一導電層、第二導電層以及接合墊所組成之一封裝基板。配置一半導體元件於封裝基板上,半導體元件具有一導電凸塊,導電凸塊連接接合墊,且導電凸塊支撐於半導體元件與封裝基板之間。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下:
本實施例之封裝基板、封裝基板製程、半導體元件之封裝結構及其製程,可應用在高I/O腳數之封裝結構中,且無須在防銲層覆蓋封裝基板之表面來防止銲錫橋接短路的情況下,導線之間仍能維持在微小間距(Fine pitch)的精度下。較佳地,銲錫可被限制於預定的凹穴內而無法流動、封裝基板內連接線結構的高度可藉由上、下堆疊之導體層而縮短、封裝基板的強度可藉由環狀補強結構之環繞而提高,避免翹曲或變形,進而改善半導體元件的封裝
可靠度。
以下係提出各種實施例進行詳細說明,實施例僅用以作為範例說明,並非用以限縮本發明欲保護之範圍。
第1A及1B圖分別繪示依照本發明一實施例之封裝基板的示意圖及沿著I-I線的剖面示意圖。第2A及2B圖分別繪示依照本發明一實施例之封裝基板的示意圖及沿著I-I線的剖面示意圖。第3A及3B圖分別繪示依照本發明一實施例之封裝基板的示意圖及沿著I-I線的剖面示意圖。
請參照第1A及1B圖,封裝基板100包括一介電層110、一第一導電層120、一第二導電層130、一接合墊140以及一焊接層150。介電層110具有一上表面112以及一下表面114。第一導電層120內埋於介電層110中,並顯露一第一表面122於上表面112。第二導電層130內埋於介電層110中,並顯露一第二表面132於下表面114。接合墊140配置於由第一導電層120之側壁121與介電層110之側壁111(參見第1B圖)所定義之一凹穴123中。當第一表面122切齊上表面112時,接合墊140部分地(或全部地)內埋於第一導電層120與介電層110中,以使接合墊140之周圍同時被第一導電層120之側壁121與介電層110之側壁111(參見第1B圖)限制於凹穴123內而無法流動,因此可避免在高溫迴焊下接合墊140(例如焊錫)發生橋接短路的現象。接合墊140之材質例如選自於錫(Sn)、銅(Cu)、銀(Ag)、鎳(Ni)、鈀(Pd)、金(Au)或其組合,較佳為可迴焊(reflowable)之焊接材料。
在第1A圖中,第一表面122切齊介電層110之上表面112,第二表面132切齊於介電層110之下表面114。在第2A圖中,第一表面122內凹於介電層110之上表面112,第二表面132內凹於介電層110之下表面114。當第一表面122內凹於介電層110之上表面112時,接合墊140部分地(或全部地)內埋於介電層110之凹穴113中,以使接合墊140之相對兩側單獨被介電層110的側壁111(參見第2B圖)限制於凹穴113內而無法流動,因此可避免在高溫迴焊下接合墊140(例如焊錫)發生橋接短路的現象。此外,當第二表面132內凹於下表面114時,可固定焊球190(參見第4A圖)於各個焊接層150上,以使植球的品質更加穩定。
接著,請參照第3A及3B圖,在確保不會發生焊錫橋接短路的情況下,接合墊140可直接形成在第一導電層120的第一表面122上,第一導電層之材質可為抗腐蝕之鎳銅合金、鎳鉻合金等,而接合墊140之材質例如選自於錫(Sn)、銅(Cu)、銀(Ag)、鎳(Ni)、鈀(Pd)、金(Au)或其組合,較佳為不需迴焊之凸塊,例如為結線凸塊(stud bump)。
請參照第4A~4C圖,其分別繪示依照本發明一實施例之半導體元件之封裝結構的示意圖。在第4A~4C圖中,採用的封裝基板可為第1A、2A及3A圖中任一種封裝基板100,其詳細內容已揭示如上,在此不再贅述。在第4A~4C圖中,半導體元件160配置於封裝基板100上。半導體元件160具有多個導電凸塊162,圖中僅繪示三個導電凸
塊162,一個導電凸塊162對應連接一個接合墊140,且導電凸塊162支撐於半導體元件160與封裝基板100之間。相對於接合墊140而言,導電凸塊162具有較高的熔點,因此當接合墊140受熱而融化時,未融化的導電凸塊162仍有足夠的高度支撐半導體元件160,以維持適當的間距於半導體元件160與封裝基板100之間。導電凸塊162例如為電鍍之銅柱,其具有一預定高度,而接合墊140例如為焊錫,當導電凸塊162與接合墊140連接時,如第1A及2A圖所示,接合墊140較佳為被限制於凹穴123內而無法流動,因此可避免在高溫迴焊下接合墊140發生橋接短路的現象。此外,導電凸塊162更可包括銅柱和焊料點設置於銅柱上,其焊料點部分粘接於接合墊140。
此外,底膠層170包覆導電凸塊162之周圍,底膠層170較佳為熱固化型環氧樹酯,具有流動快及快速固化的優點,可於迴焊過程中同時固化,以使接合墊140不會受到底膠層170流動的影響,並能維持導電凸塊162與接合墊140之間的導電性。另外,封膠層180包覆半導體元件160以及底膠層170之周圍,封膠層180較佳為熱固化型環氧樹酯,以保護半導體元件160。再者,多個焊球190形成於焊接層150上,圖中僅繪示三個焊球190,一個焊球190對應連接一個焊接層150,焊球190之材質可為無鉛錫膏或有鉛錫膏。
在第4B圖中,封膠層180包覆半導體元件160以及底膠層170之周圍,並顯露出半導體元件160之上表面112。封膠層180較佳以轉注成型(transfer molding)
的方式形成,並經高溫烘烤而固化成型。
在第4C圖中,導電凸塊162例如為結線凸塊,其材質較佳為銅或金,導電凸塊162之尖端可穿過流動性較低的底膠層170,並與底膠層170下方的接合墊140電性連接。底膠層170包覆於導電凸塊162之周圍,其材質可為熱固化型不導電膠。
另一實施例中,封裝基板100上可以不設置接合墊160。導電凸塊162包括銅柱和焊料點設置於銅柱上,其焊料點部分直接與第一導電層120粘接,從而使半導體元件160形成於半導體基板上。導電凸塊162與第一導電層120連接時,導電凸塊162較佳為被限制於該介電層110的側壁內而無法流動,由於第一導電層120之表面內凹於介電層110的上表面,從而具有限制導電凸塊162位移的作用,使得導電凸塊162準確地定位於第一導電層120上。
於以上幾種實施例,由於第一導電層120之表面內凹於介電層110的上表面之設計,增長了相鄰二第一導電層沿著封裝體之外表面的路徑長度,如此可避免電移(Electro migration)發生時,相鄰二第一導電層短路的風險。
請參照第5A~5Y圖,其中第5A~5S圖繪示依照本發明一實施例之封裝基板製程的示意圖,而第5T~5Y圖繪示依照本發明一實施例之半導體元件之封裝製程的示意圖。首先,請參照第5A~5D圖,提供一導電基板50,並形成一第一光阻層52於導電基板50上,第一光阻層52經圖案化而形成多個第一開口54,以顯露出部分導電基板
50。之後,形成一第一導電層120於此些第一開口54中。在第5A圖中,導電基板50為金屬基板,較佳為銅板或鍍有銅層之鋼板。在第5B及5C圖中,第一光阻層52例如以旋轉塗佈的方式形成在導電基板50上,並經過烘烤、曝光、顯影等步驟以圖案化第一光阻層52,以使第一光阻層52具有多個第一開口54。在5D圖中,第一導電層120例如以電鍍的方式形成在第一開口54中,其材質較佳為銅、鎳、金或其組合。
接著,請參照第5E~5H圖,形成一第二光阻層56於第一光阻層52以及第一導電層120上,第二光阻層56經圖案化而形成多個第二開口58,以顯露出部分第一導電層120。形成一第二導電層130於此些第二開口58中。之後,移除第一光阻層52及第二光阻層56。在第5E及5F圖中,第二光阻層56例如以旋轉塗佈的方式形成在導電基板50上,並經過烘烤、曝光、顯影等步驟以圖案化第二光阻層56,以使第二光阻層56具有多個第二開口58。在第5G圖中,第二導電層130例如以電鍍的方式形成在第二開口58中,其材質較佳為銅、鎳、金或其組合。第二導電層130與第一導電層120直接接觸而上、下堆疊,以做為內連接線結構。在第5H圖中,第一光阻層52與第二光阻層56以去光阻劑(例如丙酮)移除,而顯露出相互堆疊之第一導電層120以及第二導電層130。雖然,本實施例僅繪示第一導電層120與第二導電層130,但亦可形成二層以上的導電層,對此,本發明不加以限制。
接著,請參照第5I~5L圖,形成一介電層110於導
電基板50上,介電層110覆蓋第一導電層120、第二導電層130以及部分導電基板50。移除部分介電層110,以顯露出第二導電層130之一表面(即第二表面132)於介電層110之下表面114。第二導電層130之第二表面132切齊於介電層110之下表面114。之後,形成一第三光阻層60於導電基板50以及介電層110上,第三光阻層60經圖案化而形成一第三開口62,以顯露出部分導電基板50。在第5I圖中,介電層110例如以轉注成型的方式形成在導電基板50上,亦即以液態狀的介電層110注入模穴中,並經烘烤而固化成型。但介電層110亦可以模壓成型(compression molding)的方式形成在導電基板50上,並使半固化態的介電層110在高溫下完全固化而成型。在第5J圖中,部分介電層110例如以機械研磨(grinding)及/或拋光(buffing)的方式移除,以使第二導電層130之第二表面132顯露於介電層110外,並與介電層110之下表面114切齊。此外,第二導電層130之第二表面132更可經由蝕刻而內凹於介電層110之下表面114,如第2A圖所示,以方便植球。在第5K及5L圖中,第三光阻層60例如以擠壓式(slit die)塗佈法或浸漬塗佈法(dip coating)形成在導電基板50上,並經由烘烤、曝光、顯影等步驟以圖案化第三光阻層60,以使第三光阻層60具有一第三開口62。
接著,請參照第5M~5P圖,移除部分導電基板50,以形成一第四開口51,並顯露第一導電層120之一表面與介電層110之上表面112於第四開口51中。第一導電層
120之表面切齊於介電層110之上表面112。移除第三光阻層60。之後,形成一第四光阻層64於導電基板50、介電層110、第一導電層120以及第二導電層130上,第四光阻層64經圖案化而形成一第五開口66,以顯露出第一導電層120之部分表面。在第5M圖中,導電基板50例如以濕式蝕刻的方式形成第四開口51,圖中僅繪示一個第四開口51,而未被蝕刻的部分導電基板50則形成一環狀補強結構53,連接於介電層110之周圍。環狀補強結構53環繞於介電層110的上表面112,可補強整體基板的強度,以避免翹曲或變形。此外,第一導電層120之表面更可全面蝕刻而內凹於介電層110的上表面112,如第2A圖所示。在第5N圖中,第三光阻層60以去光阻劑(例如丙酮)移除,而顯露出相互堆疊之第一導電層120以及第二導電層130。在第50及5P圖中,第四光阻層64例如以擠壓式塗佈法或浸漬塗佈法形成,並經由烘烤、曝光、顯影等步驟以圖案化第四光阻層64,以使第四光阻層64具有多個第五開口66。此外,第一導電層120顯露於第五開口66中的部分表面更可經由蝕刻而形成一凹穴123,如第1A圖所示。
接著,請參照第5Q~5S圖,形成一接合墊140於第五開口66中。移除第四光阻層64。之後,形成一焊接層150於第二導電層130上,焊接層150覆蓋第二導電層130之表面。在第5Q圖中,接合墊140以電鍍的方式形成在第五開口66中,其材質例如選自於錫(Sn)、銅(Cu)、銀(Ag)、鎳(Ni)、鈀(Pd)、金(Au)或其組合,較佳
為可迴焊(reflowable)之焊接材料。在第5R圖中,第四光阻層64以去光阻劑(例如丙酮)移除,而顯露出相互堆疊之第一導電層120以及第二導電層130。在第5S圖中,焊接層150例如以無電電鍍(electroless plating)或浸漬(immersion)的方式形成在第二導電層130上,其材質例如選自於錫(Sn)、銅(Cu)、銀(Ag)、鎳(Ni)、鈀(Pd)、金(Au)或其組合,或以有機保焊劑(Organic Solderability Preservatives,OSP)取代。以上為封裝基板100製程的詳細說明,接著對半導體元件160之封裝製程進行詳細說明。
請參照第5T~5W圖,配置一半導體元件160於封裝基板100上。半導體元件160具有一導電凸塊162,導電凸塊162連接接合墊140,且導電凸塊162支撐於半導體元件160與封裝基板100之間。形成一底膠層170以包覆導電凸塊162之周圍。形成一封膠層180以包覆半導體元件160以及底膠層170之周圍。在第5T圖中,半導體元件160為積體電路元件,其主動表面上配置有多個導電凸塊162,圖中繪示三個導電凸塊162,一個導電凸塊162對應一個接合墊140。相對於接合墊140而言,導電凸塊162具有較高的熔點,導電凸塊162例如為銅柱、銅凸塊、金凸塊或結線凸塊,其具有一預定高度,而接合墊140例如為可迴焊之焊接材料。在第5U及5V圖中,先形成底膠層170於封裝基板100上,再將半導體元件160之導電凸塊162穿過流動性較低的底膠層170,並與底膠層170下方的接合墊140電性連接,以使底膠層170包覆在導電凸
塊162之周圍。當然,底膠層170除了採用上述方式形成,亦可先將半導體元件160配置於封裝基板100上,再以流動性較佳的底膠層170填入於半導體元件160與封裝基板100之間的間隙中,以包覆在導電凸塊162之周圍。在第5V圖中,當導電凸塊162與接合墊140連接時,如第1A及2A圖所示,接合墊140較佳為被限制於凹穴123內而無法流動,因此可避免在高溫迴焊下接合墊140發生橋接短路的現象。在第5W圖中,封膠層180較佳以轉注成型(transfer molding)的方式形成,並經高溫烘烤而固化成型。此外,封膠層180亦可顯露半導體元件160之上表面112,如第4B圖所示,以增加半導體元件160之散熱面積。
接著,請參照第5X~5Y圖,分別形成一焊球190於焊接層150上,並切割封裝基板100以及封膠層180,以形成多個半導體元件160之封裝結構。在第5X圖中,多個焊球190形成於焊接層150上,一個焊球190對應連接一個焊接層150,焊球190之材質可為無鉛錫膏或有鉛錫膏。在第5X圖中,以刀具沿著切割線L分開兩個半導體元件之封裝結構101,例如為晶片尺寸封裝(chip scale package)之結構,也不需再保留環狀補強結構53於其中,以縮小封裝體積。
第6A及6B圖繪示一實施例之封裝基板200的俯視圖及沿著A-A線剖面示意圖,第7A及7B圖繪示另一實施例之封裝基板200的俯視圖及沿著B-B線剖面示意圖。在第6A及6B圖中,封裝基板200包括一環狀補強結構202以
及四個封裝單元204,環狀補強結構202具有四個以肋條203分開之開口205,一個開口205對應顯露一個封裝單元204,各個封裝單元204例如分為12個元件區塊206,此12個元件區塊206被介電層210包覆,且各個封裝單元204之周圍以肋條203彼此相連,以避免翹曲或變形。此外,在第7A及7B圖中,環狀補強結構202具有一個較大開口207,對應顯露四個封裝單元204,各個封裝單元204例如分為12個元件區塊206,此48個元件區塊206被介電層210一起包覆,且四個封裝單元204之最外圍連接環狀補強結構202,以避免翹曲或變形。
請參照第8A及8B圖,其繪示於環狀補強結構53上形成定位孔57之流程圖。當第三光阻層60形成於導電基板50上時,第三開口62除了顯露導電基板50之中間部之外,更可顯露導電基板50的部分外側部55,此外側部55以蝕刻的方式移除而形成一定位孔57於環狀補強結構53上。在本實施例中,定位孔57可做為半導體元件160定位(參見第5T圖)時之參考點。當然,定位孔57亦可在形成第一光阻層52之前(參見第5A圖)形成在導電基板50的外側部55,對此,本發明不加以限制。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
50‧‧‧導電基板
51‧‧‧第四開口
52‧‧‧第一光阻層
53‧‧‧環狀補強結構
54‧‧‧第一開口
55‧‧‧外側部
56‧‧‧第二光阻層
57‧‧‧定位孔
58‧‧‧第二開口
60‧‧‧第三光阻層
62‧‧‧第三開口
64‧‧‧第四光阻層
66‧‧‧第五開口
100、200‧‧‧封裝基板
101‧‧‧半導體元件之封裝結構
110、210‧‧‧介電層
111、121‧‧‧側壁
112‧‧‧上表面
113‧‧‧凹穴
114‧‧‧下表面
120‧‧‧第一導電層
122‧‧‧第一表面
123‧‧‧凹穴
130‧‧‧第二導電層
132‧‧‧第二表面
140‧‧‧接合墊
150‧‧‧焊接層
160‧‧‧半導體元件
162‧‧‧導電凸塊
170‧‧‧底膠層
180‧‧‧封膠層
190‧‧‧焊球
202‧‧‧環狀補強結構
203‧‧‧肋條
204‧‧‧封裝單元
205‧‧‧開口
206‧‧‧元件區塊
207‧‧‧較大開口
第1A及1B圖分別繪示依照本發明一實施例之封裝基板的示意圖及沿著I-I線的剖面示意圖。
第2A及2B圖分別繪示依照本發明一實施例之封裝基板的示意圖及沿著I-I線的剖面示意圖。
第3A及3B圖分別繪示依照本發明一實施例之封裝基板的示意圖及沿著I-I線的剖面示意圖。
第4A~4C圖分別繪示依照本發明一實施例之半導體元件之封裝結構的示意圖。
第5A~5S圖繪示依照本發明一實施例之封裝基板製程的示意圖。
第5T~5Y圖繪示依照本發明一實施例之半導體元件之封裝製程的示意圖。
第6A及6B圖繪示一實施例之封裝基板的俯視圖及沿著A-A線剖面示意圖。
第7A及7B圖繪示另一實施例之封裝基板的俯視圖及沿著B-B線剖面示意圖。
第8A及8B圖繪示於環狀補強結構53上形成定位孔之流程圖。
100‧‧‧封裝基板
110‧‧‧介電層
112‧‧‧上表面
114‧‧‧下表面
120‧‧‧第一導電層
121‧‧‧側壁
122‧‧‧第一表面
123‧‧‧凹穴
130‧‧‧第二導電層
132‧‧‧第二表面
140‧‧‧接合墊
150‧‧‧焊接層
Claims (31)
- 一種封裝基板,包括:一介電層,具有一上表面以及一下表面;一第一導電層,內埋於該介電層中,並顯露一第一表面於該介電層之上表面,該第一表面切齊該介電層之上表面或內凹於該介電層之上表面;以及一第二導電層,內埋於該介電層中與該第一導電層接觸,並顯露一第二表面於該介電層之下表面,該第二表面切齊於該介電層之下表面或內凹於該介電層之下表面。
- 如申請專利範圍第1項所述之封裝基板,更包括一接合墊,配置於該第一導電層之第一表面上或內埋於該第一導電層中。
- 如申請專利範圍第2項所述之封裝基板,其中當該第一導電層之第一表面內凹於該介電層之上表面時,該接合墊部分地或全部地內埋於該介電層中,以使該接合墊之相對兩側單獨被該介電層的側壁限制於一凹穴內。
- 如申請專利範圍第2項所述之封裝基板,其中當該第一導電層之第一表面切齊該介電層之上表面時,該接合墊部分地或全部地內埋於該第一導電層與該介電層中,以使該接合墊之周圍同時被該第一導電層與該介電層之側壁限制於該一凹穴內。
- 如申請專利範圍第2項所述之封裝基板,其中當該第一導電層之第一表面切齊該介電層之上表面時,該接合墊配置於該第一導電層之第一表面上。
- 如申請專利範圍第1項所述之封裝基板,更包括 一環形補強結構,連接於該介電層之周圍,該環形補強結構環繞該介電層的該上表面,並顯露該第一導電層之該第一表面於該環形補強結構之一開口中。
- 如申請專利範圍第6項所述之封裝基板,其中該環形補強結構具有一定位孔。
- 如申請專利範圍第1項所述之封裝基板,更包括一焊接層,覆蓋該第二導電層之該第二表面。
- 一種封裝基板製程,包括:提供一導電基板;形成一第一光阻層於該導電基板上,該第一光阻層經圖案化而形成複數個第一開口,以顯露出部分該導電基板;形成一第一導電層於該些第一開口中;形成一第二光阻層於該第一光阻層以及該第一導電層上,該第二光阻層經圖案化而形成複數個第二開口,以顯露出部分該第一導電層;形成一第二導電層於該些第二開口中,並與該第一導電層接觸;移除該第一及第二光阻層;形成一介電層於該導電基板上,該介電層覆蓋該第一導電層、該第二導電層以及部分該導電基板;移除部分該介電層,以顯露出該第二導電層之一表面於該介電層之下表面,該第二導電層之該表面切齊於該介電層之下表面;形成一第三光阻層於該導電基板以及該介電層上,該 第三光阻層經圖案化而形成一第三開口,以顯露出部分該導電基板;移除部分該導電基板,以形成一第四開口,並顯露該第一導電層之一表面與該介電層之上表面於該第四開口中,該第一導電層之該表面切齊於該介電層之上表面;移除該第三光阻層;形成一第四光阻層於該導電基板、該介電層、該第一導電層以及該第二導電層上,該第四光阻層經圖案化而形成一第五開口,以顯露出該第一導電層之部分該表面;形成一接合墊於該第五開口中;以及移除該第四光阻層。
- 如申請專利範圍第9項所述之封裝基板製程,其中形成該第四開口之後,更包括蝕刻該第一導電層之該表面,以使該第一導電層之該表面內凹於該該介電層之上表面。
- 如申請專利範圍第9項所述之封裝基板製程,其中形成該第五開口之後,更包括蝕刻該第一導電層之部分該表面,以形成一凹穴。
- 如申請專利範圍第9項所述之封裝基板製程,其中移除部分該導電基板時,未被移除的該導電基板的外側部形成一環形補強結構,連接於該介電層之周圍,且該環形補強結構環繞該介電層的該上表面。
- 如申請專利範圍第9項所述之封裝基板製程,更包括移除該導電基板之部分外側部,以形成一定位孔於該環形補強結構中。
- 如申請專利範圍第9項所述之封裝基板製程,其中移除該第四光阻層後,更包括形成一焊接層於該第二導電層上,該焊接層覆蓋該第二導電層之該表面。
- 一種半導體元件之封裝結構,包括:一封裝基板,其包括:一介電層,具有一上表面以及一下表面;一第一導電層,內埋於該介電層中,並顯露一第一表面於該介電層之上表面,該第一表面切齊該介電層之上表面或內凹於該介電層之上表面;一第二導電層,內埋於該介電層中與該第一導電層接觸,並顯露一第二表面於該介電層之下表面,該第二表面切齊於該介電層之下表面或內凹於該介電層之下表面;以及一半導體元件,配置於該封裝基板上,該半導體元件具有一導電凸塊,該導電凸塊支撐於該半導體元件與該封裝基板之間。
- 如申請專利範圍第15項所述之半導體元件之封裝結構,其中該導電凸塊連接該第一導電層。
- 如申請專利範圍第15項所述之半導體元件之封裝結構,其中該封裝基板更包括一接合墊,配置於該第一導電層之第一表面上或內埋於該第一導電層中。
- 如申請專利範圍第17項所述之半導體元件之封裝結構,其中該電性接點連接該接合墊。
- 如申請專利範圍第17項所述之半導體元件之封裝結構,其中當該第一導電層之第一表面內凹於該介電層 之上表面時,該接合墊部分地或全部地內埋於該介電層中,以使該接合墊之相對兩側單獨被該介電層的側壁限制於一凹穴內。
- 如申請專利範圍第17項所述之半導體元件之封裝結構,其中當該第一導電層之第一表面切齊該介電層之上表面時,該接合墊部分地或全部地內埋於該第一導電層與該介電層中,以使該接合墊之周圍同時被該第一導電層與該介電層之側壁限制於該一凹穴內。
- 如申請專利範圍第17項所述之半導體元件之封裝結構,其中當該第一導電層之第一表面切齊該介電層之上表面時,該接合墊配置於該第一導電層之第一表面上。
- 如申請專利範圍第16項所述之半導體元件之封裝結構,其中該導電凸塊包括銅柱和焊料點。
- 如申請專利範圍第15項所述之半導體元件之封裝結構,更包括:一焊接層,覆蓋該第二導電層之該第二表面;以及一焊球,形成於該焊接層上。
- 一種半導體元件之封裝製程,包括:提供一導電基板;形成一第一光阻層於該導電基板上,該第一光阻層經圖案化而形成複數個第一開口,以顯露出部分該導電基板;形成一第一導電層於該些第一開口中;形成一第二光阻層於該第一光阻層以及該第一導電層上,該第二光阻層經圖案化而形成複數個第二開口,以 顯露出部分該第一導電層;形成一第二導電層於該些第二開口中,並與該第一導電層接觸;移除該第一及第二光阻層;形成一介電層於該導電基板上,該介電層覆蓋該第一導電層、該第二導電層以及部分該導電基板;移除部分該介電層,以顯露出該第二導電層之一表面於該介電層之下表面,該第二導電層之該表面切齊於該介電層之下表面;形成一第三光阻層於該導電基板、該介電層、該第一導電層以及該第二導電層上,該第三光阻層經圖案化而形成一第三開口,以顯露出部分該導電基板;移除部分該導電基板,以形成一第四開口,並顯露該第一導電層之一表面與該介電層之上表面於該第四開口中,該第一導電層之該表面切齊於該介電層之上表面;移除該第三光阻層;形成一第四光阻層於該導電基板、該介電層、該第一導電層以及該第二導電層上,該第四光阻層經圖案化而形成一第五開口,以顯露出該第一導電層之部分該表面;形成一接合墊於該第五開口中;移除該第四光阻層;形成由該介電層、該第一導電層、該第二導電層以及該接合墊所組成之一封裝基板;以及配置一半導體元件於該封裝基板上,該半導體元件具有一導電凸塊,該導電凸塊連接該接合墊,且該導電凸塊 支撐於該半導體元件與該封裝基板之間。
- 如申請專利範圍第24項所述之半導體元件之封裝製程,其中形成該第四開口之後,更包括蝕刻該第一導電層之該表面,以使該第一導電層之該表面內凹於該該介電層之上表面。
- 如申請專利範圍第24項所述之半導體元件之封裝製程,其中形成該第五開口之後,更包括蝕刻該第一導電層之部分該表面,以形成一凹穴。
- 如申請專利範圍第24項所述之半導體元件之封裝製程,其中移除部分該導電基板時,未被移除的該導電基板的外側部形成一環形補強結構,連接於該介電層之周圍,且該環形補強結構環繞該介電層的該上表面。
- 如申請專利範圍第27項所述之半導體元件之封裝製程,更包括移除該導電基板之部分外側部,以形成一定位孔於該環形補強結構中。
- 如申請專利範圍第24項所述之半導體元件之封裝製程,其中移除該第四光阻層之後,更包括:形成一焊接層於該第二導電層上,該焊接層覆蓋該第二導電層之該表面;以及形成一焊球於該焊接層上。
- 如申請專利範圍第24項所述之半導體元件之封裝製程,更包括切割該封裝基板以及該封膠層,以形成複數個半導體元件之封裝結構。
- 如申請專利範圍第24項所述之半導體元件之封裝製程,更包括: 形成一底膠層,以包覆該導電凸塊之周圍;以及形成一封膠層,以包覆該半導體元件以及該底膠層之周圍。
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CN103066051B (zh) | 2017-03-01 |
US20160293416A1 (en) | 2016-10-06 |
CN103066051A (zh) | 2013-04-24 |
US20130113099A1 (en) | 2013-05-09 |
US9379044B2 (en) | 2016-06-28 |
US9892916B2 (en) | 2018-02-13 |
CN106711104A (zh) | 2017-05-24 |
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