CN106711104A - 封装基板及其制作工艺、半导体元件封装结构及制作工艺 - Google Patents
封装基板及其制作工艺、半导体元件封装结构及制作工艺 Download PDFInfo
- Publication number
- CN106711104A CN106711104A CN201611207737.6A CN201611207737A CN106711104A CN 106711104 A CN106711104 A CN 106711104A CN 201611207737 A CN201611207737 A CN 201611207737A CN 106711104 A CN106711104 A CN 106711104A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- conductive
- conductive layer
- depression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title description 19
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 239000010949 copper Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 21
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 238000003466 welding Methods 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 230000003014 reinforcing effect Effects 0.000 claims 4
- 239000010410 layer Substances 0.000 description 264
- 229920002120 photoresistant polymer Polymers 0.000 description 60
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 13
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 12
- 239000012790 adhesive layer Substances 0.000 description 10
- 239000010931 gold Substances 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000007800 oxidant agent Substances 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 235000009854 Cucurbita moschata Nutrition 0.000 description 2
- 240000001980 Cucurbita pepo Species 0.000 description 2
- 235000009852 Cucurbita pepo Nutrition 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000003755 preservative agent Substances 0.000 description 2
- 235000020354 squash Nutrition 0.000 description 2
- 241000196324 Embryophyta Species 0.000 description 1
- 229910000792 Monel Inorganic materials 0.000 description 1
- 244000131316 Panax pseudoginseng Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 208000002925 dental caries Diseases 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明公开一种封装基板及半导体元件的封装结构。封装基板包括介电层以及第一导电层。介电层具有上表面以及下表面。第一导电层内埋于介电层中,并位于介电层的上表面与介电层的下表面之间,第一导电层具有一第一表面,第一表面平行于介电层的上表面。第一导电层具有至少一凹穴,凹穴位于第一导电层的部分第一表面处,以使凹穴的侧壁被第一导电层以及介电层限制,第一导电层其余的第一表面完全曝露于介电层的上表面。
Description
本申请是申请日为2012年10月19日且发明名称为“封装基板及其制作工艺、半导体元件封装结构及制作工艺”的中国发明专利申请201210401532.7的分案申请。
技术领域
本发明涉及一种封装结构及制作工艺,且特别是涉及一种封装基板、封装基板制作工艺、半导体元件的封装结构及其制作工艺。
背景技术
随着电子产品的普遍应用于日常生活中,半导体元件需求量与日遽增。由于半导体元件走向轻薄化的设计,当半导体元件尺寸缩小时,I/O脚数不减反增,使得线路间距与线路宽度缩小化,并朝微小间距(fine pitch)的设计发展,例如50μm间距,甚至35μm以下间距。
然而,在半导体元件倒装组装于封装基板的过程中,常会因焊锡高温回焊,而使两相邻的导电凸块间发生桥接(bridging)短路的现象。此外,焊锡因无防焊层覆盖在线路层上,以限制其流动,使得焊锡高温回焊时,容易沿着线路层向外扩散(overspreading),造成倒装后的半导体元件与封装基板间的高度减少,且因高度减少而难以将底胶层填入于半导体元件与封装基板之间,造成封装的可靠度下降等问题。
发明内容
本发明的目的在于提供一种封装基板、封装基板制作工艺、半导体元件的封装结构及其制作工艺,可在符合微小间距的设计下,提高半导体元件的封装可靠度。
为达上述目的,根据本发明的一方面,提出一种封装基板,包括一介电层、一第一导电层以及一第二导电层。介电层具有一上表面以及一下表面。第一导电层内埋于介电层中,并显露一第一表面于上表面。第一表面切齐上表面或内凹于上表面。第二导电层内埋于介电层中与第一导电层接触,并显露一第二表面于下表面。第二表面切齐于下表面或内凹于下表面。
根据本发明的另一方面,提出一种封装基板制作工艺,包括下列步骤。提供一导电基板。形成一第一光致抗蚀剂层于导电基板上,第一光致抗蚀剂层经图案化而形成多个第一开口,以显露出部分导电基板。形成一第一导电层于此些第一开口中。形成一第二光致抗蚀剂层于第一光致抗蚀剂层以及第一导电层上,第二光致抗蚀剂层经图案化而形成多个第二开口,以显露出部分第一导电层。形成一第二导电层于此些第二开口中,并与第一导电层接触。移除第一及第二光致抗蚀剂层。形成一介电层于导电基板上,介电层覆盖第一导电层、第二导电层以及部分导电基板。移除部分介电层,以显露出第二导电层的一表面于介电层的下表面,第二导电层的表面切齐于介电层的下表面。形成一第三光致抗蚀剂层于导电基板以及介电层上,第三光致抗蚀剂层经图案化而形成一第三开口,以显露出部分导电基板。移除部分导电基板,以形成一第四开口,并显露第一导电层的一表面与介电层的上表面于第四开口中,第一导电层的表面切齐于介电层的上表面。移除第三光致抗蚀剂层。形成一第四光致抗蚀剂层于导电基板、介电层、第一导电层以及第二导电层上,第四光致抗蚀剂层经图案化而形成一第五开口,以显露出第一导电层的部分表面。形成一接合垫于第五开口中。移除第四光致抗蚀剂层。此外,还可形成一焊接层于第二导电层上,焊接层覆盖第二导电层的表面。
根据本发明的另一方面,提出一种半导体元件的封装结构,包括一封装基板、一半导体元件、一底胶层以及一封胶层。封装基板包括一介电层、一第一导电层以及一第二导电层。介电层具有一上表面以及一下表面。第一导电层内埋于介电层中,并显露一第一表面于上表面。第一表面切齐上表面或内凹于上表面。第二导电层内埋于介电层中与第一导电层接触,并显露一第二表面于下表面。第二表面切齐于下表面或内凹于下表面。半导体元件配置于封装基板上,半导体元件具有一导电凸块。导电凸块支撑于半导体元件与封装基板之间。
根据本发明的另一方面,提出一种半导体元件的封装制作工艺,包括下列步骤。提供一导电基板。形成一第一光致抗蚀剂层于导电基板上,第一光致抗蚀剂层经图案化而形成多个第一开口,以显露出部分导电基板。形成一第一导电层于此些第一开口中。形成一第二光致抗蚀剂层于第一光致抗蚀剂层以及第一导电层上,第二光致抗蚀剂层经图案化而形成多个第二开口,以显露出部分第一导电层。形成一第二导电层于此些第二开口中,并与第一导电层接触。移除第一及第二光致抗蚀剂层。形成一介电层于导电基板上,介电层覆盖第一导电层、第二导电层以及部分导电基板。移除部分介电层,以显露出第二导电层的一表面于介电层的下表面,第二导电层的表面切齐于介电层的下表面。形成一第三光致抗蚀剂层于导电基板、介电层、第一导电层以及第二导电层上,第三光致抗蚀剂层经图案化而形成一第三开口,以显露出部分导电基板。移除部分导电基板,以形成一第四开口,并显露第一导电层的一表面与介电层的上表面于第四开口中。第一导电层的表面切齐于介电层的上表面。移除第三光致抗蚀剂层。形成一第四光致抗蚀剂层于导电基板、介电层、第一导电层以及第二导电层上,第四光致抗蚀剂层经图案化而形成一第五开口,以显露出第一导电层的部分表面。形成一接合垫于第五开口中。移除第四光致抗蚀剂层。形成一焊接层于第二导电层上,焊接层覆盖第二导电层的表面,以形成由介电层、第一导电层、第二导电层以及接合垫所组成的一封装基板。配置一半导体元件于封装基板上,半导体元件具有一导电凸块,导电凸块连接接合垫,且导电凸块支撑于半导体元件与封装基板之间。
为了对本发明的上述及其他方面有更佳的了解,下文特举实施例,并配合所附附图,作详细说明如下:
附图说明
图1A及图1B分别绘示依照本发明一实施例的封装基板的示意图及沿着I-I线的剖面示意图;
图2A及图2B分别绘示依照本发明一实施例的封装基板的示意图及沿着I-I线的剖面示意图;
图3A及图3B分别绘示依照本发明一实施例的封装基板的示意图及沿着I-I线的剖面示意图;
图4A~图4C分别绘示依照本发明一实施例的半导体元件的封装结构的示意图;
图5A~图5S绘示依照本发明一实施例的封装基板制作工艺的示意图;
图5T~图5Y绘示依照本发明一实施例的半导体元件的封装制作工艺的示意图;
图6A及图6B绘示一实施例的封装基板的俯视图及沿着A-A线剖面示意图;
图7A及图7B绘示另一实施例的封装基板的俯视图及沿着B-B线剖面示意图;
图8A及图8B绘示于环状补强结构53上形成定位孔的流程图。
主要元件符号说明
50:导电基板
51:第四开口
52:第一光致抗蚀剂层
53:环状补强结构
54:第一开口
55:外侧部
56:第二光致抗蚀剂层
57:定位孔
58:第二开口
60:第三光致抗蚀剂层
62:第三开口
64:第四光致抗蚀剂层
66:第五开口
100、200:封装基板
101:半导体元件的封装结构
110、210:介电层
111、121:侧壁
112:上表面
113:凹穴
114:下表面
120:第一导电层
122:第一表面
123:凹穴
130:第二导电层
132:第二表面
140:接合垫
150:焊接层
160:半导体元件
162:导电凸块
170:底胶层
180:封胶层
190:焊球
202:环状补强结构
203:肋条
204:封装单元
205:开口
206:元件区块
207:较大开口
具体实施方式
本实施例的封装基板、封装基板制作工艺、半导体元件的封装结构及其制作工艺,可应用在高I/O脚数的封装结构中,且无须在防焊层覆盖封装基板的表面来防止焊锡桥接短路的情况下,导线之间仍能维持在微小间距(Fine pitch)的精度下。较佳地,焊锡可被限制于预定的凹穴内而无法流动、封装基板内连接线结构的高度可通过上、下堆叠的导体层而缩短、封装基板的强度可通过环状补强结构的环绕而提高,避免翘曲或变形,进而改善半导体元件的封装可靠度。
以下提出各种实施例进行详细说明,实施例仅用以作为范例说明,并非用以限缩本发明欲保护的范围。
图1A及图1B分别绘示依照本发明一实施例的封装基板的示意图及沿着I-I线的剖面示意图。图2A及图2B分别绘示依照本发明一实施例的封装基板的示意图及沿着I-I线的剖面示意图。图3A及图3B分别绘示依照本发明一实施例的封装基板的示意图及沿着I-I线的剖面示意图。
请参照图1A及图1B,封装基板100包括一介电层110、一第一导电层120、一第二导电层130、一接合垫140以及一焊接层150。介电层110具有一上表面112以及一下表面114。第一导电层120内埋于介电层110中,并显露一第一表面122于上表面112。第二导电层130内埋于介电层110中,并显露一第二表面132于下表面114。接合垫140配置于由第一导电层120的侧壁121与介电层110的侧壁111(参见图1B)所定义的一凹穴123中。当第一表面122切齐上表面112时,接合垫140部分地(或全部地)内埋于第一导电层120与介电层110中,以使接合垫140的周围同时被第一导电层120的侧壁121与介电层110的侧壁111(参见图1B)限制于凹穴123内而无法流动,因此可避免在高温回焊下接合垫140(例如焊锡)发生桥接短路的现象。接合垫140的材质例如选自于锡(Sn)、铜(Cu)、银(Ag)、镍(Ni)、钯(Pd)、金(Au)或其组合,较佳为可回焊(reflowable)的焊接材料。
在图1A中,第一表面122切齐介电层110的上表面112,第二表面132切齐于介电层110的下表面114。在图2A中,第一表面122内凹于介电层110的上表面112,第二表面132内凹于介电层110的下表面114。当第一表面122内凹于介电层110的上表面112时,接合垫140部分地(或全部地)内埋于介电层110的凹穴113中,以使接合垫140的相对两侧单独被介电层110的侧壁111(参见图2B)限制于凹穴113内而无法流动,因此可避免在高温回焊下接合垫140(例如焊锡)发生桥接短路的现象。此外,当第二表面132内凹于下表面114时,可固定焊球190(参见图4A)于各个焊接层150上,以使植球的品质更加稳定。
接着,请参照图3A及图3B,在确保不会发生焊锡桥接短路的情况下,接合垫140可直接形成在第一导电层120的第一表面122上,第一导电层的材质可为抗腐蚀的镍铜合金、镍铬合金等,而接合垫140的材质例如选自于锡(Sn)、铜(Cu)、银(Ag)、镍(Ni)、钯(Pd)、金(Au)或其组合,较佳为不需回焊的凸块,例如为结线凸块(stud bump)。
请参照图4A~图4C,其分别绘示依照本发明一实施例的半导体元件的封装结构的示意图。在图4A~图4C中,采用的封装基板可为图1A、图2A及图3A中任一种封装基板100,其详细内容已揭示如上,在此不再赘述。在图4A~图4C中,半导体元件160配置于封装基板100上。半导体元件160具有多个导电凸块162,图中仅绘示三个导电凸块162,一个导电凸块162对应连接一个接合垫140,且导电凸块162支撑于半导体元件160与封装基板100之间。相对于接合垫140而言,导电凸块162具有较高的熔点,因此当接合垫140受热而融化时,未融化的导电凸块162仍有足够的高度支撑半导体元件160,以维持适当的间距于半导体元件160与封装基板100之间。导电凸块162例如为电镀的铜柱,其具有一预定高度,而接合垫140例如为焊锡,当导电凸块162与接合垫140连接时,如图1A及图2A所示,接合垫140较佳为被限制于凹穴123内而无法流动,因此可避免在高温回焊下接合垫140发生桥接短路的现象。此外,导电凸块162还可包括铜柱和焊料点设置于铜柱上,其焊料点部分粘接于接合垫140。
此外,底胶层170包覆导电凸块162的周围,底胶层170较佳为热固化型环氧树酯,具有流动快及快速固化的优点,可于回焊过程中同时固化,以使接合垫140不会受到底胶层170流动的影响,并能维持导电凸块162与接合垫140之间的导电性。另外,封胶层180包覆半导体元件160以及底胶层170的周围,封胶层180较佳为热固化型环氧树酯,以保护半导体元件160。再者,多个焊球190形成于焊接层150上,图中仅绘示三个焊球190,一个焊球190对应连接一个焊接层150,焊球190的材质可为无铅锡膏或有铅锡膏。
在图4B中,封胶层180包覆半导体元件160以及底胶层170的周围,并显露出半导体元件160的上表面112。封胶层180较佳以转注成型(transfer molding)的方式形成,并经高温烘烤而固化成型。
在图4C中,导电凸块162例如为结线凸块,其材质较佳为铜或金,导电凸块162的尖端可穿过流动性较低的底胶层170,并与底胶层170下方的接合垫140电连接。底胶层170包覆于导电凸块162的周围,其材质可为热固化型不导电胶。
另一实施例中,封装基板100上可以不设置接合垫160。导电凸块162包括铜柱和焊料点设置于铜柱上,其焊料点部分直接与第一导电层120粘接,从而使半导体元件160形成于半导体基板上。导电凸块162与第一导电层120连接时,导电凸块162较佳为被限制于该介电层110的侧壁内而无法流动,由于第一导电层120的表面内凹于介电层110的上表面,从而具有限制导电凸块162位移的作用,使得导电凸块162准确地定位于第一导电层120上。
于以上几种实施例,由于第一导电层120的表面内凹于介电层110的上表面的设计,增长了相邻二第一导电层沿着封装体的外表面的路径长度,如此可避免电移(Electromigration)发生时,相邻二第一导电层短路的风险。
请参照图5A~图5Y,其中图5A~图5S绘示依照本发明一实施例的封装基板制作工艺的示意图,而图5T~图5Y绘示依照本发明一实施例的半导体元件的封装制作工艺的示意图。首先,请参照图5A~图5D,提供一导电基板50,并形成一第一光致抗蚀剂层52于导电基板50上,第一光致抗蚀剂层52经图案化而形成多个第一开口54,以显露出部分导电基板50。之后,形成一第一导电层120于此些第一开口54中。在图5A中,导电基板50为金属基板,较佳为铜板或镀有铜层的钢板。在图5B及图5C中,第一光致抗蚀剂层52例如以旋转涂布的方式形成在导电基板50上,并经过烘烤、曝光、显影等步骤以图案化第一光致抗蚀剂层52,以使第一光致抗蚀剂层52具有多个第一开口54。在图5D中,第一导电层120例如以电镀的方式形成在第一开口54中,其材质较佳为铜、镍、金或其组合。
接着,请参照图5E~图5H,形成一第二光致抗蚀剂层56于第一光致抗蚀剂层52以及第一导电层120上,第二光致抗蚀剂层56经图案化而形成多个第二开口58,以显露出部分第一导电层120。形成一第二导电层130于此些第二开口58中。之后,移除第一光致抗蚀剂层52及第二光致抗蚀剂层56。在图5E及图5F中,第二光致抗蚀剂层56例如以旋转涂布的方式形成在导电基板50上,并经过烘烤、曝光、显影等步骤以图案化第二光致抗蚀剂层56,以使第二光致抗蚀剂层56具有多个第二开口58。在图5G中,第二导电层130例如以电镀的方式形成在第二开口58中,其材质较佳为铜、镍、金或其组合。第二导电层130与第一导电层120直接接触而上、下堆叠,以做为内连接线结构。在图5H中,第一光致抗蚀剂层52与第二光致抗蚀剂层56以去光致抗蚀剂剂(例如丙酮)移除,而显露出相互堆叠的第一导电层120以及第二导电层130。虽然,本实施例仅绘示第一导电层120与第二导电层130,但也可形成二层以上的导电层,对此,本发明不加以限制。
接着,请参照图5I~图5L,形成一介电层110于导电基板50上,介电层110覆盖第一导电层120、第二导电层130以及部分导电基板50。移除部分介电层110,以显露出第二导电层130的一表面(即第二表面132)于介电层110的下表面114。第二导电层130的第二表面132切齐于介电层110的下表面114。之后,形成一第三光致抗蚀剂层60于导电基板50以及介电层110上,第三光致抗蚀剂层60经图案化而形成一第三开口62,以显露出部分导电基板50。在图5I中,介电层110例如以转注成型的方式形成在导电基板50上,亦即以液态状的介电层110注入模穴中,并经烘烤而固化成型。但介电层110也可以模压成型(compressionmolding)的方式形成在导电基板50上,并使半固化态的介电层110在高温下完全固化而成型。在图5J中,部分介电层110例如以机械研磨(grinding)及/或抛光(buffing)的方式移除,以使第二导电层130的第二表面132显露于介电层110外,并与介电层110的下表面114切齐。此外,第二导电层130的第二表面132还可经由蚀刻而内凹于介电层110的下表面114,如图2A所示,以方便植球。在图5K及图5L中,第三光致抗蚀剂层60例如以挤压式(slit die)涂布法或浸渍涂布法(dip coating)形成在导电基板50上,并经由烘烤、曝光、显影等步骤以图案化第三光致抗蚀剂层60,以使第三光致抗蚀剂层60具有一第三开口62。
接着,请参照图5M~图5P,移除部分导电基板50,以形成一第四开口51,并显露第一导电层120的一表面与介电层110的上表面112于第四开口51中。第一导电层120的表面切齐于介电层110的上表面112。移除第三光致抗蚀剂层60。之后,形成一第四光致抗蚀剂层64于导电基板50、介电层110、第一导电层120以及第二导电层130上,第四光致抗蚀剂层64经图案化而形成一第五开口66,以显露出第一导电层120的部分表面。在图5M中,导电基板50例如以湿式蚀刻的方式形成第四开口51,图中仅绘示一个第四开口51,而未被蚀刻的部分导电基板50则形成一环状补强结构53,连接于介电层110的周围。环状补强结构53环绕于介电层110的上表面112,可补强整体基板的强度,以避免翘曲或变形。此外,第一导电层120的表面还可全面蚀刻而内凹于介电层110的上表面112,如图2A所示。在图5N中,第三光致抗蚀剂层60以去光致抗蚀剂剂(例如丙酮)移除,而显露出相互堆叠的第一导电层120以及第二导电层130。在图5O及图5P中,第四光致抗蚀剂层64例如以挤压式涂布法或浸渍涂布法形成,并经由烘烤、曝光、显影等步骤以图案化第四光致抗蚀剂层64,以使第四光致抗蚀剂层64具有多个第五开口66。此外,第一导电层120显露于第五开口66中的部分表面还可经由蚀刻而形成一凹穴123,如图1A所示。
接着,请参照图5Q~图5S,形成一接合垫140于第五开口66中。移除第四光致抗蚀剂层64。之后,形成一焊接层150于第二导电层130上,焊接层150覆盖第二导电层130的表面。在图5Q中,接合垫140以电镀的方式形成在第五开口66中,其材质例如选自于锡(Sn)、铜(Cu)、银(Ag)、镍(Ni)、钯(Pd)、金(Au)或其组合,较佳为可回焊(reflowable)的焊接材料。在图5R中,第四光致抗蚀剂层64以去光致抗蚀剂剂(例如丙酮)移除,而显露出相互堆叠的第一导电层120以及第二导电层130。在图5S中,焊接层150例如以无电电镀(electrolessplating)或浸渍(immersion)的方式形成在第二导电层130上,其材质例如选自于锡(Sn)、铜(Cu)、银(Ag)、镍(Ni)、钯(Pd)、金(Au)或其组合,或以有机保焊剂(OrganicSolderability Preservatives,OSP)取代。以上为封装基板100制作工艺的详细说明,接着对半导体元件160的封装制作工艺进行详细说明。
请参照图5T~图5W,配置一半导体元件160于封装基板100上。半导体元件160具有一导电凸块162,导电凸块162连接接合垫140,且导电凸块162支撑于半导体元件160与封装基板100之间。形成一底胶层170以包覆导电凸块162的周围。形成一封胶层180以包覆半导体元件160以及底胶层170的周围。在图5T中,半导体元件160为集成电路元件,其主动表面上配置有多个导电凸块162,图中绘示三个导电凸块162,一个导电凸块162对应一个接合垫140。相对于接合垫140而言,导电凸块162具有较高的熔点,导电凸块162例如为铜柱、铜凸块、金凸块或结线凸块,其具有一预定高度,而接合垫140例如为可回焊的焊接材料。在第5U及5V图中,先形成底胶层170于封装基板100上,再将半导体元件160的导电凸块162穿过流动性较低的底胶层170,并与底胶层170下方的接合垫140电连接,以使底胶层170包覆在导电凸块162的周围。当然,底胶层170除了采用上述方式形成,也可先将半导体元件160配置于封装基板100上,再以流动性较佳的底胶层170填入于半导体元件160与封装基板100之间的间隙中,以包覆在导电凸块162的周围。在图5V中,当导电凸块162与接合垫140连接时,如图1A及图2A所示,接合垫140较佳为被限制于凹穴123内而无法流动,因此可避免在高温回焊下接合垫140发生桥接短路的现象。在图5W中,封胶层180较佳以转注成型(transfermolding)的方式形成,并经高温烘烤而固化成型。此外,封胶层180也可显露半导体元件160的上表面112,如图4B所示,以增加半导体元件160的散热面积。
接着,请参照图5X~图5Y,分别形成一焊球190于焊接层150上,并切割封装基板100以及封胶层180,以形成多个半导体元件160的封装结构。在图5X中,多个焊球190形成于焊接层150上,一个焊球190对应连接一个焊接层150,焊球190的材质可为无铅锡膏或有铅锡膏。在图5X中,以刀具沿着切割线L分开两个半导体元件的封装结构101,例如为芯片尺寸封装(chip scale package)的结构,也不需再保留环状补强结构53于其中,以缩小封装体积。
图6A及图6B绘示一实施例的封装基板200的俯视图及沿着A-A线剖面示意图,图7A及图7B绘示另一实施例的封装基板200的俯视图及沿着B-B线剖面示意图。在图6A及图6B中,封装基板200包括一环状补强结构202以及四个封装单元204,环状补强结构202具有四个以肋条203分开的开口205,一个开口205对应显露一个封装单元204,各个封装单元204例如分为12个元件区块206,此12个元件区块206被介电层210包覆,且各个封装单元204的周围以肋条203彼此相连,以避免翘曲或变形。此外,在图7A及图7B中,环状补强结构202具有一个较大开口207,对应显露四个封装单元204,各个封装单元204例如分为12个元件区块206,此48个元件区块206被介电层210一起包覆,且四个封装单元204的最外围连接环状补强结构202,以避免翘曲或变形。
请参照图8A及图8B,其绘示于环状补强结构53上形成定位孔57的流程图。当第三光致抗蚀剂层60形成于导电基板50上时,第三开口62除了显露导电基板50的中间部之外,还可显露导电基板50的部分外侧部55,此外侧部55以蚀刻的方式移除而形成一定位孔57于环状补强结构53上。在本实施例中,定位孔57可做为半导体元件160定位(参见图5T)时的参考点。当然,定位孔57也可在形成第一光致抗蚀剂层52之前(参见图5A)形成在导电基板50的外侧部55,对此,本发明不加以限制。
综上所述,虽然结合以上较佳实施例公开了本发明,然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作各种的更动与润饰。因此,本发明的保护范围应以附上的权利要求所界定的为准。
Claims (28)
1.一种封装基板,包括:
介电层,具有上表面以及下表面;以及
第一导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,该第一导电层具有一第一表面,该第一表面平行于该介电层的上表面;
其中,该第一导电层具有至少一凹穴,该凹穴位于该第一导电层的部分该第一表面处,以使该凹穴的侧壁被该第一导电层以及该介电层限制,该第一导电层其余的该第一表面完全曝露于该介电层的该上表面。
2.如权利要求1所述的封装基板,还包括一接合垫,设置于该第一导电层的该凹穴中并内埋于该第一导电层中,其中,该接合垫的周围被该凹穴的侧壁限制。
3.如权利要求1所述的封装基板,其中该第一导电层的该第一表面切齐该介电层的上表面或内凹于该介电层的上表面。
4.如权利要求1所述的封装基板,还包括多个导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,其中该多个导电层包括该第一导电层并以自上而下的堆叠方式形成一连接结构,以连接该介电层的上表面至该介电层的下表面。
5.如权利要求1所述的封装基板,还包括一环形补强结构,连接于该介电层的周围,该环形补强结构具有至少一开口,以曝露该介电层的上表面以及该第一导电层的第一表面。
6.如权利要求2所述的封装基板,其中该接合垫为可回焊的焊接材料。
7.如权利要求6所述的封装基板,其中该可回焊的焊接材料在高温下融化,以使该接合垫限制于该凹穴内。
8.一种封装基板,包括:
介电层,具有上表面以及下表面;
第一导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,该第一导电层具有一第一表面,该第一表面平行于该介电层的上表面,其中,该第一导电层的该第一表面完全曝露于该介电层的上表面并内凹于该介电层的上表面;以及
至少一接合垫,设置于该第一导电层的部分该第一表面上,该接合垫被位于该介电层的上表面的一凹穴的侧壁限制。
9.如权利要求8所述的封装基板,还包括多个导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,其中该多个导电层包括该第一导电层并以自上而下的堆叠方式形成一连接结构,以连接该介电层的上表面至该介电层的下表面。
10.如权利要求8所述的封装基板,还包括一环形补强结构,连接于该介电层的周围,该环形补强结构具有至少一开口,以曝露该介电层的上表面以及该第一导电层的第一表面。
11.如权利要求8所述的封装基板,其中该接合垫为可回焊的焊接材料。
12.如权利要求11所述的封装基板,其中该可回焊的焊接材料在高温下融化,以使该接合垫限制于该凹穴内。
13.一种半导体元件的封装结构,包括:
介电层,具有上表面以及下表面;
第一导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,该第一导电层具有一第一表面,该第一表面平行于该介电层的上表面,其中,该第一导电层具有至少一凹穴,该凹穴位于该第一导电层的部分该第一表面处,以使该凹穴的侧壁被该第一导电层以及该介电层限制,该第一导电层其余的该第一表面完全曝露于该介电层的该上表面;以及
半导体元件,设置于该介电层的上表面,该半导体元件具有一导电凸块,该导电凸块连接该第一导电层并对应于该第一导电层的该凹穴。
14.如权利要求13所述的半导体元件的封装结构,其中该导电凸块包括铜柱和焊料点,该导电凸块的焊料点限制于该第一导电层的该凹穴内。
15.如权利要求13所述的半导体元件的封装结构,还包括一接合垫,设置于该第一导电层的该凹穴中并内埋于该第一导电层中,其中,该接合垫的周围被该凹穴的侧壁限制。
16.如权利要求15所述的半导体元件的封装结构,其中该导电凸块连接该接合垫。
17.如权利要求13所述的半导体元件的封装结构,其中该第一导电层的该第一表面切齐该介电层的上表面或内凹于该介电层的上表面。
18.如权利要求13所述的半导体元件的封装结构,还包括多个导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,其中该多个导电层包括该第一导电层并以自上而下的堆叠方式形成一连接结构,以连接该介电层的上表面至该介电层的下表面。
19.如权利要求13所述的半导体元件的封装结构,其中该导电凸块包括铜柱。
20.如权利要求13所述的半导体元件的封装结构,其中该导电凸块还包括焊料点,该焊料点设置于该铜柱上。
21.如权利要求15所述的半导体元件的封装结构,其中该接合垫为可回焊的焊接材料。
22.如权利要求21所述的半导体元件的封装结构,其中该可回焊的焊接材料在高温下融化,以使该接合垫限制于该凹穴内。
23.一种半导体元件的封装结构,包括:
介电层,具有上表面以及下表面;
第一导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,该第一导电层具有一第一表面,该第一表面平行于该介电层的上表面,其中,该第一导电层的该第一表面完全曝露于该介电层的上表面并内凹于该介电层的上表面;
至少一接合垫,设置于该第一导电层的部分该第一表面上,该接合垫被位于该介电层的上表面的一凹穴的侧壁限制;以及
半导体元件,设置于该介电层的上表面,该半导体元件具有一导电凸块,该导电凸块连接该第一导电层并对应于该接合垫。
24.如权利要求23所述的半导体元件的封装结构,还包括多个导电层,内埋于该介电层中,并位于该介电层的上表面与该介电层的下表面之间,其中该多个导电层包括该第一导电层并以自上而下的堆叠方式形成一连接结构,以连接该介电层的上表面至该介电层的下表面。
25.如权利要求23所述的半导体元件的封装结构,其中该导电凸块包括铜柱。
26.如权利要求23所述的半导体元件的封装结构,其中该导电凸块还包括焊料点,该焊料点设置于该铜柱上。
27.如权利要求23所述的半导体元件的封装结构,其中该接合垫为可回焊的焊接材料。
28.如权利要求27所述的半导体元件的封装结构,其中该可回焊的焊接材料在高温下融化,以使该接合垫限制于该凹穴内。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161549258P | 2011-10-20 | 2011-10-20 | |
US61/549,258 | 2011-10-20 | ||
CN201210401532.7A CN103066051B (zh) | 2011-10-20 | 2012-10-19 | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210401532.7A Division CN103066051B (zh) | 2011-10-20 | 2012-10-19 | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106711104A true CN106711104A (zh) | 2017-05-24 |
CN106711104B CN106711104B (zh) | 2021-01-05 |
Family
ID=48108613
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2012205396459U Expired - Lifetime CN202948918U (zh) | 2011-10-20 | 2012-10-19 | 封装基板及半导体元件的封装结构 |
CN201210401532.7A Active CN103066051B (zh) | 2011-10-20 | 2012-10-19 | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 |
CN201611207737.6A Active CN106711104B (zh) | 2011-10-20 | 2012-10-19 | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2012205396459U Expired - Lifetime CN202948918U (zh) | 2011-10-20 | 2012-10-19 | 封装基板及半导体元件的封装结构 |
CN201210401532.7A Active CN103066051B (zh) | 2011-10-20 | 2012-10-19 | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9379044B2 (zh) |
CN (3) | CN202948918U (zh) |
TW (1) | TWI508241B (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101175909B1 (ko) * | 2011-07-27 | 2012-08-22 | 삼성전기주식회사 | 인쇄회로기판의 표면처리 방법 및 인쇄회로기판 |
CN202948918U (zh) * | 2011-10-20 | 2013-05-22 | 先进封装技术私人有限公司 | 封装基板及半导体元件的封装结构 |
US10991669B2 (en) | 2012-07-31 | 2021-04-27 | Mediatek Inc. | Semiconductor package using flip-chip technology |
TWI562295B (en) | 2012-07-31 | 2016-12-11 | Mediatek Inc | Semiconductor package and method for fabricating base for semiconductor package |
US9177899B2 (en) | 2012-07-31 | 2015-11-03 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
US10128175B2 (en) * | 2013-01-29 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company | Packaging methods and packaged semiconductor devices |
CN104217967A (zh) * | 2013-05-31 | 2014-12-17 | 宏启胜精密电子(秦皇岛)有限公司 | 半导体器件及其制作方法 |
US9209046B2 (en) * | 2013-10-02 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
CN103730380B (zh) * | 2013-12-05 | 2017-02-15 | 通富微电子股份有限公司 | 封装结构的形成方法 |
CN103745965B (zh) * | 2013-12-05 | 2017-02-01 | 通富微电子股份有限公司 | 封装结构 |
CN103745964A (zh) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | 封装结构 |
CN103745939B (zh) * | 2013-12-05 | 2017-02-15 | 通富微电子股份有限公司 | 封装结构的形成方法 |
US10002843B2 (en) * | 2015-03-24 | 2018-06-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate structure, semiconductor package and method of manufacturing the same |
US20170084519A1 (en) * | 2015-09-22 | 2017-03-23 | Freescale Semiconductor, Inc. | Semiconductor package and method of manufacturing same |
DE102016103585B4 (de) * | 2016-02-29 | 2022-01-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt |
TWI685283B (zh) * | 2018-11-22 | 2020-02-11 | 大陸商光寶電子(廣州)有限公司 | 電路板結構 |
US11018111B2 (en) * | 2019-05-27 | 2021-05-25 | Texas Instruments Incorporated | Wafer level derived flip chip package |
US20230026254A1 (en) * | 2021-07-21 | 2023-01-26 | Apple Inc. | Flex Board and Flexible Module |
KR20230037800A (ko) | 2021-09-10 | 2023-03-17 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5877559A (en) * | 1995-06-12 | 1999-03-02 | Nitto Denko Corporation | Film carrier for fine-pitched and high density mounting and semiconductor device using same |
JP2000269271A (ja) * | 1999-03-16 | 2000-09-29 | Toshiba Corp | 半導体回路装置およびその製造方法 |
KR20060101716A (ko) * | 2005-03-21 | 2006-09-26 | 삼성전기주식회사 | Bga 인쇄회로기판의 솔더 볼 패드 형성방법 및 이로부터제조된 bga 인쇄회로기판 |
US20080145967A1 (en) * | 2006-12-14 | 2008-06-19 | Advanpack Solutions Pte Ltd. | Semiconductor package and manufacturing method thereof |
CN100438007C (zh) * | 2005-02-07 | 2008-11-26 | 恩益禧电子股份有限公司 | 互连衬底和半导体器件 |
CN101330071A (zh) * | 2007-06-19 | 2008-12-24 | 三星电机株式会社 | 安装基板及其制造方法 |
CN102044515A (zh) * | 2009-10-14 | 2011-05-04 | 日月光半导体制造股份有限公司 | 封装载板、封装结构以及封装载板工艺 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5169680A (en) * | 1987-05-07 | 1992-12-08 | Intel Corporation | Electroless deposition for IC fabrication |
US5349495A (en) * | 1989-06-23 | 1994-09-20 | Vlsi Technology, Inc. | System for securing and electrically connecting a semiconductor chip to a substrate |
US5877599A (en) * | 1996-10-11 | 1999-03-02 | National Semiconductor Corporation | Vertical and horizontal scanning correction system for video display |
JPH10160793A (ja) * | 1996-12-02 | 1998-06-19 | Hitachi Cable Ltd | ベアチップ検査用プローブ基板及びその製造方法、及びベアチップ検査システム |
JPH10256712A (ja) * | 1997-03-13 | 1998-09-25 | Denso Corp | ボールグリッドアレイパッケージ形半導体部品の実装構造 |
US6844253B2 (en) * | 1999-02-19 | 2005-01-18 | Micron Technology, Inc. | Selective deposition of solder ball contacts |
EP1122778A3 (en) * | 2000-01-31 | 2004-04-07 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
JP2001338947A (ja) | 2000-05-26 | 2001-12-07 | Nec Corp | フリップチップ型半導体装置及びその製造方法 |
KR20030033706A (ko) * | 2001-10-24 | 2003-05-01 | 앰코 테크놀로지 코리아 주식회사 | 플립칩 패키지 |
JP3591524B2 (ja) | 2002-05-27 | 2004-11-24 | 日本電気株式会社 | 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ |
US7474538B2 (en) | 2002-05-27 | 2009-01-06 | Nec Corporation | Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package |
JP4108643B2 (ja) * | 2004-05-12 | 2008-06-25 | 日本電気株式会社 | 配線基板及びそれを用いた半導体パッケージ |
US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
CN101356641B (zh) | 2006-01-06 | 2011-05-18 | 日本电气株式会社 | 半导体搭载用布线基板、其制造方法及布线基板组件 |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
TWM322059U (en) * | 2007-05-21 | 2007-11-11 | Phoenix Prec Technology Corp | Package substrate having electrical connecting pad |
TWI357141B (en) * | 2007-12-05 | 2012-01-21 | Unimicron Technology Corp | Package substrate having electrical connecting str |
TWI387076B (zh) * | 2008-04-24 | 2013-02-21 | Mutual Pak Technology Co Ltd | 積體電路元件之封裝結構及其製造方法 |
TWI414048B (zh) | 2008-11-07 | 2013-11-01 | Advanpack Solutions Pte Ltd | 半導體封裝件與其製造方法 |
US20100270668A1 (en) | 2009-04-28 | 2010-10-28 | Wafer-Level Packaging Portfolio Llc | Dual Interconnection in Stacked Memory and Controller Module |
WO2011027186A1 (zh) | 2009-09-02 | 2011-03-10 | 先进封装技术私人有限公司 | 封装结构 |
JP2011082450A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム |
US8569894B2 (en) * | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8866301B2 (en) | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
US8709874B2 (en) * | 2010-08-31 | 2014-04-29 | Advanpack Solutions Pte Ltd. | Manufacturing method for semiconductor device carrier and semiconductor package using the same |
US8476772B2 (en) * | 2010-09-09 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die |
US8865525B2 (en) | 2010-11-22 | 2014-10-21 | Bridge Semiconductor Corporation | Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby |
JP5855905B2 (ja) | 2010-12-16 | 2016-02-09 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
CN102891131B (zh) | 2011-07-22 | 2017-07-14 | 先进封装技术私人有限公司 | 用于制造半导体封装元件的半导体结构及其制造方法 |
CN202948918U (zh) * | 2011-10-20 | 2013-05-22 | 先进封装技术私人有限公司 | 封装基板及半导体元件的封装结构 |
US9723717B2 (en) | 2011-12-19 | 2017-08-01 | Advanpack Solutions Pte Ltd. | Substrate structure, semiconductor package device, and manufacturing method of semiconductor package |
-
2012
- 2012-10-19 CN CN2012205396459U patent/CN202948918U/zh not_active Expired - Lifetime
- 2012-10-19 TW TW101138782A patent/TWI508241B/zh active
- 2012-10-19 CN CN201210401532.7A patent/CN103066051B/zh active Active
- 2012-10-19 CN CN201611207737.6A patent/CN106711104B/zh active Active
- 2012-10-20 US US13/656,703 patent/US9379044B2/en active Active
-
2016
- 2016-06-15 US US15/183,761 patent/US9892916B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5877559A (en) * | 1995-06-12 | 1999-03-02 | Nitto Denko Corporation | Film carrier for fine-pitched and high density mounting and semiconductor device using same |
JP2000269271A (ja) * | 1999-03-16 | 2000-09-29 | Toshiba Corp | 半導体回路装置およびその製造方法 |
CN100438007C (zh) * | 2005-02-07 | 2008-11-26 | 恩益禧电子股份有限公司 | 互连衬底和半导体器件 |
KR20060101716A (ko) * | 2005-03-21 | 2006-09-26 | 삼성전기주식회사 | Bga 인쇄회로기판의 솔더 볼 패드 형성방법 및 이로부터제조된 bga 인쇄회로기판 |
US20080145967A1 (en) * | 2006-12-14 | 2008-06-19 | Advanpack Solutions Pte Ltd. | Semiconductor package and manufacturing method thereof |
CN101330071A (zh) * | 2007-06-19 | 2008-12-24 | 三星电机株式会社 | 安装基板及其制造方法 |
CN102044515A (zh) * | 2009-10-14 | 2011-05-04 | 日月光半导体制造股份有限公司 | 封装载板、封装结构以及封装载板工艺 |
Also Published As
Publication number | Publication date |
---|---|
TW201318122A (zh) | 2013-05-01 |
US20160293416A1 (en) | 2016-10-06 |
US9379044B2 (en) | 2016-06-28 |
CN103066051B (zh) | 2017-03-01 |
CN103066051A (zh) | 2013-04-24 |
US9892916B2 (en) | 2018-02-13 |
CN106711104B (zh) | 2021-01-05 |
CN202948918U (zh) | 2013-05-22 |
TWI508241B (zh) | 2015-11-11 |
US20130113099A1 (en) | 2013-05-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103066051B (zh) | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 | |
CN103367300B (zh) | 引线框、半导体装置以及引线框的制造方法 | |
JP5598787B2 (ja) | 積層型半導体装置の製造方法 | |
US8241967B2 (en) | Semiconductor package with a support structure and fabrication method thereof | |
US20150091118A1 (en) | Package-on-package assembly with wire bonds to encapsulation surface | |
US20130203216A1 (en) | Package-on-package assembly with wire bonds to encapsulation surface | |
CN108063094A (zh) | 基于基板的扇出型晶圆级封装 | |
JP4919103B2 (ja) | ランドグリッドアレイ半導体装置パッケージ、同パッケージを含む組み立て体、および製造方法 | |
CN102456648B (zh) | 封装基板的制法 | |
US8569885B2 (en) | Stacked semiconductor packages and related methods | |
US9132494B2 (en) | Wiring board and method for manufacturing the same | |
JP2008243853A (ja) | インターポーザ基板、それを利用したlsiチップ及び情報端末装置、インターポーザ基板製造方法、並びにlsiチップ製造方法 | |
US9502337B2 (en) | Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof | |
KR20020097036A (ko) | 전자 부품의 실장 기판 및 실장 구조를 갖는 전자 장치 | |
CN112768437B (zh) | 多层堆叠封装结构和多层堆叠封装结构的制备方法 | |
JP3732378B2 (ja) | 半導体装置の製造方法 | |
CN101770994A (zh) | 具有金属突点的半导体封装基板 | |
CN106898593B (zh) | 半导体装置及其制造方法 | |
CN106158792A (zh) | 半导体封装及其制造方法 | |
CN103887187B (zh) | 半导体封装结构的形成方法 | |
CN106876340B (zh) | 半导体封装结构及其制作方法 | |
CN103730440B (zh) | 封装结构 | |
KR20130027870A (ko) | 패키지 기판 및 패키지의 제조 방법 | |
JP4561969B2 (ja) | 半導体装置 | |
US11830845B2 (en) | Package-on-package assembly with wire bonds to encapsulation surface |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |