TWI387076B - 積體電路元件之封裝結構及其製造方法 - Google Patents

積體電路元件之封裝結構及其製造方法 Download PDF

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TWI387076B
TWI387076B TW097114993A TW97114993A TWI387076B TW I387076 B TWI387076 B TW I387076B TW 097114993 A TW097114993 A TW 097114993A TW 97114993 A TW97114993 A TW 97114993A TW I387076 B TWI387076 B TW I387076B
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integrated circuit
layer
conductive
wafer
forming
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TW097114993A
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TW200945526A (en
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Lu Chen Hwan
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Mutual Pak Technology Co Ltd
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Priority to TW097114993A priority Critical patent/TWI387076B/zh
Priority to US12/421,512 priority patent/US7943426B2/en
Priority to JP2009105525A priority patent/JP4819144B2/ja
Publication of TW200945526A publication Critical patent/TW200945526A/zh
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Description

積體電路元件之封裝結構及其製造方法
本發明係關於一種積體電路元件之封裝結構及其製造方法，更具體地是關於晶圓級封裝結構及其方法。
一般晶圓級封裝(wafer level package)是將已製好多個積體電路元件的晶圓透過重佈線、介電材料塗佈及錫球製程直接在晶圓上完成封裝結構。這種晶圓級封裝結構僅適用於尺寸較大，輸出/輸入端較少的積體電路元件。詳言之，由於錫球需要對應到電路板的接點，其間距規範通常不能小於0.25 mm，因此對於尺寸較小而無法提供是夠間距的積體電路元件，就無法適用於一般錫球製程。
習知已有利用二次封裝方式來擴充積體電路元件之可接觸面積的作法，例如將已封裝之積體電路元件切割成粒，然後在一顆顆地移植到一塊面積較大的載板上。接著在這塊面積較大的載板上進行第二次封裝並產生積體電路元件之接觸延伸線進而擴大其可接觸面積。這種習知二次封裝方式製程相當複雜且成本也很高，所以需要一種新穎的積體電路元件封裝結構及其製法來改善習知之上述缺點。
有鑑於上述之需求，本發明係提供一種適用於較小尺寸之積體電路元件的晶圓級封裝結構。
本發明之一特點在於利用可延伸載板將已切割之晶圓其晶粒與晶粒之間的距離擴大之後再封裝，如此將可避免將晶粒一顆顆地移植到另一塊面積較大載板的複雜製程。
依據一實施例，本發明提供一種封裝積體電路元件的方法，包含提供一晶圓，該晶圓具複數個積體電路元件；提供一可延伸載板，具有一第一面及一第二面相對於該第一面，該第一面承載該晶圓；切割該晶圓以形成複數個溝槽使該積體電路元件相互隔離；拉伸該可延伸載板以擴大該複數個溝槽；及形成一絕緣層填充該複數個溝槽並覆蓋該複數個積體電路元件。
本發明之另一特點在於利用貼附在可延伸載板上的抗延伸層來控制可延伸載板所延伸位置。
依據一實施例，本發明提供一種封裝積體電路元件的方法，提供一晶圓，該晶圓具複數個積體電路元件；提供一可延伸載板，具有一第一面及一第二面相對於該第一面，該第一面承載該晶圓；形成複數個抗延伸層於該第二面上；切割該晶圓以形成複數個溝槽使該積體電路元件相互隔離；拉伸該可延伸載板以擴大該複數個溝槽；及形成一絕緣層填充該複數個溝槽並覆蓋該複數個積體電路元件。
本發明之更一特點在於形成至少一通孔及表面導電層於封裝好的積體電路元件上，該通孔及表面導電層可使封裝好的積體電路元件於各個不同的面向都具有對外的接點，藉此更加擴大積體電路元件對外接觸之可利用面積。
依據更另一實施例，本發明提供一種封裝積體電路元件的方法，包含提供一晶圓，該晶圓具複數個積體電路元件；形成複數個導電凸塊於該複數個積體電路元件上；提供一可延伸載板，該可延伸之載板具有一第一面及一第二面相對於該第一面，該第一面承載該晶圓；形成複數個抗延伸層於該第二面上；切割該晶圓以形成複數個溝槽使該積體電路元件相互隔離；拉伸該可延伸載板以擴大每個溝槽；形成一絕緣層填充該複數個溝槽並覆蓋該複數個積體電路元件；形成複數個通孔穿透該絕緣層及該可延伸載板；及形成一表面導體層覆蓋該通孔之內壁，該表面導體層係往外延伸以覆蓋該複數個導電凸塊及該複數個抗延伸層；及去除該表面導體層之一部分以形成一第一線路連接該複數個導電凸塊之頂表面上及一第二線路連接該複數個抗延伸層之表面。
以下將參考所附圖式示範本發明之較佳實施例。所附圖式中相似元件係採用相同的元件符號。應注意為清楚呈現本發明，所附圖式中之各元件並非按照實物之比例繪製，而且為避免模糊本發明之內容，以下說明亦省略習知之零組件、相關材料、及其相關處理技術。
圖1至圖12係剖面圖，例示根據本發明之一第一實施例所形成一封裝結構的方法。首先參照圖1，提供一晶圓100。晶圓100具有複數個積體電路元件102以及形成其上的輸出/輸入接點104與保護層110。積體電路元件102可為二極體，如發光二極體、光電二極體、雷射二極體或整流型二極體；也可為電晶體，如MOS、CMOS等各種類型的電晶體。圖1所示之複數個積體 電路元件102尚未隔開，故以虛線區隔以清楚顯示其各別位置。輸出/輸入接點104之一材料可為鋁，或任何其他合適導電材料。保護層110之一材料可為氮氧化矽，或任何其他可供保護積體電路元件102之材料。
參照圖2，形成複數個導電凸塊200於輸出/輸入接點104上。可用習知鋼板印刷製程製作，例如以經蝕刻或雷射切割的一圖案化網版(較佳為一鋼板)為遮罩，利用印刷機將導體材料通過網版上之開孔印刷至輸出/輸入接點104之表面上以形成導電凸塊200。除了上述方式，其它製程例如電鍍、無電鍍、濺鍍、及沉積微影等等也適用。導體材料可為如銅、銀、或錫膏之金屬或非金屬之導電高分子材料，而且也可視需要摻雜其它高分子黏著劑，例如環氧樹脂等。
參照圖3，提供一可延伸載板300。可延伸載板300具有一第一面300a及一第二面300b相對於第一面300a。第一面300a承載晶圓100。可塗佈一黏著層301於可延伸載板300之第一面300a上以連接晶圓100與可延伸載板300。可延伸載板300可為任何具有支撐功能之基板如軟板、硬板或軟硬板。可延伸載板300可含能被拉伸的彈性材質，例如矽橡膠、聚亞醯胺、聚乙烯或聚丙烯，其中更可含合適的填充料如矽酸鹽等等。黏著層的材質可為丙烯酸酯、環氧樹脂、聚氨酯、或矽膠。
同樣參照圖3所示，視需要在可延伸載板300的第二面300b形成複數個抗延伸層302。抗延伸層302的材料可為任何能附著於可延伸載板300上的材料，較佳為相對於可延伸載板300張力 較強彈性較差的材料。抗延伸層302之功能之一在於控制可延伸載板300之延展位置。當拉伸可延伸載板300時，不被抗延伸層302所覆蓋的部分將更容易拉開。本實施例之每個抗延伸層302係對應每個輸出/輸入接點104，且以導電材料如銅、鋁等金屬或導電高分子等作為抗延伸層302，然不以此為限。導電性抗延伸層302之一優點在於除有抗延伸功能外，還可作為導電線路。除此以外，也可以圖案化可延伸載板300而將抗延伸層302嵌設在可延伸載板300中，這樣的結構同樣可以達到控制可延伸載板300之延展位置的效果，而且可以降低整體厚度。
參照圖4，沿虛線所示位置於晶圓100上形成複數個溝槽400使每個積體電路元件102相互隔離。溝渠400可穿透晶圓100、黏著層301、及一部分之可延伸載板300，但不將可延伸載板300切斷。換言之，在此階段每個積體電路元件102仍藉由可延伸載板300而相互連接。溝槽400的形成方式可利用切割刀、雷射切割、乾式蝕刻或濕式蝕刻等合適製程。
參照圖5，拉伸可延伸載板300以擴大每個溝槽400，增加每個積體電路元件102之間的間距。擴大後之溝槽以500表示。應注意，可延伸載板300具有對應溝槽500之一第一部分501及不對應溝槽500之一第二部分502。於拉伸步驟時，由於第二部分502有積體電路元件102設在上方，因此其拉伸程度將大於第一部分501之拉伸程度。抗延伸層302更是進一步覆蓋第二部分502，第二部分502夾設在積體電路元件102與抗延伸層302之間，如此更可抑制第二部分502於該拉伸步驟時向外延伸。
參照圖6，塗佈絕緣層600於可延伸載板300上方，絕緣層600填充複數個溝槽500並覆蓋複數個積體電路元件102、導電凸塊200及保護層110。絕緣層600的材料可為環氧樹脂、聚亞醯胺、苯并環丁烷、液晶高分子、或其組合，或任何其他合適之封裝材料。若積體電路元件102為光學元件，如發光二極體、光電二極體、CMOS感應器等，絕緣層600的材料則以透明材質為佳。接著，參照圖7，去除絕緣層600之一部分以使複數個導電凸塊200之頂表面露出。執行此步驟後之絕緣層以元件符號700稱之。可以習知之化學機械研磨法來完成此步驟。
參照圖8，形成複數個通孔800穿透位在溝槽500的絕緣層700及可延伸載板300。此複數個通孔800較佳係環繞每個積體電路元件102的週圍。可利用習知之機械鑽孔機或雷射鑽孔技術來完成此步驟。如圖所示，通孔800有一通孔內壁800a係露出絕緣層700及可延伸載板300之第一部分501。
參照圖9，形成一表面導體層900覆蓋之圖8所示結構整體。詳言之，表面導體層900覆蓋絕緣層700、可延伸載板300，包含通孔800之內壁800a，也覆蓋抗延伸層302及複數個導電凸塊200。可利用電鍍、濺鍍、化學氣相沉積、印刷、電鍍或無電鍍等合適的技術執行此步驟。材料可用銅、鋁等金屬或導電高分子。表面導體層900形成之後，通孔800成為可電連接導電凸塊200之導通孔901。應注意表面導體層900可填滿通孔800也可只覆蓋通孔800之內壁800a表面而使導通孔901之仍為中空，本實施例即以後者作為示範說明。
參照圖10，利用習知之微影蝕刻技術去除表面導體層900之一部分而露出其下方之絕緣層700，此步驟可稱為圖案化表面導體層900之步驟。經圖案化之表面導體層900係形成一第一線路1001連接該複數個導電凸塊200之頂表面上及一第二線路1002連接該複數個抗延伸層1002之頂表面。
參照圖11及圖12，將表面導體層900之圖案化之後，可視需要在其表面鍍上導電保護層1101，材料可為鎳或金；也可視需要再塗佈一層防焊油墨(未顯示)於導電保護層1101上方。完成上述步驟之後，沿圖11所示之虛線進行切割以使完成封裝及對外連接之延伸線路的複數個積體電路元件102相互分離而成為顆粒狀的晶片1200。如圖12所示(僅顯示兩個晶片1200)，經封裝晶片1200包含積體電路元件102；經延伸之可延伸載板300，具有第一面300a及第二面300b相對於第一面300a，第一面300a承載積體電路元件102；抗延伸層302設置第二面300b上；及絕緣層700包覆積體電路元件102。經封裝晶片1200更包含導電凸塊200電連接積體電路元件102，導電凸塊200嵌設於絕緣層700中；黏著層301連接經延伸載板300與積體電路元件102；圖案化表面金屬層900覆蓋絕緣層700、導電凸塊200及抗延伸層302；及導電保護層1101覆蓋圖案化表面導體層900。更詳言之，圖案化表面金屬層900係包含第一線路1001覆蓋導電凸塊200上方；及第二線路1002覆蓋抗延伸層302；及側面導電層1201電連接第一線路1101及第二線路1102。側面導電層1201即為切割前覆蓋通孔800的表面導體層900。由此可知，圖案化表面金屬層900可使積體電路元件102於各個不同的面向都具有對外的接點，藉此更加擴大積體電路元件102對外接觸之可利用面積。
參照圖13，顯示以第一實施例所示方法製作而成的封裝晶片1200的立體透視圖，所示虛線A－A’的剖面即為圖12。如圖13所示，封裝晶片1200有八個側面導電層1201，每個側面導體層1201係為半個圓形導通孔。
參照圖14，顯示依據本發明之第二實施例之封裝晶片1400的立體透視圖。第二實施例之方法與第一實施例之差別在於側面導電層1401所在位置及外形。如圖14所示，封裝晶片1400有四個側面導電層1401分別設置於封裝晶片1400的四個角落，每個側面導體層1401係為四分之一個圓形的導通孔。
參照圖15，顯示依據本發明之第三實施例之封裝晶片1500的立體透視圖。第三實施例之方法與第一實施例之差別在於側面導電層1501的外形。如圖15所示，封裝晶片1400有八個側面導電層1501，每個側面導體層1501係為被絕緣層700所環繞之完整的圓形導通孔。
以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請厚度專利範圍內。
100‧‧‧晶圓
102‧‧‧積體電路元件
104‧‧‧輸出/輸入接點
110‧‧‧保護層
200‧‧‧導電凸塊
300‧‧‧可延伸載板
300a‧‧‧第一面
300b‧‧‧第二面
301‧‧‧黏著層
302‧‧‧抗延伸層
400‧‧‧溝槽
500‧‧‧溝槽
501‧‧‧第一部分
502‧‧‧第二部分
600‧‧‧絕緣層
700‧‧‧絕緣層
800‧‧‧通孔
800a‧‧‧通孔內壁
900‧‧‧表面導體層
901‧‧‧導通孔
1001‧‧‧第一線路
1002‧‧‧第二線路
1101‧‧‧導電保護層
1200‧‧‧晶片
1201‧‧‧側面導電層
1400‧‧‧晶片
1401‧‧‧側面導電層
1500‧‧‧晶片
1501‧‧‧側面導電層
圖1至圖12係本發明第一實施例之製作過程的剖面圖；圖13係本發明第一實施例所示封裝晶片的立體透視圖；圖14係本發明第二實施例所示封裝晶片的立體透視圖；及圖15係本發明第三實施例所示封裝晶片的立體透視圖。
100‧‧‧晶圓
102‧‧‧積體電路元件
104‧‧‧輸出/輸入接點
110‧‧‧保護層
200‧‧‧導電凸塊
300‧‧‧可延伸載板
300a‧‧‧第一面
300b‧‧‧第二面
301‧‧‧黏著層
302‧‧‧抗延伸層
400‧‧‧溝槽
500‧‧‧溝槽
501‧‧‧第一部分
502‧‧‧第二部分
600‧‧‧絕緣層
700‧‧‧絕緣層
900‧‧‧表面導體層
901‧‧‧導通孔
1001‧‧‧第一線路
1002‧‧‧第二線路
1101‧‧‧導電保護層
1200‧‧‧晶片
1201‧‧‧側面導電層

Claims (18)

  1. 一種封裝積體電路元件的方法，包含：提供一晶圓，該晶圓具複數個積體電路元件；形成複數個導電凸塊於該複數個積體電路元件上；提供一可延伸載板，具有一第一面及一第二面相對於該第一面，該第一面承載該晶圓；形成一黏著層以連接該晶圓與該可延伸載板；形成複數個抗延伸層於該第二面上；形成複數個溝槽於該晶圓使該積體電路元件相互隔離；拉伸該可延伸載板以擴大該複數個溝槽；形成一絕緣層填充該複數個溝槽並覆蓋該複數個積體電路元件；形成複數個通孔穿透該絕緣層及該可延伸載板；形成一表面導體層覆蓋該通孔之內壁，該表面導體層係往外延伸以覆蓋該複數個導電凸塊及該複數個抗延伸層；及去除該表面導體層之一部分以形成一第一線路連接該複數個導電凸塊之頂表面上及一第二線路連接該複數個抗延伸層之頂表面。
  2. 如請求項1所述之方法，其中該可延伸載板具有一第一部分對應該溝槽及一第二部分不對應該溝槽，於該拉伸步驟時該第一部分的拉伸程度大於該第二部分之拉伸程度。
  3. 如請求項2所述之方法，其中該複數個抗延伸層係覆蓋該第二部分以抑制該第二部分於該拉伸步驟時向外延伸。
  4. 如請求項1所述之方法，更包含切斷該可延伸載板以使該複數個積體電路元件互不相連。
  5. 如請求項1所述之方法，其中該複數個抗延伸層係以導電材料製成。
  6. 如請求項1所述之方法，其中該可延伸載板之材質包含矽橡膠、聚亞醯胺、聚乙烯或聚丙烯。
  7. 如請求項1所述之方法，其中形成該複數個溝槽之方法包含利用切割刀、雷射切割、乾式蝕刻或濕式蝕刻。
  8. 如請求項1所述之方法，其中該絕緣層包含環氧樹脂、聚亞醯胺、苯并環丁烷、液晶高分子、或上述之各種組合。
  9. 如請求項1所述之方法，其中形成該複數個通孔之方法包含機械鑽孔或雷射鑽孔。
  10. 如請求項1所述之方法，其中該複數個導電凸塊之材質包含銅、銀、錫或導電高分子。
  11. 如請求項1所述之方法，其中該黏著層之材質包含丙烯酸酯、環氧樹脂、聚氨酯、或矽膠。
  12. 如請求項1所述之方法，其中形成該第一線路或該第二線路 之方法包含微影、印刷、電鍍或無電鍍。
  13. 一種積體電路元件之封裝結構，包含：一積體電路元件；一經延伸載板，具有一第一面及一第二面相對於該第一面，該第一面承載該積體電路元件；一抗延伸層設置於該二面上；一絕緣層包覆該積體電路元件；一導電凸塊電連接該積體電路元件，該導電凸塊嵌設於該絕緣層中；一黏著層連接該經延伸載板與該積體電路元件；一導通孔於該封裝結構之一側面，該導通孔穿透該絕緣層與該經延伸載板且電連接該導電凸塊與該抗延伸層；一第一線路位於該導電凸塊上方，該第一線路連接該導通孔與該導電凸塊；一第二線路覆蓋該抗延伸層，該第二線路連接該導通孔與該抗延伸層；及一表面金屬層覆蓋該絕緣層、該導電凸塊及該抗延伸層。
  14. 如請求項13所述之封裝結構，其中該抗延伸層係以導電材料製成。
  15. 如請求項13所述之封裝結構，其中該可延伸載板之材質包含矽橡膠、聚亞醯胺、聚乙烯或聚丙烯。
  16. 如請求項13所述之封裝結構，其中該絕緣層包含環氧樹脂、 聚亞醯胺、苯并環丁烷、液晶高分子、或上述之各種組合。
  17. 如請求項13所述之封裝結構，其中該複數個導電凸塊之材質包含銅、銀、錫或導電高分子。
  18. 如請求項20所述之封裝結構，其中該黏著層之材質包含丙烯酸酯、環氧樹脂、聚氨酯、或矽膠。
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