FR3093230B1 - Boîtier de puce électronique - Google Patents

Boîtier de puce électronique Download PDF

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Publication number
FR3093230B1
FR3093230B1 FR1902000A FR1902000A FR3093230B1 FR 3093230 B1 FR3093230 B1 FR 3093230B1 FR 1902000 A FR1902000 A FR 1902000A FR 1902000 A FR1902000 A FR 1902000A FR 3093230 B1 FR3093230 B1 FR 3093230B1
Authority
FR
France
Prior art keywords
electronic chip
chip box
substrate
conductive layer
insulating envelope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1902000A
Other languages
English (en)
Other versions
FR3093230A1 (fr
Inventor
Olivier Ory
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Tours SAS
Original Assignee
STMicroelectronics Tours SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Tours SAS filed Critical STMicroelectronics Tours SAS
Priority to FR1902000A priority Critical patent/FR3093230B1/fr
Priority to US16/802,325 priority patent/US11289391B2/en
Publication of FR3093230A1 publication Critical patent/FR3093230A1/fr
Application granted granted Critical
Publication of FR3093230B1 publication Critical patent/FR3093230B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Abstract

Boîtier de puce électronique La présente description concerne un dispositif (100) comprenant un substrat semiconducteur (102), une couche électriquement conductrice (104) recouvrant le substrat (102), et une enveloppe isolante (110), la couche conductrice étant en contact avec l'enveloppe isolante (110) du côté opposé au substrat. Figure pour l'abrégé : Fig. 3
FR1902000A 2019-02-27 2019-02-27 Boîtier de puce électronique Active FR3093230B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1902000A FR3093230B1 (fr) 2019-02-27 2019-02-27 Boîtier de puce électronique
US16/802,325 US11289391B2 (en) 2019-02-27 2020-02-26 Electronic chip package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1902000A FR3093230B1 (fr) 2019-02-27 2019-02-27 Boîtier de puce électronique
FR1902000 2019-02-27

Publications (2)

Publication Number Publication Date
FR3093230A1 FR3093230A1 (fr) 2020-08-28
FR3093230B1 true FR3093230B1 (fr) 2023-01-06

Family

ID=67441295

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1902000A Active FR3093230B1 (fr) 2019-02-27 2019-02-27 Boîtier de puce électronique

Country Status (2)

Country Link
US (1) US11289391B2 (fr)
FR (1) FR3093230B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019121722A (ja) * 2018-01-10 2019-07-22 株式会社ディスコ パッケージ基板の製造方法
FR3085575B1 (fr) 2018-09-03 2021-06-18 St Microelectronics Tours Sas Boitier de puce electronique
FR3125357A1 (fr) * 2021-07-16 2023-01-20 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US8203942B2 (en) 2006-07-14 2012-06-19 Raytheon Company Communications resource management
US20080242052A1 (en) * 2007-03-30 2008-10-02 Tao Feng Method of forming ultra thin chips of power devices
TWI387076B (zh) 2008-04-24 2013-02-21 Mutual Pak Technology Co Ltd 積體電路元件之封裝結構及其製造方法
WO2009156970A1 (fr) * 2008-06-26 2009-12-30 Nxp B.V. Produit à semi-conducteur conditionné et son procédé de fabrication
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
JP6096442B2 (ja) * 2012-09-10 2017-03-15 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
CN107533963A (zh) * 2015-04-20 2018-01-02 三菱电机株式会社 半导体装置的制造方法
KR102382635B1 (ko) * 2016-06-09 2022-04-05 매그나칩 반도체 유한회사 전력 반도체의 웨이퍼 레벨 칩 스케일 패키지 및 제조 방법
US10242926B2 (en) * 2016-06-29 2019-03-26 Alpha And Omega Semiconductor (Cayman) Ltd. Wafer level chip scale package structure and manufacturing method thereof
US10510741B2 (en) * 2016-10-06 2019-12-17 Semtech Corporation Transient voltage suppression diodes with reduced harmonics, and methods of making and using

Also Published As

Publication number Publication date
FR3093230A1 (fr) 2020-08-28
US11289391B2 (en) 2022-03-29
US20200273767A1 (en) 2020-08-27

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