CN1893046A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1893046A
CN1893046A CNA2005101253624A CN200510125362A CN1893046A CN 1893046 A CN1893046 A CN 1893046A CN A2005101253624 A CNA2005101253624 A CN A2005101253624A CN 200510125362 A CN200510125362 A CN 200510125362A CN 1893046 A CN1893046 A CN 1893046A
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wiring layer
electrode terminal
external electrode
cylindrical conductor
semiconductor device
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CN100421242C (zh
Inventor
松冈由博
今村和之
大岛政男
铃木贵志
泽田丰治
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Socionext Inc
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Fujitsu Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种半导体器件，其中布线层设置在半导体衬底上并沿着预设方向延伸。外接电极端子通过多个柱状导体设置在布线层上。柱状导体位于外接电极端子下方。柱状导体的排列密度沿着布线层的延伸方向而改变。

Description

半导体器件
技术领域
本发明涉及一种半导体器件，特别涉及一种半导体器件的外接电极端子(terminal)部分的连接结构。
背景技术
为获得微型化、高性能及低成本的电子设备，要求安装于电子设备上的半导体器件微型化、性能更高及成本更低。使用焊料凸点(solder bump)的结构为这种半导体器件的外接电极端子结构之一。因此，与半导体器件的这种微型化要求相对应，作为外接电极端子结构的焊料凸点也已经微型化并且其直径也减小。
另一方面，这种半导体器件中流动的电流量趋于增加，以获得半导体器件的更高运行速度。因此，流经一个焊料凸点的电流的电流密度增加，这导致构成焊料凸点的焊料和/或焊料凸点的基础金属层中产生电迁移。因此，在焊料凸点中产生孔洞的可能性较高。这种孔洞的存在可能使焊料凸点中电流路径的截面积减小，而导致电阻的增加。因而，孔洞的存在对半导体器件的运行速度产生不利影响，并导致半导体器件的可靠性下降。
作为焊料凸点的焊料，所谓的无铅焊料被广泛应用。这种无铅焊料被认为具有比传统含铅焊料低的抗电迁移性。
图1示出具有由焊料凸点构成的外接电极端子结构的半导体器件的焊料凸点部分的一个实例。
图1中，在形成于半导体衬底1的一个主表面上的铝(Al)布线层中，形成焊盘(terminal pad)部分2。经由钛(Ti)层3、铜(Cu)层4及镍(Ni)层5构成的基础金属层6，在焊盘部分2上设置由锡(Sn)-银(Ag)焊料形成的焊料凸点7。由表面保护膜限定焊盘部分2与基础金属层6相互接触的区域，该表面保护膜包含由氮化硅形成的钝化层8和覆盖该钝化层8的聚酰亚胺层9。
如图2所示，在上述外接电极端子结构中，电流可能聚集在布线层21从其延伸的部分，即在外接电极端子的基础金属层6连接至基础金属层6下面的布线层21的连接区域中的基础金属层6的端部。也就是说，流入焊料凸点7的电子(e-)在基础金属层6的端部聚集，从而在焊料凸点7和/或基础金属层6中可能发生电迁移。而导致在焊料凸点7内可能形成孔洞22。
应该注意，通过常规的半导体工艺在图1所示的半导体衬底1中形成有源元件和/或无源元件。此外，在半导体衬底1的主表面上设置所谓的多层布线结构，并且有源元件和/或无源元件彼此电连接。在布线层的中部或布线层的端部选择性设置用于外接的焊盘部分2。
以下专利文献公开了上述凸点结构。
专利文献1：日本特开平No.2000-195866
专利文献2：日本特开平No.2002-16065
如上所述，在半导体衬底的一个主表面上设置的布线层与外接电极端子的连接部分中，由于在外接电极端子与布线层之间流动的电流的局部聚集，导致在外接电极端子中和/或外接电极端子下面的基础金属层中可能发生电迁移。因此，在构成外接电极端子的凸点中产生孔洞。这将引起外接电极端子部分的电阻增加，并进而降低半导体器件的可靠性。
因此，在布线层与外接电极端子之间的连接部分中，需要获得不可能发生电流局部聚集的连接结构。
发明内容
本发明的概括目的是提供一种改进且实用的半导体器件，其中上述问题被消除。
本发明的更具体目的是提供一种连接结构，其中在布线层与外接电极端子之间的连接部分中不发生电流局部聚集。
为实现上述目的，按照本发明的一个方案，提供一种半导体器件，其包括：布线层，其设置在半导体衬底上并沿着预设方向延伸的；以及外接电极端子，其通过多个柱状导体设置在该布线层上，其中该柱状导体排列在由连接开口限定的区域中。
此外，按照本发明的另一方案，提供一种半导体器件，其包括：布线层，其设置在半导体衬底上并沿着预设方向延伸；以及外接电极端子，其通过多个柱状导体设置在该布线层上，其中该柱状导体位于该外接电极端子下方，并且该柱状导体的排列密度沿着该布线层的延伸方向而改变。
另外，按照本发明的另一方案，提供一种半导体器件，其包括：布线层，其经由第一绝缘膜设置在半导体衬底上并沿着预设方向延伸；外接电极端子，其经由第二绝缘膜设置在该布线层上；以及多个柱状导体，其设置在该第二绝缘膜中，其中该柱状导体位于该外接电极端子下方，并且该柱状导体的排列密度沿着该布线层的延伸方向而改变。
按照本发明，柱状导体使布线层与外接电极端子相互电连接。柱状导体可位于任何选择的位置，以防止布线层与外接电极端子之间流动的电流局部聚集，从而防止在外接电极端子和/或外接电极端子的基础金属层中产生电迁移。因此，在构成外接电极端子的焊料凸点中不会形成孔洞，因而外接电极端子部分的电阻不会增加，或者半导体器件的可靠性不会下降。
从以下联系附图的详细说明中更清楚了解本发明的其它目的及优点。
附图说明
图1为传统外接电极端子的截面图；
图2为传统外接电极端子的示意图；
图3为按照本发明的实施例的半导体器件的外接电极端子的截面图；
图4为以完全均匀的密度排列的柱状导体的示例的平面图；
图5为示出当如图4所示排列柱状导体时，电流密度随着与凸点中心的距离而变化的模拟结果的图表；
图6A和图6B为示出当如图4所示排列柱状导体时，电流密度随着与凸点中心的距离而变化的模拟结果的图表；
图7为以网格图案形成图4所示的布线的示例的平面图；
图8为柱状导体的密度朝电子流入的方向而逐渐降低的示例的平面图；
图9为示出当如图8所示排列柱状导体时，电流密度随着与凸点中心的距离而变化的模拟结果的图表；
图10A和图10B为示出当如图8所示排列柱状导体时，电流密度随着与凸点中心的距离而变化的模拟结果的图表；
图11为以网格图案形成图8所示的布线的示例的平面图；
图12为示出当电子从四个方向流入时柱状导体的设置的平面图；
图13A和图13B为示出当如图12所示排列柱状导体时，电流密度随着与凸点中心的距离而变化的模拟结果的图表。；
图14为以网格图案形成图12所示的布线的示例的平面图；
图15为分路(branched)布线层的平面图；
具体实施方式
将参照附图说明本发明的实施例。
图3示出按照本发明的实施例的半导体器件的焊料凸点部分的结构，该半导体器件具有由焊料凸点构成的外接电极端子作为该半导体器件的布线结构。
图3中，在形成于半导体衬底31的一个主表面上的铝(Al)布线层中，形成焊盘部分32。经由钛(Ti)层33、铜(Cu)层34及镍(Ni)层35构成的基础金属层36，在焊盘部分32上设置由锡(Sn)-银(Ag)焊料形成的焊料凸点37。
由表面保护膜限定焊盘部分32与基础金属层36相互接触的区域，该表面保护膜包含由氮化硅形成的钝化层38和覆盖该钝化层38的聚酰亚胺层39。通过覆盖钝化层38的聚酰亚胺层39限定连接开口40。
在本实施例中，在上述外接电极端子结构中，在焊盘部分32下方设置布线层41，其作为该焊盘部分的布线层。通过多个柱状导体43电连接及机械连接布线层41与焊盘部分32，所述柱状导体通过穿过层间绝缘膜42被选择性设置在与连接开口40限定的区域相对应的区域(正下方的区域)中。应该注意，布线层41由铝(Al)或铜(Cu)形成，而柱状导体(塞)43由钨(W)、铝(Al)或铜(Cu)形成。
按照上述结构，在布线层41与外接电极端子的焊料凸点37之间流动的电流流经多个柱状导体(钨塞)43而被分散。因而，在布线层与外接电极端子之间的连接部分中，在布线层41与外接电极端子之间流动的电流不会局部聚集。也就是说，在焊盘部分32与基础金属层36之间的接触部分中以及在基础金属层36与焊料凸点37之间的接触部分中流动的电流的电流密度均匀化，从而导致流入焊料凸点37的电子(e-)密度均匀化。因此，可防止在外接电极端子中和/或外接电极端子的基础金属层36中产生电迁移。
因此，在构成外接电极端子的焊料凸点中不会形成孔洞。因而外接电极端子部分的电阻不会增加，并且半导体器件的可靠性不会下降。
应该注意，通过常规的半导体工艺在图3所示的半导体衬底31中形成有源元件和/或无源元件。此外，在半导体衬底31的主表面上设置所谓的多层布线结构，从而使有源元件和/或无源元件彼此电连接(详细结构未示出)。
在布线层的中部或端部选择性设置用于外接的焊盘部分32。此外，基础金属层36不限于上述钛(Ti)层/铜(Cu)层/镍(Ni)层的叠层结构，根据需要其可以为具有焊料凸点37与焊盘部分32之间的屏蔽效应的所选择金属的组合。
此外，焊料凸点37并不限于锡(Sn)-银(Ag)焊料，可以为锡基合金(焊料)，例如锡(Sn)-铋(Bi)。
图4示出在由连接开口40限定的区域中，即层间连接区域中，以完全均匀的密度设置多个柱状导体(钨塞)43的状态。图4中，实黑方块表示的部分为柱状导体(钨塞)43。在实际器件中每个柱状导体(钨塞)43的截面通常为圆形。
图5示出在如图4所示的示例中，获得电流密度(单位：×105A/cm2)随着与焊料凸点37中心的距离而变化的模拟结果。图5中，实线表示当如图4所示排列柱状导体(钨塞)43时的电流密度，而虚线表示在图1所示的传统凸点连接结构的情况下的电流密度。应该注意，图5中纵轴代表电流密度，而横轴代表与焊料凸点37中心的距离(单位：μm)。
在模拟中，将焊料凸点37的连接部分的直径设置为50μm，约等于焊料凸点37的直径。此外，将电子的流动方向看作一个方向，设定为电子从图5横轴的距离为正值的一端流到距离为负值的一端。也就是说，图1和图2所示的焊料凸点7的右端对应于图5中的横轴的25μm的位置，而焊料凸点37的左端对应于-25μm。
由图5可见，焊料凸点37右端的电流密度值在由虚线所示的传统结构中达到1×105A/cm2，而在本实施例中该电流密度值约为0.5×105A/cm2，该值减少约一半。此外，在焊料凸点37左端，由实线所示的按照本实施例的布线结构的电流密度高于由虚线所示的传统凸点布线结构的电流密度。因此，可以确认，通过使用图4所示的布线结构，流经焊料凸点37的电流的电流密度完全均匀化。
然后，通过利用图4所示的柱状导体(钨塞)43的排列的模拟，获得在如下条件下的电流密度分布。
1)600mA的电流在X1方向流动的情况。
2)300mA的电流分别在X1方向和X2方向流动的情况。
3)300mA的电流分别在X1方向和Y1方向流动的情况。
4)200mA的电流分别在X1方向、Y1方向和X2方向流动的情况。
5)150mA的电流分别在X1方向、Y1方向、X2和Y2方向流动的情况。
在上述1)-5)的情况中，流经焊料凸点37的总电流设定为600mA。
图6A和图6B为示出模拟结果的图表。图6A示出X1-X2方向的电流密度分布，而图6B示出Y1-Y2方向的电流密度分布。
如图6A所示，在电流在X1方向和X2方向均流动的条件2)、4)及5)中，X1-X2方向的电流密度分布曲线接近平坦及对称，并且电流密度相对均匀。
此外，如图6B所示，在电流在Y1方向和Y2方向均流动的条件5)、和电流在Y1方向和Y2方向均不流动的条件1)及2)中，Y1-Y2方向的电流密度分布曲线接近平坦及对称，并且电流密度相对均匀。
根据图6A和图6B所示的模拟结果，发现在柱状导体43均匀排列的情况下，当电流在相反方向的其中一个方向流动时，在这一个方向的电流密度变大。
也就是说，发现当柱状导体43均匀设置时，如果将条件设置为电流在两个相反方向流动或者电流在两个相反方向不流动，则电流密度分布可相对均匀。
应该注意，通常由上述铜或铝形成图4所示的布线层41，并以平板形状形成布线层41。但是，也可以图7所示的网格图案形成布线层41。在这种情况下，在形成网格图案的布线上设置柱状导体43。
在本实施例中，通过根据图8所示的电流流动来设置柱状导体(钨塞)43可获得更大的效果。也就是说，通过将柱状导体(钨塞)43的排列设定为图8所示的排列，试图进一步使电流密度均匀化。柱状导体43位于外接电极端子下方，并且柱状导体43的密度沿着布线层41延伸的方向而变化。在图8所示的结构中，柱状导体43的排列密度为朝电子(e-)流入的方向(沿电流的流动方向)而逐渐降低。
图8中，当电子(e-)从右侧流入时，柱状导体43的密度从焊料凸点37的中心(即金属层36的中心)朝右侧逐渐降低。利用柱状导体43的这种排列，当电子e-从布线层41的一个方向(图8中右侧)流入时，由于在电子(e-)易于聚集之处，即在焊料凸点37的右侧(基础金属层的右侧)柱状导体43的排列密度小于包括中心部分的左侧部分，因此右侧的电流密度减小，从而使中心部分附近的电流密度增大。
图9示出当如图8所示排列柱状导体(钨塞)43时，电流的电流密度随着与焊料凸点37中心的距离而变化的模拟结果。图9中，实线表示当如图8所示排列柱状导体43时的电流密度，虚线表示图1所示的传统凸点连接结构的电流密度。
如图9所示，当如图8所示排列柱状导体43时的电流密度呈现如实线所示的凸曲线，该凸曲线在接近中心处(距离为0的位置)具有约0.42×105A/cm2的最大值，并在两侧减小。另一方面，传统布线结构中的焊料凸点37右侧的电流密度高达1×105A/cm2。对比最大电流密度，在如图8所示排列柱状导体43的情况下的最大电流密度比传统布线结构中的最大电流密度减少了约58％，从而使整个焊料凸点37的电流密度均匀化。
尽管图8所示的柱状导体43的排列为电子从一个方向流入的情况，然而如果电子从相对侧流入(从相反的两个方向流入)，柱状导体43的排列密度可朝相对侧减小，从而使电流密度均匀化。
然后，通过利用图8所示的柱状导体(钨塞)43的排列的模拟，获得如下条件下的电流密度分布。
1)600mA的电流在X1方向流动的情况。
2)300mA的电流分别在X1方向和X2方向流动的情况。
3)300mA的电流分别在X1方向和Y1方向流动的情况。
4)200mA的电流分别在X1方向、Y1方向和X2方向流动的情况。
5)150mA的电流分别在X1方向、Y1方向、X2和Y2方向流动的情况。
在上述1)-5)的情况中，经由基础金属层36流经焊料凸点37的总电流设定为600mA。
图10A和图10B为示出模拟结果的图表。图10A示出X1-X2方向的电流密度分布，而图10B示出Y1-Y2方向的电流密度分布。
如图10A所示，在电流在X1方向和X2方向均流动的条件2)、4)及5)中，X1方向这一侧的电流密度小于X2方向这一侧的电流密度，且最大电流密度出现在X2方向这一侧。另一方面，在电流仅在沿X1-X2方向的X1方向流动的条件1)和3)中，X1方向的电流密度减小为小于图6所示的情况1(柱状导体43以均匀分布的方式排列的情况)的电流密度，从而获得相对均匀的电流密度。
此外，如图10B所示，在电流在Y1方向和Y2方向均流动的条件5)、和电流在Y1方向和Y2方向均不流动的条件1)及2)中，Y1-Y2方向的电流密度分布曲线接近平坦及对称，并且电流密度相对均匀。
根据图10A和图10B所示的模拟结果，发现当电流在相反方向的其中一个方向流动时，在排列柱状导体43以使其密度在这一个方向逐渐降低的情况下，可抑制在这一个方向的电流密度增加。也就是说，在电流在相反方向的其中一个方向流动的情况下，当排列柱状导体43以使其排列密度在这一个方向逐渐降低时，电流密度分布可相对均匀。
应该注意，如上所述，通常由铜或铝形成图8所示的布线层41，并以平板形状形成布线层41。但是，也可以图11所示的网格图案形成布线层41。在这种情况下，在形成该网格图案的布线上设置柱状导体43。
此外，图12示出在电子从四个方向流入一个外接电极端子部分的情况下，即在四个方向延伸的布线层连接至外接电极端子部分的情况下，柱状导体(钨塞)43的排列。即使电子从四个方向流入，也可以沿着电子流动的四个方向，从与焊料凸点37的中心对应的位置逐渐降低柱状导体(钨塞)43的排列密度，使焊料凸点37中的电流密度均匀化。
然后，通过利用图12所示的柱状导体(钨塞)43的排列的模拟，获得如下条件下的电流密度分布。
1)600mA的电流在X1方向流动的情况。
2)300mA的电流分别在X1方向和X2方向流动的情况。
3)300mA的电流分别在X1方向和Y1方向流动的情况。
4)200mA的电流分别在X1方向、Y1方向和X2方向流动的情况。
5)150mA的电流分别在X1方向、Y1方向、X2和Y2方向流动的情况。
在上述1)-5)的情况中，经由基础金属层36流经焊料凸点37的总电流设定为600mA。
图13A和图13B为示出模拟结果的图表。图13A示出X1-X2方向的电流密度分布，而图13B示出Y1-Y2方向的电流密度分布。如图13A所示，在电流在X1方向和X2方向均流动的条件2)、4)及5)中，表示电流密度分布的曲线接近平坦及对称，并且电流密度相对均匀。
此外，如图13B所示，在电流在Y1方向和Y2方向均流动的条件5)、和电流在Y1方向和Y2方向均不流动的条件1)及2)中，Y1-Y2方向的电流密度分布曲线接近平坦及对称，并且电流密度相对均匀。
对比图13所示的模拟结果与图6所示的模拟结果，图13所示的电流密度分布的中心部分(接近距离为0的中心)在X1-X2方向和Y1-Y2方向均上升，这进一步使电流密度分布均匀化。
如上所述，无论从布线层41流入焊料凸点37的电子方向为一个方向或多个方向，均可以通过朝电流方向(即沿电流的流动方向)逐渐降低柱状导体(钨塞)43的排列密度，使焊料凸点37的连接部分中的电流密度均匀化。因此，可消除可能发生电迁移的高电流密度区，从而能够抑制由于电迁移引起的孔洞的产生。
应该注意，如上所述，通常由铜或铝形成图10所示的布线层41，并以平板状形成布线层41。但是，也可以图14所示的网格图案形成布线层41。在这种情况下，在形成该网格图案的布线上设置柱状导体43。
应该注意，尽管在上述实施例中柱状导体(钨塞)43设置在布线层41与焊盘部分32之间，但可在布线层41与焊盘部分32之间进一步设置金属层，以在该金属层与布线层41之间以及在该金属层与焊盘部分32之间设置柱状导体(钨塞)。按照这种设置，可进一步提高柱状导体(钨塞)的电流密度均匀化效果。
此外，尽管在上述实例中根据电流(电子)的流动方向确定柱状导体(钨塞)43的排列密度，但也可根据围绕焊料凸点37设置的布线层41的电位确定柱状导体(钨塞)43的排列密度。如果存在高电位部分和低电位部分，可通过对应于高电位部分逐渐降低排列密度而使电流密度均匀化。
此外，当流入连接至外接电极端子部分的布线层中的电流值较大时，可分散外接电极端子部分与布线层41之间的连接位置，也就是说，可以将布线层41分路，如图15所示，以在不同方向连接布线层41。
在这种情况下，除了将布线层分为多个分路之外，可以按照上述布线层41的多个连接位置(在此情况下为两个位置)设定柱状导体43的排列密度，从而进一步使焊料凸点37中的电流密度均匀化。因此，即使在处理较大电流密度的情况下，也可以显著抑制电迁移及由电迁移引起的孔洞的产生。
按照本发明的电流分散结构并不限于按照上述实施例的凸点型外接电极端子结构，可根据需要应用于其中可能产生电迁移及由电迁移引起的孔洞的任何电极结构。
本发明并不限于具体公开的实施例，在不偏离本发明的范围的前提下可做出改变及修改。

Claims (10)

1.一种半导体器件，包括：
布线层，其设置在半导体衬底上并沿着预设方向延伸；以及
外接电极端子，其通过多个柱状导体设置在所述布线层上，
其中，所述柱状导体排列在由连接开口限定的区域中。
2.一种半导体器件，包括：
布线层，其设置在半导体衬底上并沿着预设方向延伸；以及
外接电极端子，其通过多个柱状导体设置在所述布线层上，
其中，所述柱状导体位于所述外接电极端子下方，并且所述柱状导体的排列密度沿着所述布线层的延伸方向而改变。
3.一种半导体器件，包括：
布线层，其经由第一绝缘膜设置在半导体衬底上并沿着预设方向延伸；
外接电极端子，其经由第二绝缘膜设置在所述布线层上；以及
多个柱状导体，其设置在所述第二绝缘膜中，
其中，所述柱状导体位于所述外接电极端子下方，并且所述柱状导体的排列密度沿着所述布线层的延伸方向而改变。
4.如权利要求2或3所述的半导体器件，其中所述柱状导体设置在所述布线层与所述外接电极端子之间由连接开口限定的区域中。
5.如权利要求4所述的半导体器件，其中在所述布线层与所述外接电极端子之间由所述连接开口限定的区域中，所述柱状导体的排列密度沿着所述布线层的延伸方向而逐渐降低。
6.如权利要求1、2和3其中之一所述的半导体器件，其中所述布线层位于所述外接电极端子下方，并具有宽度大于其它部分的部分。
7.如权利要求1、2和3其中之一所述的半导体器件，其中所述外接电极端子由焊料凸点构成。
8.如权利要求7所述的半导体器件，其中所述外接电极端子由具有基础金属层的焊料凸点构成。
9.如权利要求1、2和3其中之一所述的半导体器件，其中所述柱状导体是由从钨、铝和铜构成的组中选出的材料制成。
10.如权利要求1所述的半导体器件，其中在所述布线层与所述外接电极端子之间由所述连接开口限定的区域中，所述柱状导体的排列密度沿着所述布线层的延伸方向而逐渐降低。
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