TWI314772B - Semiconductor device and unit equipped with the same - Google Patents

Semiconductor device and unit equipped with the same Download PDF

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Publication number
TWI314772B
TWI314772B TW095100934A TW95100934A TWI314772B TW I314772 B TWI314772 B TW I314772B TW 095100934 A TW095100934 A TW 095100934A TW 95100934 A TW95100934 A TW 95100934A TW I314772 B TWI314772 B TW I314772B
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Taiwan
Prior art keywords
columnar
semiconductor device
columnar portion
melting point
electrode
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Application number
TW095100934A
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English (en)
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TW200701411A (en
Inventor
Taizo Inoue
Kenzo Kitazaki
Hisashi Shigetani
Eiji Mugiya
Original Assignee
Taiyo Yuden Kk
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Application filed by Taiyo Yuden Kk filed Critical Taiyo Yuden Kk
Publication of TW200701411A publication Critical patent/TW200701411A/zh
Application granted granted Critical
Publication of TWI314772B publication Critical patent/TWI314772B/zh

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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04D—ROOF COVERINGS; SKY-LIGHTS; GUTTERS; ROOF-WORKING TOOLS
    • E04D1/00—Roof covering by making use of tiles, slates, shingles, or other small roofing elements
    • E04D1/34—Fastenings for attaching roof-covering elements to the supporting elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • E—FIXED CONSTRUCTIONS
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    • E04D1/00—Roof covering by making use of tiles, slates, shingles, or other small roofing elements
    • E04D1/02—Grooved or vaulted roofing elements
    • E04D1/06—Grooved or vaulted roofing elements of metal
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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1314772 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置及其安裝體，尤其關於對窄間 距化有效的半導體裝置及其安裝體。 【先前技術】 伴隨積體電路之小型化要求，半㈣裝置之結構以 csP(ChlpSizePackage，晶片尺寸封裝）為代表，以無限接 近裸B日之形式構成，藉由覆晶安裝將該半導體裝置接合於 配線基板之方法引人注目。 此處’藉由上述覆晶安裝實現半導體裝置與配線基板之 接合’係介以設置於構成該半導體裝置之半導體基板的主 面側之凸塊而進行，為實現以窄間距配置該凸塊，必須使 凸塊之體積減少，且避免鄰接之凸塊之間接觸。 然而’若使凸塊之體積減少，半導體基板與配線基板之 ]隙將減丨故曰在使接合穩定化、提高或確保連接可靠 性而於該間隙内填充樹脂之填底料難以實現。 因此，必須確保上述間隙，自先前研究出利用柱狀之金 屬柱之接合凸塊，作為已利用此種柱型接合凸塊之半導體 裝置及其安裝方法’眾所周知有例如下述文獻。 [專利文獻1]特開平5_1362〇1號公報 [專利文獻2]特開2002-313993號公報 [專利文獻3]美國專利第6,592,0 19號公報 此處’上述專利文獻1中’如該文獻之段落0020及圖1所 不’揭不有藉由焊接線法形成具備金屬柱之接合凸塊之方 104989.doc 1314772 法。 專利文獻2中，如該文獻之段落〇〇〇2〜〇〇〇7及圖18〜 圖24所不，揭示有藉由電鍍法形成金屬柱，並且於該金屬 柱之上面具備錫球之接合凸塊的形成方法。 ，專利文獻3中，如該文獻之第7行第16列〜第54列及第 s第W所不，揭不有藉由電鑛法於金屬才主及其上面形成 知錫層’將該焊錫層以原來的狀態接合於配線基板之方 法，與焊㈣暫時料球狀後接合於配線基 [發明所欲解決之問題] 开H上34專利文獻1所揭示之方法中，因必須於各端子 =，，故難以適用於輸入輸出端子數量較多之半導 體裝置，並且難以統—各 古 多接鬼之回度，難以適用於近年之 夕接腳乍間距型半導體裝置。 又，上述專利文獻2所揭示 。，及圖22所示，存在以下門題：中，如該文獻之段落 脂覆蓋之過程，故於形 ：金屬柱之上面由樹 圖23所示之狀態，並且二=必須研磨金屬柱且形成 構成半導體裝置，故柱埋設於樹脂之狀態下 …古確保填底料之間隙。 另—方面，上述專利文獻3所揭示之 金屬柱與烊錫層，該金卩電鍍形成 板，故於各凸塊之高度之狀態下安裳於配線基 非常優越。 b人確保填底料間隙之方面 然而’該專利文獻3中 如該文獻之第7行第47列〜第53 104989.doc 1314772 丨】斤丁提及有於對形成於金屬柱之上面之烊錫層進行暫 時圮焊亚形成錫球之情形時所產生的各種問題，為於金 柱上精度良好地形成锡球，必須進一步研究。 因此，本發明提供—種對於柱狀部之上面具備錫球之 '"凸塊之形成有效的半導體t置及#安裝體。 【發明内容】 :達到上述目的’請求項】之發明係一種半導體裝置，宜 個設置於半導體基板之柱狀電極，其特二 述柱狀電極具傭：包含導電材料之柱狀部，以及金屬球部 =屬球部由炫點低於上述柱狀部之導電材料而形成:且 a，將上餘”上\料奴體積設為 之上面的起伏部之體積設為柱狀七 A-Ey】.5之關係。 上迷柱狀電極具有 如上所述’根據柱狀部上面之面積 部的關係，而將金屬球部之體積控制在特定之；Γ 藉此與柱狀部之接觸面所產生之張力大於對=以：， 之重力，故藉由低熔點材料之迴 、、”’球部施加 防止該低溶點材料向柱狀部側面渗漏/成金屬球部時，可 此處，所謂形成於柱狀部之上面之、 狀部之側面成直角交叉之水平線延伸二指將= 分時，突出於該水平線之起伏部分。 。卩之上鳊部 藉由電鍍步驟自然地形成或有昧 匕之起伏部分有時 〜巧吋有忍地形，— 起伏部分之體積，可防止低炼 错由考慮該 U材枓向杜狀部側面參漏。 104989.doc 1314772 採取該等結構之情形時，上述柱狀部上面之面積β為盘低 炫點層接觸之部分的表面積。因此，若採取該等結構，低 炫點層與柱狀部之接觸面積可更大，故可使低溶 積增加。 m 其結果，因實現各柱狀電極之高度之均一化，故可提古 各電極接合於配線基板之精度’並且可實現確保填底料: 隙且盡可能的使電極間距狹窄化的結構。 另外，根據本方法，無須於柱狀部進行多餘的側面處理， ::成僅於該柱狀部之上面接合之金屬球部，故成為具備 結構簡單且可靠性較高之柱狀電極的半導體裝置。再者， f發明並非不於柱狀部實施側面處理，為更確實地防止低 t點材料向柱狀部側面之渗漏’亦可於柱狀部進行側面處 i里。 :處’ &好的是柱狀部以如銅般電阻較低但溶點之較高 :材：而形成’且金屬球部為進行焊錫較好的是由 :且與構成柱狀部之材料適應性較好之材料而形 者，柱狀部由鎳、銘、鈦等導電材料形成亦可。 上二;1求項2之發明如請求項1之半導體裝置，其中於將 上述各柱狀電極之間距 度設為〇時，上述各柱：電:為：將上述金屬球部之高 … 义谷枉狀電極具有_之關係。 ::’藉由進而規梅電極之間距 之關係’於將本半導體奘罢〜抽 又 裝置女裝於配線基板之時進行迴焊 時’可避免鄰接之柱狀電極間之接觸。 又口月求項3之發明係—種半導體裝置之安裝體，其將具 104989.doc 1314772 有複數個設置於半導體基板之柱狀電極的半導體裝置介以 該各柱狀電極而安裝於配線基板上，其特徵在於^述= 電極具備:包含導電材料之柱狀部，以及金屬球部，該金屬 球部由以熔點低於上述柱狀部之導電材料而形成，且接合 於上述柱狀部之上面，於將上述低熔點金屬層之體積設為 A，將上述柱狀部上面之面積設為B,將形成於上述柱狀邱 之上面的起伏部之體積設為E之時，上述柱狀電極罝^ 之關係。 。 如上所述，根據柱狀部上面之面積與形成於上面之起伏 部的關係將金屬球部之體積控制在特定之體積以下，藉此 於防止低熔點金屬|向柱狀部侧面滲漏之狀態下可將：導 體裝置安裝於配線基板，故可實現各柱狀電極之高度之均 化’其結果’可提高各電極接合於配線基板之精度，並 且可實現確保填底料間隙且盡可能的使電極間距狹窄化之 結構。 又叫求項4之發明如請求項3之半導體裝置之安裝體， 其中於上述半導體裝置與上述配線基板之間，具備於直接 連接於上述柱狀部之側面之狀態下填充的填底料。 错由如此構成’於較好地確保填底料間隙之狀態下可實 現半導體裝置之窄間距安裝。 又，請求項5之發明係一種半導體裝置，其具有複數個設 置於半導體基板之柱狀電極，其特徵在於上述柱狀電極具 備.包含導電材料之第i及第2柱狀部，以及金屬球部，該 金屬球部由炫點低於上述柱狀部之導電材料而形成，且接 104989.doc 10 1314772 合於上述第2柱狀部之上面，且上述第2柱狀部具有直徑小 於第1柱狀部的部位，並插入於上述金屬球部與上述第比 狀部之間。 士上所ϋ II由於直徑較大之柱狀部上配置直徑較小之 柱狀部’並且於直徑較小之柱狀部上設置金屬球部，於藉 由低嫁點材料之迴焊形成金屬球部時，即使該低炼點材料 較少亦可防止其向直徑較大之柱狀部之側面渗漏。 '、其結果，即便低熔點材料向直徑較小之柱狀部之側面滲 ' 口於直位敔大之柱狀部之上面滲漏停止，故可實現各 柱狀電極之高度之均-化，可提高各電極接合於配線基板 之精度’並且可實現確保填底料㈣且盡可能的使電極間 距狹窄化之結構。 另外根據本方法，無須於柱狀部進行多餘的側面處理， 可：：僅於該柱狀部上面接合之金屬球部，故成為具備結 構間早且可靠性較高之柱狀電極之半導體裝置。再者，本 I明並非不於枝狀部側面實施處理，Α更確實地防止低溶 點材料向柱狀部側面之滲漏’亦可於柱狀部進行側面處 理，防止向側面央、、P ^ + 止效果。處理可有效地獲得更可靠的渗漏防
， 士σ άΚ ， I 曰由以第1及第2之2個階段形成柱狀部，於電 鍍形成柱狀部時·^ ， 了减小SX置於抗蝕劑之開口部的縱橫尺寸 比故可形成以更_ μ @ ^ i m [發明之效果] 如上述說明，相 乂據本兔明’可形成具有僅於柱狀部之上 104989.doc 1314772 面接&之球部的柱狀電極。 【實施方式】 '下參照隨附圖式就本發明之實施形態加以詳細說 明。具去 + & 、 ’發明並非限定於下述將說明之實施形態亦可 進行適當變更。 圖係表不本發明之第丨實施形態之半導體裝置之安裂結 構的。面圖。如該圖所示，本安裝結構具有將半導體裝置 ^ 乂柱狀電極2 0安裝於配線基板3 〇之結構。 半導體裝置1G由包切之半導體基板12、於該半導體基 板12之主面側設有複數個之銘電極塾14、及於使該各電極 塾14部分暴露之狀態而形成之鈍化膜16而構成。 柱狀電極20由分別形成於上述各電極墊14之暴露部之包 含銅的柱狀部22、與形成於該柱狀部22上面之包含焊錫的 低炫點層24而構成。再者，較好的是該柱狀部形成為15_ 以上之高度。 配線基板30由内層有各種圖案之多層基板^、與形成於 該多層基板32之表面之配線圖案34而構成。 半導體裝置10與配線基板30之電性接合，藉由將位於柱 狀電極20之前端部之低熔點層24於配線圖案34上熔融而進 行，於該半導體裝置10與配線基板3〇之間，實施填底料4〇, 且保護各柱狀電極20之接合狀態。 圖2係表示第！實施形態之半導體裝置之第！製造步驟的 剖面圖。於製造本實施形態之半導體裝置之情形時，首先， 如該圖（a)所示，於形成有複數個積體電路之晶圓u之主面 J04989.doc 1314772 側形成複數個電極墊14，且於使該各電極墊丨4之中央部暴 露之狀態下形成鈍化膜1 6。 繼而’如該圖（b)所示，於純化膜16上塗敷光阻姓劑42， 其後，如該圖⑷所示’使之對應各電極塾14之暴露部且將 光阻蝕劑42感光，從而形成使各電極墊14暴露之開口部 44。此處各開口部14之寬度為小於鈍化膜16之開口寬度的 寬度，且，於未接觸純化膜16之端部的狀態下形成各開口 部1 4 〇 圖3係表示第1實施形態之半導體裝置之第2製造步驟的 剖面圖。如該圖（a)所示，利用前圖所示之開口部44於電極 塾14上形成柱狀部22。該柱狀部22之形成藉由鍍銅而進行。 繼而，如該圖（b)所示，利用前圖所示之開口部料於柱狀 部22之上面形成低熔點層24。該低熔點層24之形成藉由焊 錫電鍍而進行。 立圖4係表示第丨實施形態之半導體裝置之第3製造步驟的 J面圖如6亥圖（a)所示，去除前圖所示之光阻蝕劑42，得 到形成於晶BM3上之複數個柱狀電極2G。其後，如該圖⑻ 所不，將低熔點層24加熱熔融後將該低熔點層 =該加㈣融處理1由將晶圓13投人迴焊爐、且^ 疋-度及時間實施加熱處理而進行。再者，於迴焊之前先 塗敷氧化臈去除劑。 广係表示第丨實施形態之半導體裝置之第i安裝步驟的 剖：圖。如該圖所示’於將經過上述所說明之一系列步驟 所製造出之半導體裝置10安裝於配線基板30之情形時，使 1049B9.doc 1314772 該半導體裝置10之主面側面向配線基板30，並對位於柱狀 電極20之前端的球狀低熔點層24與設置於配線基板30上之 配線圖案進行位置對準。 圖6係表示第】實施形態之半導體裝置之第2安裝步驟的 剖面圖。如該圖所示，將前圖所示之步驟中位置已對準之 半導體裝置U)安裝於配線基板3〇上，其後，進行迴谭使低 熔點層24熔融固定於配線圖案34上。使各低熔點層以之固 定結束後，自該圖中之箭頭A所示之方向填充填底料樹脂， 得到圖1所示之結構。 圖7係表示第丨實施形態之半導體裝置之其他安裝結構的 剖面圖。如該圖所示，半導體裝置1〇若安裝於配線基板％ 後’柱狀部22之前端亦可係埋設於低熔點層以之狀態。 圖8係表示連接可靠性較低之柱狀電極之狀態的剖面 圖。如該圖（a)所示，若球狀低熔點層24於接觸於柱狀部Μ 之側面的狀態下形成，則各柱狀電極22之高度將產生不 均’其結果’如該圖（b)所示’產生未接合於配線圖案他 柱狀電極。 為防止出現該狀態，本實施形態中’於形成圖4所示之球 狀低熔點層24之步驟中，適用如下述說明之方法。 圖9係表示圖4所示之低熔點層之體積與柱狀部上面之面 積的關係之剖面圖。如該圖所示，於將各低熔點層％之體 積設為A，將各柱狀部22之上面之面積設為B時，以滿足 ΑΊ.3ΧΒΙ.5之關係的方式’於使用上述圖2及圖3所說明之 步称中’ If由調整開口部44之剖面面積與低炫點層24之電 I04989.doc 14 1314772 鑛量形成各柱狀電極20。 圖10係表示形成有柱狀電極之晶圓之迴焊步驟的側視 圖。如该圖所示，以上述關係形成各柱狀電極2 0後，將形 成有该各柱狀電極2〇之晶圓〗3之底面側载置於晶圓支撐台 52上，於使低熔點層24朝上之狀態下將該晶圓]3設 置於迴 焊爐5 0内。 而且，若於該狀態下進行低熔點層24之加熱，則已熔融 之低熔點層24向下之重力增加，根據與柱狀部22上面的面 積之關係控制低熔點層24之量，故於未接觸於柱狀部U之 側面的狀態下將低熔點層24加工為球狀。 圖U係表示藉由圖10之步驟形成之半導體裝置之電極結 構的剖面圖。如該圖所示，經過圖】〇之步驟的半導體裝^ 之各柱狀電極20,於將各低熔點層24之體積設為a，將各 柱狀部22之上面之面積設為叫，於滿足八^】5之關係 勺狀I下形成，且，於將各柱狀電極2〇之間距之丨設為匚， 將球狀低熔點層24之高声句· i n ,, 曰at阿度。又為D時，上述各柱狀電極星 之關係。 圖12係表示驗證低炫點層之體積a與枉狀部上面之 的關係時之結果的表格。如該圖所示，使八與B之值改 亀炫點層向柱狀部側面的滲漏之結果，Ν〇 ι〜3 中石“忍可於未向柱狀部側面參漏之狀態下形成球部，N" 之條件中產生向側面之滲漏。圖i3係表示 好的結構例之剖面圖。上述柱狀電極，為如該圖⑷所Γ 將柱狀部22之上面形成為山型的結構亦可，如該=所 104989.doc 1314772 不，具有起伏之結構亦可，如該圖⑷所示，於中央部且有 凸部之結構亦可’如該圖⑷所示，將上面部分變寬之結構 亦可，如該圖⑷所示，形成為彎曲型之結構亦可。 又，於如該圖⑷、（b)、⑷、⑷般上面具有山形、起伏、 凸部之情形時’若將該圖⑷、(b)、⑷、⑷所示之虛線『 以上之體積設w，則於滿；^^13心.5之關係的狀態下 形成。該虛線係將與柱狀部之側面成直角交叉之水平線延 伸至㈣狀部之上端部分之線’突出於該水平線之起伏部 分之體積為E。如此之起伏部分有時藉由電鍍步驟自然地形 成或有時有意地形成’ #由考慮該起伏部分之體積，可防 止低炫點材料向柱狀部側面之滲漏。 、知取該等結構之情形時，上述柱狀部22之上面之面積B， 為與低溶點層24接觸之部分的表面積。因&，若採取該等 結構，低溶點層24與柱狀部22之接觸面積將變大，故可/使 低炫點層之體積增加。 圖14係表示本發明之第2實施形態之半導體裝置之安裝 結構的剖面圖。如該圖所示，本安裝結構具有將半導體裝 置1〇介以柱狀電極20安裝於配線基板30之結構。 、 半導體裝置ίο由包含Si、GaAs、GaN、SiGe等之半導體 土板 & Π亥半導體基板12之主面側設置複數個之鋁電極 墊1 4及於使該各電極墊〗4部分暴露之狀態下而形 化膜1 6而構成。 純 柱狀電極20 且包含銅、錄、 由分別形成於上述各電極墊14之暴露部 導電膏等高熔點材料之柱狀部“^及^^ 104989.doc •16- 1314772 與形成於該柱狀部22之上面包含焊錫的低熔點層24而構 成。再者’較好的是該柱狀部形成為丨5μιη以上之高度。 此處，柱狀部22-1及22-2形成為直徑不同之形狀，該等堆 積後構成一個柱狀部。柱狀部22_2具有小於柱狀部22_丨的外 徑，於該外徑較小之面上設置低熔點層24。即，由複數段 構成柱狀。卩，且隨著自半導體基板〗2面向低熔點金屬層 24，柱狀部之直徑階段性地或連續地減小，藉此於由迴焊
等形成球狀低熔點金屬層24時，防止該低熔點金屬層以向 柱狀部之側面滲漏。 配線基板30由内層具有各種圖案之多層基板32、與形成 於該多層基板32之表面之配線圖案34而構成。 半導體裝置1G與配線基板3G之電性接合，藉由將位於柱 狀電極20之前端部之低熔點層24於配線圖案34上熔融而進 打，於該半導體裝置10與配線基板3〇之間，實施填底料40， 且保護各柱狀電極2 〇之接合狀態。 圖15係表示第2實施形態之半導體裝置之第i製造步驟的 剖面圖。於製造本實施形態之半導體裝置之情形時，首先， 如該圖_示’於形成有複數個積體電路之晶_之主面 側形成複數電極墊14，且於使該各電極墊14之中央部暴露 之狀態下形成鈍化膜1 6。 繼而，如該圖（b)所示 其後，如該圖（c)所示， 光阻钱劑4 2 -1感光，從 44。此處較好的是各開 ’於鈍化膜I 6上塗敷光阻蝕劑42-1， 使之對應各電極墊14之暴露部且將 而形成使各電極墊丨4暴露之開口部 口 °卩14之寬度為小於純化膜1 6之開 104989.doc 1314772 口寬度的寬度’且，於未接觸鈍化膜16之端部的狀態下形 成各開口部14’但各開口部14之寬度亦可大於鈍化膜⑽ 開口寬度。 圖16係表示第2實施形態之半導體裝置之第2製造步驟的 剖面圖。如該圖⑷所示’利用前圖所示之開口部44於電極 塾14上形成柱狀部22小該柱狀部22]之形成藉由鑛銅或鍍 錦或由印刷法填充導電膏而進行。 繼而，如6亥圖（b)所不，於光阻银劑44_}上塗敷光阻姓劑 2_2,其後，如該圖（C)所示，使之對應各柱狀部22-i之暴 路P將光阻|虫劑42-2感光’形成使各柱狀部22_丄暴露之開口 P此處各開口部44之寬度為小於各柱狀部22-1寬度之 寬度。 立圖Π係表示第2實施形態之半導體裝置之第3製造步驟的 ^面圖。如該圖⑷所示，利用前圖所示之開口部44於柱狀 邛22 1上形成柱狀部22_^該柱狀部之形成藉由鍍銅或 鍍鎳或由印刷法填充導電膏而進行。 塵而如δ亥圖（b)所示，利用同圖⑷所示之開口部44於柱 P 1之上面形成低熔點層24。該低熔點層24之形成藉 由焊錫電錢而進行。 圖18係表不第2實施形態之半導體裝置之第4製造步驟的 圖如6玄圖（a)所示，去除前圖所示之光阻蝕劑42-1及 2侍到形成於晶圓1 3上之複數個柱狀電極20。其後， 如該圖（b )戶 、 不’將低熔點層24加熱熔融後將該低熔點層24 :、'、泉狀°亥加熱熔融處理，藉由將晶圓丨3投入迴焊爐、 104989.doc 1314772 加熱處，行。再者 圖19係表示第2實施形態之半導體裝置之 剖面圖。如該圓所示，於將經過上述所說明之一系列步驟 所製造出之半導體裝置1G安裝於配線基板刊之情形時，使 。亥半導體褒置10之主面側面向配線基板3G，將位於柱狀電 極20-2之前端的球狀低炫點層24與設置於配線基板3〇上之 配線圖案進行位置對準。 圖2〇係表示第2實施形態之半導體裂置之第2安裳步驟的 剖面圖。如該圖所示，將前圖所示之步驟中位置已對準之 半導體裝置10安裝於配線基板3〇，其後，進行迴焊使低溶 點層24熔融固定於配線圖案34上。使各低熔點層24之固定 結束後’自該圖中之箭頭A所示之方向填充填底料樹脂得到 圖14所示之結構。 圖21係表示第2實施形態之半導體裳置之其他安裝結構 的剖面圖。如該圖所示’半導體裝置1()若安裝於配線基板 3〇後，柱狀部22之前端亦可係埋設於低熔點層24之狀態。 圖2 2係表示連接可靠性較低之柱狀電極之狀態的剖面 圖。如該圖（a)所示，若球狀低熔點層24於接觸於柱狀部22 之側面的狀態下形成，則各柱狀電極22之高度將產生不 均’其結果’如該圖（b)所示，產生未接合於配線圖案^之 柱狀電極。 為防止该狀悲之產生，本實施形態中，如圖丨8所示，於 柱狀部設置直徑不同之部位，於形成球狀低熔點層以之步 104989.doc •19- 1314772 驟中’於該低溶點廣24之炼融時至少防止該低炼點層以向 柱狀部2 0 -1之側面滲漏。 圖繼示使用台狀柱狀部之情形之實施形態的剖面 圖。如該圖所示，使用低炫點層24側之直徑較小而半導雕 基板=側之直徑較大的台狀柱狀部22構成柱狀電極= 可。藉由如此之結構’於低溶點層24之㈣時可防止該低 炼點層24向柱狀部2〇之側面之滲漏。 _ 圖24係表示設置於半導體基板之貫通通道之接合例的剖 面圖。如該圖所示，於貫通半導體基板12_2之表裏的貫通 通道51上形成電極塾14_2，且於該電極塾上接合低炫點層 Μ亦可。此處，貫通通道51由向形成於半導體基板12_2^ 内部的貫通孔填充銅或導電膏而形成。 圖25係表示設置於半導體基板上之電極圖案之接合例的 剖面圖。如該圖所示，形成於半導體基板之主面上之電極 墊14-2上形成配線圖案34，且於該配線圖案34上接合低熔 點層2 4亦可。 [產業上之可利用性] 根據本發明，可形成具有僅接合於柱狀部之上面之球狀 低熔點層的柱狀電極，故期待對要求更小型窄間距之半導 體裝置適用。 【圖式簡單說明】 圖1係表示本發明之第1實施形態之半導體裝置之安裝結 構的剖面圖。 圖2(a)、（b)、（c)係表示第！實施形態之半導體裝置之第1 104989.doc -20- 1314772 製造步驟的剖面圖。 製造 ° (b)係表示第1實施形態之半導體裝置之第 步驟的剖面圖。 3製造 • ( ) (b)A表示第1實施形態之半導體裝置之第 步驟的剖面圖。 圖5係表示第}實 剖面圖。 圖6係表示第1實 剖面圖。 施形態半導體裝置之第i之安裝步 驟的 施形態之半導體裝置之第2安裝步 驟的 圖7係表示第1實施形 剖面圖。 悲之半導體裝置之其他安裝結 構的 之狀態的 θ ( ) 係表示連接可靠性較低之柱狀電極 剖面圖。 表示圖4所示之低炫點層之體積與柱狀部上面之面 積之關係的剖面圖。 • 圖10係表示形成有柱狀電 圖。 極之晶圓之迴焊步 驟的側視 处構…丨示藉㈣iG之步驟而形成之半導體裝置之電極 、-'。構的剖面圖。 ％ ( 圖12係表不驗證低熔點層之體積A與柱狀部上 B的關係時之結果的表格。 面之面積 極之較好結構例的剖面圖。 明之第2實施形態之半導體裝置之安裝 图1 3(a)-(e)係表示柱狀電本 圖1 4係表示本發 結構的剖面圖。 104989.doc 1314772 圖l5(a)、（b)、（c)係表示第2實施形態之半導體裝置之第i 製造步驟的剖面圖。 圖16(a)、（b)、（匀係表示第2實施形態之半導體裝置之第2 製造步驟的剖面圖。 "" 圖17(a)、（b)係表示第2實施形態之半導體裝置之第3製造 步驟的剖面圖。 圖18(a)、（b)係表示關於第2實施形態之半導體裝置之第斗 製造步驟的剖面圖。 圖19係表示第2實施形態之半導體裝置之第1安裝步驟的 剖面圖。 圖2〇係表不第2實施形態之半導體裝置之第2安裝步驟的 剖面圖。 圖21係表示第2實施形態之半導體裝置之其他安裝结 的剖面圖。 ^、α 圖22(a)、（b)係表示連接可靠性較低之柱狀電極之狀態的 剖面圖。 圖圖23係表示使用台狀柱狀部之情形之實施形態的剖面 圖24係表示使用貫通通道之半導體基板安 圖。 g〜呐面 。係表示设置於半導體基板上之電極圖案接合例μ S圖。 饮σ例的剖 【主要元件符號說明】 1〇 半導體裝置 104989.doc -22- 1314772 12 半導體晶片 13 晶圓 14 電極墊 16 鈍化膜 20 22 24 30 32 34
柱狀電極 柱狀部 低熔點層 配線基板 多層基板 配線圖案 40 填底料 42 44 50 51
光阻蝕劑 開口部 迴焊爐 貫通通道 晶圓支撐台 104989.doc -23-

Claims (1)

  1. D ,14f ”00934號專利申請案 A1. 中文申請專利範圍替換本(98年2月） 十、申請專利範圍： 1. 一種半導體裝置，其具有複數個設置於半導體基板之柱 狀電極，其特徵在於 上述柱狀電極具備： 包含導電材料之柱狀部，以及 金屬球部，該金屬球部由熔點低於上述柱狀部之導電 材料而形成’且接合於上述柱狀部之上面， 於將上述金屬球部之體積設為A，將上述柱狀部上面之 面積設為B，將形成於上述柱狀部之上面的起伏部之體積 設為E之時，上述柱狀電極具有Α_Ε$13χΒΐ5之關係。 浚β求項1之半導體裝置，其中於將上述各柱狀電極之間 距的1/2設為C，將上述金屬球部之高度設為〇時，上述各 柱狀電極具有D^C之關係。 3. 一種半導體裝置之安裝體，其將具有複數個設置於半導 體基板之柱狀電極的半導體裝置介以該各柱狀電極而安 裝於配線基板上，其特徵在於 上述柱狀電極具備： 包含導電材料之柱狀部，以及 低炼點金屬層，其由炼點低於上述柱狀部之導電材料 而形成，且接合於上述柱狀部之上面， 於將上述㈣點金屬層之體積設為A，將上述柱狀部上 面之面積設為B，將形成於上述柱狀部之上面的起伏部之 體積設為E之時，上述柱狀電極具有Α_Ε^ΐ3χΒΐ5之關 係0 104989-980227.doc 13.14772
    4.如請求項3之半導體裝置之安裝體，其中於上述半導體裝 置與上述配線基板之間，具備於直接連接於上述柱狀部 之側面的狀態下填充的填底料。 5. —種半導體裝置，其具有： 半導體基板， 上述半導體基板上之電極墊，以及 配置於上述電極墊之至少一個柱狀電極，上述至少一 個柱狀電極具有： 至少包含第1導電材料之第丨柱狀部， 至少包含第2導電材料之第2柱狀部，以及 至少包含第3導電材料之金屬球部，該金屬球部具備 溶點低於上述第1導電材料之熔點及低於上述第2導電 材料之溶點’且接合於上述第2柱狀部之前端， 其中’上述第2柱狀部具有直徑小於上述第1柱狀部 的部位，並介於上述金屬球部與上述第1柱狀部之間。 6. 如請求項5之半導體裝置，其中上述第3導電材料係焊錫。 7. 如清求項5之半導體裝置，其中每一個上述第1及第2柱狀 部之上面及底面設計成俱備相同直徑。 8. ，明求項5之半導體裝置，其中上述第2柱狀部連接上述 弟1柱狀邛之底面具備小於上述第〗柱狀部之直徑的直 徑。 104989-980227.doc
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