CN1574319A - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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Publication number
CN1574319A
CN1574319A CNA03152608XA CN03152608A CN1574319A CN 1574319 A CN1574319 A CN 1574319A CN A03152608X A CNA03152608X A CN A03152608XA CN 03152608 A CN03152608 A CN 03152608A CN 1574319 A CN1574319 A CN 1574319A
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China
Prior art keywords
mentioned
pad
circuit arrangement
semiconductor element
weld pad
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CNA03152608XA
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English (en)
Inventor
高桥幸嗣
草野和久
坂本则明
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Application filed by Northeast Sanyo Semi-Conductive Co Ltd, Sanyo Electric Co Ltd filed Critical Northeast Sanyo Semi-Conductive Co Ltd
Publication of CN1574319A publication Critical patent/CN1574319A/zh
Pending legal-status Critical Current

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    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
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Abstract

一种电路装置。其在焊垫11的表面上形成第二电镀膜14B，以防止钎焊材料19从焊垫11流出。在焊垫11的表面的四周边缘部上，围着安装半导体元件13的区域设置第二电镀膜14B。在用钎焊材料19在焊垫11上安装半导体元件13的工序中，由于在熔化的钎焊材料19的上部放置半导体元件13，钎焊材料19从第一电镀膜14A流出，第二电镀膜14B作为阻止区域起防止流出的作用。因而，能够防止由于漫延的钎焊材料19造成焊垫11和结合垫12的短路。

Description

电路装置及其制造方法
技术领域
本发明涉及能防止连接半导体元件的焊料流出的电路装置及其制造方法。
背景技术
现在，因为安装在电子设备上的电路装置用在移动电话、手提式电子计算机等上，所以要求小型化、薄型化、轻量化。例如，若以半导体装置为例说明电路装置，作为一般的半导体装置，现在有用普通的传递模封装的插件型半导体装置。该半导体装置如图13安装在印刷基板PS上。
再有，该插件型半导体装置61是用树酯层63覆盖半导体芯片62的周围，并且从该树酯层63的侧部引出用于连接外部的导线端子64。但是，该插件型半导体装置61其导线端子64从树酯层63向外引出，全体尺寸增大，不满足小型化、薄型化及轻量化。为此各厂家竞争开发可以实现小型化、薄型化及轻量化的各种各样的构造。最近，开发了称作CSP(芯片尺寸插件)的与芯片尺寸相等的芯片规模CSP或者尺寸比芯片大一点的CSP。
图14表示采用玻璃环氧树酯基片65作为支持基片的、比芯片尺寸大一些的CSP66。在此，作为在玻璃树酯基片65上安装了晶体管芯片T的插件进行说明。
在该玻璃环氧树酯基片65的表面形成第一电极67、第二电极68以及焊垫69，在背面形成第一背面电极70和第二背面电极71。而且，通过通孔TH上述第一电极67和第一背面电极70、第二电极68和第二背面电极71电气连接。再有，在焊垫69上固定上述裸的晶体管芯片T，晶体管的发射极和第一电极67通过金属细线72连接，晶体管的基极和第二电极68通过金属细线72连接。再有，在玻璃环氧树酯基片65上设置树酯层73，使其覆盖晶体管芯片T。
上述CSP66尽管采用玻璃环氧树酯基片65，然而和芯片规模CSP不同，只是简单的从芯片T引出到外部连接用的背面电极70、71的结构，具有制造价格低的优点。再有，如图13所示，上述CSP66安装在印刷基片PS上。印刷基片PS上设置构成电路的电极、配线，电气连接固定着上述CSP66、插件型半导体装置61、芯片电阻CR或者芯片电容CC等。而且，用该印刷基片构成的电路安装在了各种各样的装置中。
但是，在上述那样的半导体装置中通过将涂布在焊垫69上的焊锡等钎焊材料熔化的回流工序固定晶体管T。因而，当将晶体管T放置在熔化的焊锡上时，焊锡从焊垫69上流出，而发生焊垫69和其他的电极短路的问题。
再有，为了防止从焊垫69流出的钎焊材料流到第二电极68上，要使焊垫69和第二电极68隔开间隙，这导致了装置整体的大型化。
发明内容
本发明鉴于这样的问题而产生。本发明的主要目的是提供一种电路装置，其在用钎焊材料在焊垫上安装半导体元件时，能防止钎焊材料从焊垫上流出。
本发明的电路装置具有：焊垫，其通过钎焊材料安装半导体元件；结合垫，其接近上述焊垫设置；电镀膜，其形成在上述焊垫和上述结合垫的表面上。还在上述焊垫的放置上述半导体元件的第一电镀膜的周围离开间隙，设置用于防止上述钎焊材料流出的第二电镀膜，用两个电镀膜的间隙防止从上述第一电镀膜溢流的上述钎焊材料流出。
再有，本发明的电路装置在上述第一电镀膜的两侧面设置凸部，使上述钎焊材料从上述凸部流出而在周围漫延。
再有，本发明的电路装置通过用上述凸部使上述钎焊材料在周围漫延，维持上述半导体元件平行。
再有，本发明的上述半导体装置是IC芯片。
再有，本发明的上述半导体元件通过金属细线和所希望的上述结合垫电气连接。
再有，本发明的电路装置具有：焊垫，其安装半导体元件；第一结合垫，其接近上述焊垫设置且和上述焊垫电气绝缘；第二结合垫，其接近上述焊垫设置且和上述焊垫形成一体；绝缘性树酯，其使上述焊垫、上述第一结合垫和上述第二结合垫的背面露出，而密封上述半导体元件、上述焊垫、上述第一结合垫和上述第二结合垫。通过上述第二结合垫介于窄幅形成的配线部连接上述焊垫，增大上述第二结合垫和上述绝缘性树酯的接触面积，而强化了结合垫和上述绝缘性树酯的结合。
再有，本发明的上述第一结合垫沿着上述焊垫的相对的两条边设置多个。
再有，本发明的上述第二结合垫沿着上述焊垫的相对的另外两条边设置多个。
再有，本发明的上述半导体元件通过金属细线与所希望的上述第一结合垫和第二结合垫电气连接。
再有，本发明的上述第一结合垫和上述第二结合垫形成圆形。
再有，本发明的电路装置具有：焊垫，其安装半导体元件；结合垫，其围着上述焊垫而设置；第一外部电极，其设在上述焊垫的背面；第二外部电极，其设在上述结合垫的背面；抗蚀层，其在对应两种外部电极的部分形成开口且覆盖背面。使在对应上述第二外部电极的地方设置的上述抗蚀层的开口部比上述结合垫还大，通过由上述开口部露出的上述结合垫的背面的濡润性和涂布在上述结合垫的背面上的作为外部电极材料的钎焊材料的量限制上述第二外部电极的大小。
再有，本发明通过上述抗蚀层的开口部限制上述第一外部电极的位置和大小。
再有，本发明的电路装置制造方法具有：准备导电箔工序；形成焊垫和结合垫工序，其在上述导电箔上形成比导电箔厚度浅的分离槽而构成多个电路装置部；形成电镀膜工序，其在与预定要连接半导体元件的区域相对应的上述焊垫的表面形成第一电镀膜的同时围着上述区域形成第二电镀膜；连接工序，其在上述第一电镀膜上通过钎焊材料连接半导体元件；导线结合工序，其进行上述半导体元件和所希望的上述导电图形的导线结合；共同成型工序，其用绝缘树酯覆盖上述半导体元件并充填上述分离槽；除去工序，其除去上述导电箔的背面直到露出所述绝缘树酯；分隔工序，其通过切割上述绝缘树酯，分隔成各电路装置。
再有，本发明通过在上述第一电镀膜的周端部设置凸部，使上述钎焊材料从上述凸部流出，维持上述半导体元件平行。
再有，本发明通过使从上述凸部流出的上述钎焊材料沿着上述第二电镀膜流动，防止上述钎焊材料从上述焊垫表面流出。
再有，本发明的上述钎焊材料是锡焊料或者银焊糊。
附图说明
图1(A)是说明本发明的电路装置的平面图、图1(B)是剖面图；
图2(A)是说明本发明的电路装置的平面图、图2(B)是背面图、图2C是剖面图；
图3(A)是说明本发明的电路装置的平面图、图3(B)是剖面图；
图4(A)是说明本发明的电路装置的制造方法的剖面图、图4(B)是平面图；
图5是说明本发明的电路装置的制造方法的剖面图；
图6(A)是说明本发明的电路装置的制造方法的剖面图、图6(B)是平面图；
图7(A)是说明本发明的电路装置的制造方法的剖面图、图7(B)是平面图；
图8(A)是说明本发明的电路装置的制造方法的剖面图、图8(B)是平面图；
图9(A)是说明本发明的电路装置的制造方法的剖面图、图9(B)是平面图；
图10(A)是说明本发明的电路装置的制造方法的剖面图、图10(B)是平面图；
图11(A)是说明本发明的电路装置的制造方法的剖面图、图11(B)是平面图；
图12(A)是说明本发明的电路装置的制造方法的剖面图、图12(B)是剖面图、图12(C)是平面图；
图13是说明现有的电路装置的剖面图；
图14是说明现有的电路装置的剖面图。
具体实施方式
(说明电路装置10的结构的第一实施例)
参照图1，说明本发明的电路装置10的构成等。图1(A)是电路装置10的平面图，图1(B)是电路装置10的剖面图。
参照图1(A)和图1(B)，电路装置10具有如下的结构，即，具有：焊垫11，其通过钎焊材料19安装半导体元件13；结合垫12，其接近焊垫11设置；电镀膜，其形成在焊垫11和结合垫12的表面上。在焊垫11放置半导体元件13的第一电镀膜14A的周围离开间隙设置用于防止钎焊材料19流出的第二电镀膜14B，用两个电镀膜的间隙防止从第一电镀膜14A溢流的钎焊材料19流出。下面，说明这样的各构成要素。
焊垫11是安装半导体元件13的导电图模，由铜箔等金属制成，露出背面而埋入绝缘性树酯16内。而且，使焊垫11的平面要比安装的半导体元件13大一些，在其周围形成第二电镀膜14B。在图1(A)，在中央部形成焊垫11，通过钎焊材料19安装在由IC芯片制成的半导体元件13，再有，在与安装半导体元件13的范围相对应的焊垫11的表面用Ag等形成第一电镀膜14A。
结合垫12是结合细金属线15的导电图模，露出背面而埋入绝缘性树酯16内。在此，包围在装置的中央部形成的焊垫11形成多个圆形的结合垫12。在图1(A)，在焊垫11的左右两侧形成的结合垫12A电气独立设置。在焊垫11的上下两侧形成的结合垫12B形成和焊垫11电气连接。而且，为了提高结合的细金属线的连接性，在结合垫12的表面用Ag等形成第三电镀膜14C。
通过钎焊材料19在焊垫11的表面安装半导体元件13。在此，通过钎焊材料19安装在半导体元件中也是比较大的IC芯片。而且，通过细金属线15电气连接在半导体元件13的表面形成的电极和结合垫12。再有，和焊垫11电气连接的结合垫12也通过细金属线15和半导体元件13电气连接。在此，可以使用焊锡或银焊糊等导电性连接材料作为钎焊材料。
绝缘性树酯16露出焊垫11和结合垫12的背面而封住全体。再有，在焊垫11表面上形成的槽14中也充填着绝缘性树酯16。在此，封住半导体元件13、金属细线15、焊垫11和结合垫12。作为绝缘树酯的材料可以采用通过传递模成形的热硬性树酯或者通过注塑成形的热塑性树酯。
钎焊材料19是焊锡或银焊糊等导电性的焊糊，具有连接半导体元件1 3和焊垫11的作用。由于钎焊材料19是导电性材料，所以半导体元件13的背面和焊垫11形成电气连接。再有，在焊垫11的上下两侧形成的结合垫12B和焊垫11电气连接。因而，通过用细金属线15连接半导体元件13的电极和结合垫12B，就能电气连接在半导体元件13的表面上形成的电路和半导体元件13的背面。
参照图2(B)说明在焊垫11和结合垫12的表面上形成的电镀膜。在图2(A)平面图，只表示焊垫11、结合垫12和在两者的表面上形成的电镀膜，省略图示半导体元件13和细金属线15。在焊垫11的表面上形成对应放置半导体元件13的范围的第一电镀膜14A以及围着第一电镀膜14A离开间隙设置的第二电镀膜14B。而且，在结合垫12的表面上设置第三电镀膜14C。可以采用银、镍或者金等作为上述的电镀膜14的材料。
对应放置半导体元件13的范围而设置第一电镀膜14A，形成其形状和大小与半导体元件13相同。再有，在第一电镀膜14A的相对边的中央部附近设置凸部14D，其目的是在通过钎焊材料安装半导体元件13时，使钎焊材料19左右均等地流出。凸部14D是使第一电镀膜14A的周围边缘部的一部分变形的地方，在此，形成凸部14D向外侧突出。
第二电镀膜14B围着并离开上述第一电镀膜14A间隙，形成在焊垫11的四周边缘部上。当通过钎焊材料19安装半导体元件13时，钎焊材料19从设在第一电镀膜14A上的凸部14D附近溢流。而且，通过由第二电镀膜14B形成的台阶防止钎焊材料19从焊垫11流出。再有，因为第二电镀膜14B是对钎焊材料濡润性良好的材料，所以从第一电镀膜14A溢流到达第二电镀膜14B的钎焊材料19沿着第二电镀膜14B的内侧流动。
本发明通过第二结合垫12B介于窄幅形成的配线部20和焊垫11连接，使第二结合垫12B和绝缘性树酯16的接触面积增大，强化了结合垫12A和绝缘树酯16的结合。具体来说，如上所述，因为焊垫1 1和第二结合垫12B电气连接，所以也能形成使两者一体化的矩形的结合面。然而，在本发明第二结合垫12B形成圆形，介于窄幅形成的配线部20和矩形的焊垫连成一体。通过这样的构成能增大与第二结合垫12B配线的侧面的面积，增大与绝缘树酯16接触的面积。从而，形成非常牢固的通过配线部20连成一体的结合垫12B与焊垫11和绝缘树酯16的连接。因此，能防止结合垫以及焊垫11从绝缘树酯16剥离开。
参照图2(B)(C)说明在电路装置10的背面形成的外部电极17。本发明的电路装置10具有：焊垫11，其安装半导体元件13；结合垫12，其围着焊垫11而设置；第一外部电极17A，其设在焊垫11的背面；第二外部电极17B，其设在结合垫12的背面；抗蚀层，其在对应两外部电极的部分形成开口21且覆盖背面。使在对应第二外部电极17B的地方设置的抗蚀层1 8的开口部21A比结合垫12还大，通过由开口部21露出的结合垫12的背面的濡润性和涂布在结合垫12背面的作为外部电极17的材料的钎焊材料的量限制第二外部电极17B的大小。以下，说明这样的构成要素。再有，关于参照图1进行说明的构成要素是相同的，因而其说明省略。
在焊垫11的背面成矩阵状地设置多个第一外部电极17A，其由锡焊等钎焊材料形成。再有，第一外部电极17A的位置及大小由在抗蚀层18形成的第一开口部21A限制。因而，第一外部电极17A的平面的大小和设置在抗蚀层18上的第一开口部21A相同。
第二外部电极17B设置在围着焊垫11设置的结合垫12的背面上。再有，由于结合垫12从抗蚀层18的第二开口部21B露出，因而第二外部电极17B在第二开口部21B的内部形成。在此，设在抗蚀层18上的第二开口部21B比从开口部露出的结合垫12B的背面还大。因而，结合垫12和绝缘树酯16的背面从第二开口部21B露出。由此，在形成外部电极17的工序，当在结合垫12上涂布钎焊材料而熔化时，只在对焊料濡润性良好的结合垫12的部分上形成外部电极17B。从而，第二外部电极17B的平面形状形成和结合垫12相同的形状。
配线部20是连接结合垫12和焊垫11的部分，形成其宽度比结合垫12的直径窄。通过这样窄幅形成配线部20，能增大形成一体的焊垫11和结合垫12的侧面部的面积。再有，配线部20的一部分从形成比结合垫12还大的第二开口部21露出，通过形成这样的窄幅，能使露出部分的面积最小。在形成第二外部电极17B时，在露出的配线部20上也浸润了熔化的钎焊材料，因而，也能认为第二外部电极17B的形状从圆形变形了。在此，通过窄幅地形成配线部20，通过配线部20上浸润焊料可以使第二外部电极17B的变形为最小。
在电路装置10的背面矩阵状等间距配置着上述第一外部电极17A和第二外部电极17B。而且，形成各个外部电极17大小基本相同。因而，由于通过外部电极17在主基片等安装基片上安装电路装置10，故能降低作用在各外部电极17上的应力。
参照图3说明在电路装置的背面形成的外部电极17。外部电极17在围着焊垫11而设置的结合垫12的背面形成，再有，在焊垫11的背面也设置了多个外部电极。因而，在电路装置10背面的全范围内矩阵状等间距地设置了多个外部电极17。这样，通过外部电极17在主基片等安装基片上安装了电路装置10时，能减小作用在外部电极17上的应力。
参照图3(B)，在焊垫11的背面形成的外部电极17的和大小通过抗蚀层18的开口部限制。而且，在结合垫12的背面形成的外部电极17的位置和大小由结合垫12的背面限制。作为结合垫12的材料的铜等金属是浸润性良好的材料，通过该浸润性限制外部电极17的位置和大小。这样，通过利用结合垫12的浸润性限制在结合垫12的背面形成的外部电极17的位置和大小，在抗蚀层18的开口部的位置偏移时也能形成精度良好的外部电极17。
本发明从在焊垫11的放置半导体元件13的区域形成的第一电镀膜14A离开间隔而围着第一电镀膜14A设置第二电镀膜14B。当在第一电镀膜14A上通过钎焊材料19安装半导体元件13时，通过半导体元件的重量等使熔化的钎焊材料19从第一电镀膜14A流出。而且，通过围着第一电镀膜14A而设置的第二电镀膜形成台阶，该台阶作为阻止区域起防止焊料19流出的作用。从而，从第一电镀膜14A流出的钎焊材料19滞留在第一电镀膜14A和第二电镀膜14B之间形成的间隙中。因而，能防止通过安装半导体元件13而从第一电镀膜14A溢流的钎焊材料19从焊垫11流出。因此，能防止由于流出的钎焊材料19造成焊垫11和结合垫12短路。
再有，本发明在第一电镀膜14A的两侧面上设凹部14D。这样，在使用熔化的钎焊材料19安装半导体元件13时，能使钎焊材料19从两侧面均等地流出。因而，能防止由于钎焊材料19流偏造成的半导体元件13的倾斜。再有，能使钎焊材料19的厚度均匀。
更进一步说明设置第二电镀膜14B的优点。钎焊材料19是使用分配器等供给钎焊材料的机械涂布在焊垫11的表面，由该定量分料器规定供给的钎焊材料20的最小涂布量。因而，在定量分料器的最小涂布量比为在焊垫11上安装半导体元件13所必要的钎焊材料19的量多时，会担心钎焊材料19从焊垫11的表面流出。因此，通过设置第二电镀膜14B能防止钎焊材料19流出。
(说明电路装置10的制造方法的第二实施例)
在本实施例，说明电路装置10的制造方法。在本实施例，电路装置10用如下的工序制造，即：准备导电箔40的工序；形成焊垫11和结合垫12的工序，其在导电箔40上形成比导电箔40的厚度浅的分离槽16而构成多个电路装置部45；形成电镀膜工序，其在与预定要连接半导体元件13的区域相对应的焊垫11的表面上形成第一电镀膜14的同时围着上述区域形成第二电镀膜14B；连接工序，其在第一电镀膜14A上通过钎焊材料19连接半导体元件13；导线结合工序，其进行半导体元件13和所希望的结合垫12的导线结合；共同成型工序，其用绝缘树酯16覆盖半导体元件13并充填分离槽16；除去工序，其除去导电箔40的背面直到露出绝缘树酯16；分隔工序，其通过切割绝缘树酯16分隔成各电路装置。以下，参照图4～图12说明本发明的各工序。
如图4～图6所示，本发明的第一工序是准备导电箔40形成焊垫11和结合垫12，即在导电箔40上形成比其厚度浅的分离槽16而构成多个电路装置部45。
在本工序，首先如图4(A)，准备片状的导电箔40。该导电箔40要考虑钎焊材料的附着性、结合性、电镀性而选择其材料。作为材料采用以Cu为主材料的导电箔、以A1为主材料的导电箔或者由Fe-Ni等的合金形成的导电箔等。
导电箔的厚度要考虑以后的蚀刻工序，以10μm～300μm程度为理想，然而，在300μm以上或10μm以下也基本可以，如后所述，只要能形成比导电箔40的厚度浅的分离槽16就可以。
再有，片状的导电箔40可以按规定的宽度、准备成例如45mm卷成筒状，再运送到后面的各工序，也可以准备或按规定的大小切成短册状的导电箔40，再运送到后述的各工序。
具体地如图4(B)所示，在短册状的导电箔40上离开间隔并列着四～五个形成多个电路装置部45的方块42。在各方块42间设置间隙43，用来吸收在成型工序中由于加热处理而产生的导电箔40的应力。再有，在导电箔40的上下周边以规定间隔设置指示孔44，用于决定在各工序的位置。
然后，形成导电图模。首先，如图5所示，在导电箔40上形成耐光保护层(耐蚀刻掩膜)PR，在耐光保护层PR上制图模，露出除成为导电图模51的区域之外的导电箔40。而且，如图6(A)所示，有选择地蚀刻导电箔40。在此，导电图模5 1形成各电路装置部45的焊垫11和结合垫12。
图6(B)中表示形成焊垫11和结合垫12的导电图模51。本图对应放大的在图4(B)表示的一个方块42。一个影线部分是一个电路装置部45，在一个方块42中两行两列矩阵状地配列着多个电路装置45，每个电路装置45上设置相同的导电图模51。在各方块的四周上设框状的图模46，在图46的内侧离开一点间隔设置切割时的定位标记47。框状的图模46用于和成型模具嵌合，并且在导电箔40的背面蚀刻后具有增强绝缘树酯16的作用。再有，在各电路装置部，在焊垫11的上下两侧形成的结合垫12和焊垫11形成一体化，两者也电连接。
如图7所示，本发明的第二工序是在与预定连接半导体元件13的区域相对应的焊垫11的表面上形成第一电镀膜14A的同时围着上述区域形成第二电镀膜14B。再有，在本工序，在结合垫12的表面形成第三电镀膜14C。
在本工序，首先，在除去预定要形成第一电镀膜14A、第一电镀膜14B和第三电镀膜14C的地方形成抗蚀层。而且，通过电场电镀法或者非电场电镀法形成电镀膜。在此可以采用银、镍或者金等作为上述电镀膜的材料。再有，在形成矩形的第一电镀膜14A的两侧面形成凸部14D。
本发明的第三工序，如图8和图9所示，是在第一电镀膜14A上通过钎焊材料19连接半导体元件13。
参照图8(A)，在焊垫11的表面上形成的第一电镀膜14A上，通过钎焊材料19安装半导体元件13。在此，作为钎焊材料19使用焊锡或者银焊糊等的导电性糊。由于在本工序钎焊材料19是熔化的状态，因此当在钎焊材料19的上部放置半导体元件13时，由于半导体元件13的重量等钎焊材料19从第一电镀膜14A溢流。在此，围着放置半导体元件13的区域，由于在焊垫11的四周边缘部上形成第二电镀膜14B，因此漫延的钎焊材料19不会从焊垫11流出。已到达第二电镀膜14B的钎焊材料19积存在第一电镀膜14A和第二电镀14B之间的间隙内。因而，第二电镀膜14B作为阻止区域起着阻止钎焊材料19流出的作用。因而，钎焊材料19不会从焊垫11的表面溢流，从而能防止焊垫11和结合垫12短路。
参照图9说明设置在第一电镀膜14A两侧面的凸部14D的作用。图9(A)是表示在本工序钎焊材料19从第一电镀膜14A流出的状态的剖面图，图9(B)是其平面图。
参照图9(A)和图9(B)，由于在熔化的钎焊材料19A的上部安装半导体元件13，钎焊材料19从第一电镀膜14A溢流。在此，由于在第一电镀膜14A的两侧面(这里是左右的两侧面)形成凸部14D，因此钎焊材料19先从形成凸部14D的部分流出，并且左右均等地没有偏移地流出。由此可见，钎焊材料19保持规定的厚度，并且通过钎焊材料19连接着的半导体元件13保持水平安装。通过使焊料19形成规定厚度，能提高半导体元件13的散热性。通过平行地安装半导体元件13，能利用半导体元件13表面的光反射正确地判断其位置。因此，能稳定地进行位置判断之后的金属结合工序。
如图10所示，本发明的第四工序是进行半导体元件13和所希望的结合垫12的金属线结合。
具体地，是将安装在各电路装置部45上的半导体元件13的电极和所希望的结合垫12通过热压接的球式结合法以及超声波的湿式结合法汇集一起进行金属线结合。
在本工序，利用照射在半导体元件13的表面的光的反射，进行位置判断；由于在前工序相对导电箔40平行地安装了半导体元件13，因此能正确地进行半导体元件13的位置判断。
如图11所示，本发明的第五工序是用绝缘树酯16覆盖半导体元件13并填充分离槽16和槽14的共同成型工序。
如图11(A)所示，在本工序，绝缘树酯16完全地覆盖了半导体元件13、多个焊垫11和结合垫12，在分离槽16和槽14内充填绝缘树酯16，并与分离槽41嵌合牢固地结合。而且，通过绝缘树酯16支持焊垫11和结合垫12。
再有，由于在本工序能通过传递模成型法、注塑成型法或者浇注法实现。作为树酯材料，环氧树酯等热硬性树酯用传递模成型法实现，聚酰亚胺、聚苯硫化物等热塑性树酯用注塑成型法实现。
再有，在本工序进行传递模成型或者注塑成型时，如图11(B)中所示地各方块42都将电路装置部63收放在一个共同的成型模具内，每个方块用一种绝缘树酯16进行共同成型。因此，和现在的传递模成型等那样地将各电路装置部单独地成型的方法相比，可实现大幅度减少树酯使用量。
本工序的特征在于，直到覆盖绝缘树酯16，作为导电图模51的导电箔40成为支持基片。现有技术是采用原本就不必要的支持基片形成导电图模，然而，在本发明成为支持基片的导电箔40是作为电极的必要的材料。因此，具有可以非常节省构成材料而制造的优点，并且也能实现降低成本。
再有，由于使分离槽41比导电箔的厚度浅，因此导电箔40没被分离成一个一个的导电图模51，因而，能整体地处理片状的导电箔40，具有在成型绝缘树酯16时向模具运送，在模具上安装的操作非常舒适的特征。
本发明的第六工序是除去导电箔40的背面直到露出绝缘树酯的工序。
本工序是用化学方法或者物理方法除去导电箔40的背面，分隔成导电图模51的工序。本工序通过研磨、蚀刻、激光蒸发金属等方法进行。
在实验中全面湿蚀刻导电箔40，使绝缘树酯16从分离槽41露出。在图11(A)用虚线表示该露出面。结果，分隔成导电图模51，形成在绝缘树酯16上露出导电图模51的背面的构造。即，成为填充在分离槽41内的绝缘树酯16的表面和导电图模51的表面实质上一致的构造。
再有，进行导电图模51的表面处理，得到例如图1所示的最终构造。即，根据需要在露出的导电图模51上覆盖焊锡等导电材料，完成电路装置。
参照图12(A)、(B)，本发明的第七工序是在焊垫11和结合垫12的背面上设置外部电极。
首先，参照图12(A)，在绝缘树酯16的露出焊垫11和结合垫12B的面上涂布抗蚀层18，并在要形成外部电极17的部位设置开口部21。具体的是，在焊垫11的背面上设置矩阵状的第一开口部21A，在结合垫12B露出的部位设置第二开口部21B。形成第二开口部21B的尺寸比结合垫12大。因而，即使设置在抗蚀层18的开口部21的平面的位置有偏移，由于在结合垫12的背面上形成的第二外部电极的位置通过结合垫12背面的浸润性来限制，所以也能正确地形成第二外部电极17B。
再有，参照图12(B)，通过在各个抗蚀层的开口部21上覆盖钎焊材料并且熔化，形成第一外部电极17A和第二外部电极17B。在此，通过第一开口部21A限制在焊垫11的背面形成的第一外部电极17A的位置和大小。而且，通过结合垫12背面的浸润性限制在结合垫12的背面形成的第二外部电极17B的位置和大小。
如图12(C)所示，本发明的第八工序是将绝缘树酯16按每个电路装置45切割分隔。
在本工序，将方块42用真空方式吸附在切割装置的放置台上，用切割片49沿着各电路装置45之间的切割线(点划线)切割分离槽41的绝缘树酯16，分离成单独的电路装置。
在本工序，切割刀49以几乎切断绝缘性树酯16的切削深度进行，在从切割装置中取出方块42之后用辊子象分割巧克力将其断开就行。切割时预先确认在上述第一工序设置的各方块的定位标记47，以此为基准进行切割。
然后，用众所周知方式，在纵方向切割全部的切割线之后，使放置台转动90°，沿着横方向的切割线70进行切割。
发明的效果
在本发明能产生如下的效果。
第一，在本发明，由于围着半导体元件13在焊垫11的四周边缘部设置第二电镀膜14B而防止连接半导体元件13的钎焊材料19流出，因此能防止由于流出的钎焊材料19造成导电图模之间的短路。
第二，因为能通过槽14防止钎焊材料19流出，所以可使焊垫11和结合垫12接近，能使装置整体小型化。
第三，在安装半导体元件13的第一电镀膜24A的两侧面上设置凸部14D，因此在安装半导体元件13的工序，能使钎焊材料19从形成凸部14D的部位流出。因而，能使钎焊材料19均匀地流出，因此能使钎焊材料的厚度形成规定厚度。再有，能平行导电箔安装半导体元件13。
第四，通过绝缘树酯16封住的第二结合垫12B和焊垫11通过配线部20连接着，因此能增大第二结合垫12B和焊垫11的侧面的面积。因而，能增大结合垫12B与焊垫11和绝缘树酯16接触的面积，因此能增大其之间的结合力。因此能防止结合垫12和焊垫11从绝缘树酯16剥离。
第五，通过抗蚀层18的第一开口部21B限制在焊垫11的背面形成的第一外部电极的位置和大小，通过结合垫12背面的浸润性限制在结合垫12的背面形成的第二外部电极17B的位置和大小。因而，在抗蚀层18的开口部21的位置上产生偏移时，也能防止第二外部电极17B变形。

Claims (16)

1.一种电路装置，其特征在于，具有：焊垫，其通过钎焊材料安装半导体元件；结合垫，其接近上述焊垫设置；电镀膜，其形成在上述焊垫和上述结合垫的表面上，
在上述焊垫的放置上述半导体元件的第一电镀膜的周围离开间隔，设置用于防止上述钎焊材料流出的第二电镀膜，用两个电镀膜的间隙防止从上述第一电镀膜溢流的上述钎焊材料流出。
2.如权利要求1所述的电路装置，其特征在于，在上述第一电镀膜的两侧面设置凸部，使上述钎焊材料从上述凸部流出而在周围漫延。
3.如权利要求2所述的电路装置，其特征在于，通过用上述凸部使上述钎焊材料在周围漫延，维持上述半导体元件平行。
4.如权利要求1所述的电路装置，其特征在于，上述半导体装置是IC芯片。
5.如权利要求1所述的电路装置，其特征在于，上述半导体元件通过细金属线和所希望的上述结合垫电气地连接。
6.一种电路装置，其特征在于，具有：焊垫，其安装半导体元件；第一结合垫，其接近上述连接设置且和上述焊垫电气绝缘；第二结合垫，其接近上述连接片设置且和上述焊垫形成一体；绝缘性树酯，其使上述焊垫、上述第一结合垫和上述第二结合垫的背面露出，而密封上述半导体元件、上述焊垫、上述第一结合垫和上述第二结合垫；通过上述第二结合垫介于窄幅形成的配线部连接上述焊垫，增大上述第二结合垫和上述绝缘性树酯的接触面积，而强化了结合垫和上述绝缘性树酯的结合。
7.如权利要求6所述的电路装置，其特征在于，上述第一结合垫沿着上述焊垫的相对的两条边而设置多个。
8.如权利要求6所述的电路装置，其特征在于，上述第二结合垫沿着上述焊垫的相对的另外两条边设置多个。
9.如权利要求6所述的电路装置，其特征在于，上述半导体元件通过金属细线与所希望的上述第一结合垫和第二结合垫电气连接。
10.如权利要求6所述的电路装置，其特征在于，上述第一结合垫和上述第二结合垫形成圆形。
11.一种电路装置，其特征在于，具有：焊垫，其安装半导体元件；结合垫，其围着上述焊垫而设置；第一外部电极，其设在上述焊垫的背面；第二外部电极，其设在上述结合垫的背面；抗蚀层，其在对应两种外部电极的部位形成开口且覆盖背面，
使在对应上述第二外部电极的地方设置的上述抗蚀层的开口部比上述结合垫还大，通过由上述开口部露出的上述结合垫的背面的浸润性和涂布在上述结合垫的背面上的作为外部电极材料的钎焊材料的量限制上述第二外部电极的大小。
12.如权利要求11所述的电路装置，其特征在于，通过上述抗蚀层的开口部限制上述第一外部电极的位置和大小。
13.一种电路装置的制造方法，其特征在于，具有：准备导电箔工序；形成焊垫和结合垫工序，其在上述导电箔上形成比导电箔厚度浅的分离槽而构成多个电路装置部；形成电镀膜工序，其在与预定要连接半导体元件的部位相对应的上述焊垫的表面形成第一电镀膜的同时，围着上述区域形成第二电镀膜；连接工序，其在上述第一电镀膜上通过钎焊材料连接半导体元件；导线结合工序，其进行上述半导体元件和所希望的上述导电图模的导线结合；共同成型工序，其用绝缘树酯覆盖上述半导体元件并充填上述分离槽；除去工序，其除去上述导电箔的背面直到露出所述绝缘树酯；分隔工序，其通过切割上述绝缘树酯，分隔成各个电路装置。
14.如权利要求13所述的电路装置的制造方法，其特征在于，通过在上述第一电镀膜的周端部设置凸部，使上述钎焊材料从上述凸部流出，而维持上述半导体元件平行。
15.如权利要求13所述的电路装置的制造方法，其特征在于，通过使从上述凸部流出的上述钎焊材料沿着上述第二电镀膜流动，防止上述钎焊材料从上述焊垫表面流出。
16.如权利要求13所述的电路装置的制造方法，其特征在于，上述钎焊材料是锡焊料或者银焊糊。
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