TWI228949B - Circuit device and method for making the same - Google Patents

Circuit device and method for making the same Download PDF

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Publication number
TWI228949B
TWI228949B TW092119103A TW92119103A TWI228949B TW I228949 B TWI228949 B TW I228949B TW 092119103 A TW092119103 A TW 092119103A TW 92119103 A TW92119103 A TW 92119103A TW I228949 B TWI228949 B TW I228949B
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TW
Taiwan
Prior art keywords
pad
wafer
aforementioned
bonding
bonding pad
Prior art date
Application number
TW092119103A
Other languages
English (en)
Other versions
TW200405774A (en
Inventor
Kouji Takahashi
Kazuhisa Kusano
Noriaki Sakamoto
Original Assignee
Sanyo Electric Co
Kanto Sanyo Semiconductors Co
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Publication date
Application filed by Sanyo Electric Co, Kanto Sanyo Semiconductors Co filed Critical Sanyo Electric Co
Publication of TW200405774A publication Critical patent/TW200405774A/zh
Application granted granted Critical
Publication of TWI228949B publication Critical patent/TWI228949B/zh

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
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1228949 狄、發明說明： 【發明所屬之技術領域】 土本毛月疋關於種可防止用來固接半導體元件之銲材 流出的電路裝置及其製造方法。 【先前技術】 含過2，、安裝於電子機器的電路裝置是應用在行動電 払π式私腦等，因此要求小型化、薄型化及輕量化。 12 ’右以半導體裝置為例來說明電路裝置，就一般的半 置而言’有過去通常利用轉注成型法（t削如则⑷ =仃在封的封裝型半導體裝置。此半導體裝置是如第u 圖所示’可安裝於印刷基板PS。 、•：且’此封裝型半導體裝置61是以樹脂層63覆蓋半 片2的周圍，並且由此樹脂層63的側部導出外部 接用的引線端子64。然而，此封裝型半導體裝置Η是 弓ί、泉ί而子64從樹脂層63露出在外部，所以整體尺寸較 夂，因而無法滿足小型化、薄型化及輕量化的需求。因此， 二:為：實現:型化、薄型化及輕量化而競相開發了各 k取近開發出一種稱為Csp(chip ““㈣，晶 曰^寸封幻之與晶片尺寸同等的晶圓級CSP、或是尺寸比 日日片尺寸略大的CSP 〇 第14圖是表示採用玻璃環氧基板㈣ 而且比晶片尺+田々丄^ ^ 螭产，其士 、 的CSP66之示意圖。在此是針對於玻 H反65安裝有電晶體晶片T的例子加以說明。 在此破㈣乳基板65的表面形成有第1電極67、第2 314862 5 1228949 電極68以及晶片銲勢 下艾(die pad)6()， 電極70以及第2背面電極7 在月面形成有第1背面 h〇le)TH使前述第丨恭 71。而且是經由貫穿孔（thr〇 不1甩極67盥莖】北 各 使第2電極68與第9北，、罘1月面電極7Θ電性連接， 片銲墊69固接有前、f、 氣性連接。另外，在晶 按韦則述稞露的電 隹 的射極與第1電極67、# 9體日日片τ，並且使電晶體 的基極與第2電極68 〃 、、、田、、泉72而連接，使電晶體 覆蓋電晶體晶片τ的方★王屬細線72而連接。而且，以 73。 ；破㈤環氧基板6 5設有樹脂層 則逃CSP66是採用 不同，從Μ T料部=板65’但與緣級⑶ 構造相當簡單，因而罝有=/”面電極7。、71的延伸 CSP66 θ u η /、有可廉價製造的優點。而且，前述 疋如弟13圖所 柘PQ 、 yN可女裝於印刷基板PS。印刷基 S上設有構成電路的+代 ^ 刼壯 勺包極、配線，且可使前述CSP66、 、衣型半導體裝置61、曰η帝 泰 日日片境阻CR或晶片電容器CC等 連接而固接。而且’由此印刷基板構成的電路是安裝 在各種裝置中。 曰然而，上述半導體裝置中，電晶體丁是藉由使塗布於 曰片I干墊69上的銲錫等銲材熔融的回流（refi〇w)步驟而固 妾因此’若將電晶體T載置於已熔融的銲錫上，銲錫會 y曰曰片|干墊6 9上流出’而有晶片鋅墊6 9與其他電極發生 起路的問題。 而且，為了防止從晶片銲墊69流出的銲錫到達第2 电極68，而使晶片銲墊69與第2電極68相互分開，因此 6 314862 1228949 會導致整體裝置大型化。 【發明内容】 本發明是鑒於上述問題而研創者，本發 在於提供—稀诱 X 主要目的 種透過I干材將半導體元件安裝於 可防止銲材從w料流㈣電料置。、、干塾日” 晶片之特徵為具有：$透過銲材安裝半導體元件的 f le pad)，接近前述晶片銲墊而設置的接入 (bonding pad、·以》r 丄、 ^ 夺要口墊 , 形成在前述晶片銲墊及前述接人# 表面的電鑛膜，且是與前述晶片録塾：；：之 體元株沾笼1兩 < 用木戰置則迷半導 出的第2 + % ^ 周圍分開而設置用來防止前述鮮材流 %鍍膜’並利用兩電鍍膜間的空間防止從前述第 1電鍍膜溢出的前述銲材流出。 述弟 而且’本發明是在前述第1電鍍膜的兩側面設置凸 部’使前述銲材從前述凸部流出而使銲材擴展至周圍。 而且’本發明是利用前述凸部使前述銲材 圍，藉此使前述半導體元件維持平行狀態。’、 而且’本發明巾’前述半導體裝置S 1C晶片。 本^月中，m述半導體元件是透過金屬細線盥 預J的前述接合墊作電性連接。 /、 "二且’本Ϊ明之特徵為具有：可安裝半導體元件的晶 接近則4晶片銲墊而設置，並且與前述晶片 電性分離的第"妾合塾；接近前述晶片銲墊而設置，並且 :則述：片：墊一體形成的第2接合墊；卩及使前述晶片 a 第1接合墊及前述第2接合墊的背面露出而密 314862 7 1228949 封别述半導體元件、前述晶片銲墊、前述第1接合塾及前 述第2接合墊的絕緣性樹脂，藉由使前述第2接合墊透過 寬度狹窄形成的配線部與前述晶片銲墊相連接，以使前述 第2接合塾與前述絕緣性樹脂接觸的面積 只曰八，亚且強化 接合墊與前述絕緣性樹脂的接合。 而且，本發明中，前述第丨接合墊是沿著前述晶片銲 塾之相對向的兩個邊設置複數個。 而且，本發明巾，前述第2接合墊是沿著前述晶片銲 塾之相對向的另外兩個邊設置複數個。 預二且，本發明巾，前述半導體元件是透過金屬細線使 預期的雨述第"妾合塾及第2接合墊作電性連接。 是形=本發明中，前述第1接合塾及_2接合墊 ，本發明之特徵為具有：可 片銲墊；幻FI儿、丄、 文衣牛¥體兀件的 ，圍則述晶片銲墊而設置 片銲墊之普 丧。塾，故在W述 第2外部電極：：二部電極；設在前述接合墊之背面 開口部，並且二二對應於前述兩外部電極的部位形 第2外部面的光阻劑’並且使設在對應於前 塾，並二?部位的前述光阻劑的開口部大於前述接. 性、以1^述開口部露出的前述接合墊之 及作為塗布於前述接合 、‘ 銲材量來限制前述第2外部電之外部電極之材料| 而 I包極的大小。 .„ 本發明中，前述第1外邻+代Θ丄 的開D部限制位置及大小。 卜邛电極疋由前述光阻 314862 8 !228949 日 I，本發明之特徵為具有：準備 前述導畲# 干1W ¥包箔的步驟；在 安消形成比其厚度淺的分離凹槽， 數個雷败壯 形成可構成補 衣置部的晶片銲墊及接合墊的步· 定固接的立、音~，在對應於預 、+ V脰兀件之區域的前述晶片銲墊矣；π Λ、_ 、 電鑛膜， 登表面形成第1 驟；透ir^日』L … 〆取弟2電鍍膜的步 _ β干材將半導體元件固接於前述第1電获腺卜& #^ίΛ y ife 上的步 則：^半導體元件與預期的前 合的步騍· & V电圖案之打線接 填充於前、+、八μ ^、千¥體兀件，並且 J述刀離凹槽的方式，共同 前述導雷# 3b 丁成型的步驟；去除 泊的背面直到前述絕緣性 除 以及藉由切宝，丨1、+、 Γ細^出為止的步騾； 驟。 刀雕成各電路裝置的步 而且，本發明是在前述第丨電获 部，並且倭I 电鍍艇的周端部設置凸 __ 』述1于材從前述凸部流出，茲+ & _ 元件維持平行狀離。 猎此使珂述半導體 而且’本發明是使從前 述第2電鍍膜_ u 巩出的前述銲材沿著前 面流出。4，猎此防止前述銲材從前述晶片鲜塾表 而且，本發明中，前 【實施方式】 吁疋銲錫或銀（Ag)膠。 (說明電路梦罢t Λ 、 0之構成的第1 參照第1圖來今Μ 4 ^m3 不1 IS)木呪明本發明兩 1圖（A)是電路穿f ]n 甩路衣置10的構成等。第 电峪衣置10之俯視圖， 之剖視圖。 系1圖（B)疋電路裝置1() 314862 9 1228949 參照第1圖（A)及第i圖（]5)，電路裝置1〇具有以下的 構成。亦即形成具有：可透過銲材19安裴半導體元件U 的晶片銲墊11 ;接近晶片銲墊11而設置的接合墊丨2 ;以 及形成在晶片銲墊U及接合墊12表面的電鍍膜，其中\ 與晶片銲墊U之用來載置半導體元件13的第丨電鍍膜 14A之周圍分開而設置用來防止銲材19流出的第2電=膜 14B，並利用兩電鍍膜間的空間防止從第i電鍍膜μ:溢 出的銲材19流出之構成。以下說明上述的各構成要素酿 晶片銲墊11是安裝有半導體元件13的導電圖案，並 且由銅羯等金屬所構成’且是使背面露出而埋設於絕緣性 樹脂16。而且’晶片㈣U的平面大小形成地比所安掌 的+導體元件13略大，在其周邊部則形成有第2電鑛膜 ⑽。在該圖⑷中是使晶片料n开）成於中央部，並且 透過鮮材19安裝有由1C晶片等所構成的半導體元件13。 另外，在對應於安裝有半導體元# 13之區域的晶片銲塾 11表面形成有由銀（Ag)等所構成的第i電鍍膜14八。 接合墊12是可搭接金屬細線15的導電圖案，且是使 背面露出而埋設於絕緣性樹脂16。在此是圍 置中央部的晶片鲜塾η的方式，形成有多數個圓狀接2 :在該圖㈧當中’形成於晶片鲜塾11Α右兩側的接合 1以是以電性獨立的方式設置。另外，形成於晶片銲塾 \上下兩側的接合塾12Β是與晶片銲塾ιι#連形成，並 的二電：連接。而且，在接合塾12表面為了提高所搭接 m泉的接著性，而形成有由銀（Ag)等所構成的第3 314862 ]0 !228949 電鍍膜14C。
的#半導體元件13是透過鋒材19而安裝於晶片輝塾u 的表面，在此是透過鮮材19而安裝有在半導 =U 大型的1C晶片。而且，开…千¥…牛中較為 與接合墊12是透過金屬 二凡件13表面的電極 曰Μ 4Θ '，、、泉5而作電性連接。另外，盥 曰曰片鋅墊11作電性連接的接 - 而電性連接於半導體纟疋透過金屬細線Η 瓴十/ 件 在此所使用的銲材可使用名曰 錫或銀（Ag)膠等導電性接著劑。 使用鲜 出而”性樹脂16是使晶片：塾U及接合塾12的背面露 :而靖全體。而且，在形成 二路 槽上士 ^丄^ 表面的凹 也填充有絕緣性樹两匕*1 ^ 13、金屬細線= 是密封住半導體元件 才料可使用可藉師=合塾12。絕緣性樹脂 脂、或可葬ώ私Φ々、" /成i法而形成的熱硬化性樹 一 a 型法而形成的熱可塑性樹脂。 使半==?=膠等導電性膠一)，具^ 是導電性材料，二導= 是作電性連拯^ v月豆7°件13的背面與晶片銲墊u 电「玍運接。而且，报 a u 墊12B盘曰片^執 U塾11上下兩側的接合 屬細線^Λ 是電性連接。因此，藉由使用金 可使开^ +導體7^件13的電極與接合塾12Β相連接， 半導體元件13之表面的電路與半導 7月面作電性連接。 面所带成=圖Μ) ’說明於晶片鋒塾Η及接合塾12之表 ^ 1鍍膜。該俯視圖中僅顯示出晶片鲜塾η、接 314862 11 1228949 合：u以及形成於兩者之表面的電鍍膜， …牛13及金屬細線15的圖示’各體 有對應於半導體元件13之載置巴塾U的表面形成 炙戟置£域的第1電鍍膜UA;以 及以與弟1電鍍膜14A分開而包圍 膜14B。而且，在接合墊 =/ 2電鐘 又有弟3電鍍膜14C。 处甩鍍膜1 4的材料可使用銀、鎳或金等。 第1電鍍膜14A是對應於半導體元件13的載置區域 叹置、、形狀及大小與半導體元件13同等。而且，透過 鲜材安裝半導體元件13時，為了使銲材19左右均等流出， 在第1電鍵膜14A之相對邊的中央部附近設有凸部14D。 凸部14D是使第i電鍍膜14A之周邊部的一部分變形的部 位，在此，凸部14D是朝外側突出而形成。 第2電錄膜14B是以與上述第1電鍵膜14A分開而包 圍的方式^成在晶片銲塾n的周邊部。透過_材19安 衣半導組兀件13時’鮮材19會從設在第1電鍍膜“A的 凸部14D附近溢出。然後藉由第2電鍍膜所形成的段 差，防止鮮材19從晶片產导塾n流出。另外，由於第2電 鑛膜1 4B之材料係為銲材的濕潤性良好者，因此從第1電 锻膜14A溢出而到達第2電鑛膜MB的鲜材19會沿著第^ 電鍍膜1 4 B的内側流動。 本發明之特徵在於：使第2接合墊丨2]B透過寬度狹窄 的配線邓20與晶片銲墊丨丨相連接，以增加第2接合墊丨 與·巴緣性樹月曰1 6接觸的面積，並且強化接合墊i 2 A與絕 緣性樹脂1 6的接合。具體而言，如上所述，由於晶片銲墊 12 314862 1228949 i i興第2接合 —體化的矩形陸塊（land)。然而，成使兩者 本發明中，篦2接Α熱 UB是形成圓形，透過寬度狹窄 口 片銲墊η μ… 部20而與矩形的晶 Π 述構成，即可使"接合塾 的面-. 卫日加與絕緣性樹脂16接觸 的面積。因此，透過配線部2〇而—雕 晶片銲塾11與絕緣性樹脂16 1接合墊12B及 防止接合墊及晶片銲墊⑽絕緣;;：7固。由此即可 . 、豕注Μ脂16剝離。 麥照第2圖（B)(C)，說明電路裝置 部電極17。本發明的電路裝 β戶斤形成的外 安裝半導體元…晶片鲜塾冓成係具有：可 置的接合塾12;設在晶片鲜塾；/ί面圍”鲜塾"而設 1 7Α .却·名姓入# 月面的第1外部電極
17A，δ又在接合墊12背面的第”卜 U 應於兩外部電極的部位 ：以及在對 阻劑，其中，使設在對應於第2二=盖背面的光 阻劑1“㈣口部21Β大於接 之部位的光 露出的接人勃 墊12,並利用從間口部21Β 路出的接合墊12背面的濕潤性以及 I 113 背面的外部電極17的材料 ’”、土布於接合墊12 17Β的大*。以下，: 的$來限制第2外部電極 丨圖已作」明 ^種構成要素。此外，關於袁昭第 1圖已作祝明的構成要素由於相同…弟 第"卜部電極ΠΑ是在曰片㈣“略其導 設有複數個，i I ώ ρ Μ A 5月面以矩陣狀 亚且由鲜錫等銲材所形成。而且，第彳& 電極”A的位置及大小是由形 -外部 部21A所限制。因此，第”卜部、”:？““1開口 卜邛兒極17A的平面大小與設 314862 13 1228949 在光阻劑1 8的第1開口部21A同等。 第2外部電極i7B是設在以包圍晶片銲墊η的方式 設置的接合墊12的背面。而且，接合 工 々 复以疋攸先阻劑1 8 的弟2開口部21B露出，因此第2外 m 7 , 外°卩電極17B是形成在 弟2開…1B内部。在此，設於光阻劑18的第2開口 的大小形成地比從該處露出的接合墊ΐ2β的背 大。因此，從第2開…1B會露出接合墊^
樹脂的背面。由此，在形成外部電極17的步驟中、、豪生 果將銲材塗布於接合墊12上而使i炫 Λ D >然/聞性良好的接合墊12之部位形成外部電極” 第”卜部電極17B的平面形狀與接合塾12為 狀 、配㈣2G是使接合塾12與晶片料U相連接的邻 分，其見度比接合墊12的直徑狹窄。如 ' 形成地較狹窄，可增"形成的晶Γ:: = :二2墊T部的面積。而且’配線部2。的-部分4 J大的弟2開口部21B露出，但 寬度狹窄，可使霖屮Μ 上述使 了使L出的部分的面積降到最 外部電極1叫已溶融的詳材也可能會弄渴=弟2 部20，而佶筮？从如； …、路出的配線 弟2外邛U極17Β的形狀從圓形 如上述使配線部⑽寬度狹窄，可將銲因此， 所““"2外部電極17Β的變形 :;配、、〜 在電路襄置Η)的背面是使上述第丄外舍?^ 極17是各自形成大致同等的大小。因此而二外部電 错由透過外部带 3]4862 14 1228949 電路裝置w安裝於母板叫等安裝基 I~低對於各外部電極1 7所作用的應力。 17 > ^弟3圖，說明形成於電路裝置之背面的外 二外二電極”是形成在包圍晶片鲜塾Π而設置的接1 外二Γ面口。而且，在晶片鲜塾11的背面也設有多數； : 此外部電極17是在整個電路裝置10背面以 將干隔且成矩陣狀設置多數個。藉此，在透過外部電極！ 7 裝置1G安裝於母板等安裝基板時，可縮 屯極17所作用的應力。 卜$ 17的：:弟及1圖⑻’形成在晶片銲墊11背面的外部電極 --------- ]2的背面所 潤性良好的材料，由：:二v料的銅等金 大小會受到限制。如卜 使外部電極17的位置及 σ上述，利用接合墊1 2的渴潤性來卩F & 形成於接合墊12昔而沾从如； （，、、们性入限制 是在光阻劑18之:广 17的位置及大小，即使 上先？"8之開口部的位置發生偏移的情況下， 度良好地形成外部電極丨7。 精 =之特徵在於:與形成在晶片薛墊η之可 ¥肢兀件13之區域的第1 干 第1電鍍膜14Α的方式而 V /刀開’然後以包圍 ㈣半導=電錢膜14Β。透過辉材 體元件鳴量等已膜14Α時’由於半導 流出。然後’藉由以包圍㈣9會㈣1電鍛膜14Α 匕出弟1电鍍膜14Α的方式而設置的 314862 15 1228949 第2電鍍膜1 4B來形成段差，而且此段差可作為防止鲜材 19流出的阻止區域而發揮作用。因此，從第i電鑛膜14a 流出的銲材19會貯存在第1電鍍膜14A與第2電鍵膜14β 之間所形成的空間。故可防止由於安裝半導體元件丨3以致 從第1電鍍膜14A溢出的銲材19從晶片銲墊u流出。由 此’即可防止流出的銲材19導致晶片銲墊丨丨與接合塾12 發生短路。 面 ^ x电殿朕丄4A的兩側 一设置凸部14D。藉此，在透過已熔融的銲材19安裝半導 豆件1 3日守，可使銲材1 9從兩側面均等流出。因此，可 =:::19偏向一邊流出而導致半導體元件13傾斜。還 了使鲜材1 9的厚度均一。 p㈣設置第2钱膜14B的其他㈣ Γ利用配料機等用來供應銲材的機械而塗布於曰二： '表面’但由此配料機可供應的銲# 19的最 旦 疋疋的。ϋ此，如果配料機的最小f 二9里 兀件13安裝於晶片銲墊u所需 於將半¥體 恐有從晶片銲墊"的表面流出之虞則銲材19 電鍍膜14B，可防止銲材19流出。'此’藉由設置第2 (說明電路裝置i。之製造；法 本實施例是說明電路裝 、 貝轭形態） 態中，電路裝置10是由以 的製造方法。在本實施形 驟··準備導電箔4。的步驟.在：所製造。亦即具有以下步 的分離凹槽…以形成可構成比其厚度淺 笔路裝置部4 5的晶 314862 16 的49 ju 辞墊11及接合墊1 賤元件13 <…曰的步驟’·在對應於預定固接之半導 十u之&域的晶片銲墊 卞’ :A’同時以包圍前述區域 I面形成第1電鑛膜 〉鱗；透過輝材19將半式形成第2電錢膜⑽的
取上的步驟；進行半ϋΓ13固接於第1電鑛臈i4A 後镇合（wire b〇ndlng)的/"〗3與預期的接合墊U之打 舉導體元件13,並且殖利用絕緣性樹脂Μ以覆蓋 的步驟；去除導電笛凹槽41的方式共同成型 此的步驟，·以及夢由㈣^面直到絕緣性樹脂Μ露出為 复的步驟。以下==緣性樹脂16而分離成各電路裝 ^罐。 乐1 2圖來說明本發明的各 本發明的第1步驟e ^40,並且在導電^:如第4圖至第6圖所示，準備導 R形成可構成、 $成比其厚度淺的分離凹槽4 1， 聲12構成硬數個電路裳置部^的晶片鲜塾U及接合 在本步驟中，首弈3^ 電箔40。此導帝μ疋口弟4圖（Α)準備片（sheet)狀的導 錢性而選擇其:料 電落、以銘⑷）為主要 铜（CU)為主要材料的導 等合金所構成的導電落^。、導電Η是由鐵叫錄（Ni) 導電箔的厚度若+ 1〇_至3⑽μΐΏ左右，^本之/的㈣作業，則最好在 下皆可。如後文所述，σ—要^^在3〇〇_以上或1〇帅以 分離凹槽41即可。 /成比導電落40之厚度淺的 314862 17 1228949 m夕卜#狀導電箔40能以預定寬度例如45mm捲繞成 滾同狀而預備，並 疮、兀成 成預定女^ 、搬迗至後述各步驟，亦可準備已切 、具w的細長狀導電箔40，並搬送至後述各步驟。 上形成：：：二第4圖⑻所示，使在細長狀導電“〇 並列。在夂路裝置部45的4至5個區塊42分開而 在各區塊42 > p卩却·士日日 等之加熱處理所產生：“ 43 ’用來吸收成型步騾 4〇的上下周ρ、 的¥ -电落40的應力。而且，在導電箔 在各步驟的定：：定間隔設有索引孔h°le)44，可用 =下來形成導電圖案。首先如第5圖所示，在導 化⑽terning)，俾使^罩）叹，亚且使光阻齊！ PR圖案 的導電箱4〇霖出1要形成導電㈣51《區域之外 導電落40。在此，導^，如第6圖⑷所示’選擇性姓刻 晶片銲塾η及接合墊：51即形成各電路裝置部45的 圖案(圖形成晶片銲墊U及接合墊丨2的導電 對應圖。-個；I:、4圖(B)所示之-個區…大後的 塊…數路㈣ 且在各個電路穿置： 排列成兩列兩行的矩陣狀， 的周邊設有框二445設有同一導電圖帛51。在各區塊 割時的位置對準/ 6,與其稍微分開而在其内側設有切 叙合，而且在框狀圖案…於與成型模具 脂……卜另：：的背面㈣後具有可補強絕緣性樹 在各電路裝置部中，形成在晶片銲墊 314862 18 1228949 2上下兩側的接合塾12是與晶片料11 -體〖，而且兩 者也作電性連接。 兩 本發明的第2步驟是如第7圖所示，在對應於預定固 ==元V3之區域的晶片銲墊11表面形成第1電 、 ^以包圍料區域的方式形成第2電錄膜 14C。本步驟中是在接合塾12表面形成第3電鑛膜 在本步驟中，首先在除了預定形成之第i電鍍膜 "A、弟2電鑛膜14B及第3電鑛膜Mc之外的部位形成 光阻劑。然後，利用電 膜。在此，上述電…::或然電％電鑛法形成電錢 鍍胺的材料可採用銀、鎳或金等。 在形=形的^電鑛膜14A的兩側面形成有凸部⑽。 务明的弟3步驟是如第8圖及第9圖所示，透過俨 材19將半導體元件13固接於第！電鍵膜14A上。牡 :知弟8圖⑷，透過鮮材19將半導體元件η安裝在 >成方；晶片銲塾u表面的帛1電㈣\ =錫:鄉嶋導電性《。本步驟中，：:: 部時，銲材^因為^載置於銲材19上 鑛膜1从溢出。在此，以二3的重量等而從第1電 域的方式，在晶片銲墊二:Ϊ置半導體元件13之區 11的周邊部形成有第2帝供η- =1擴展的'材19並不會從晶賴1流： 達弟2電鍵膜14Β的鲜材19 出到 第2電鍍膜14Β之間 、子在弟1电鑛版14Α與 1的工間。因此，第2電鍍膜14Β具有 314862 19 1228949 用來阻止銲材19流出之阻止區域的功能。所以，鲜材b 不會從晶片銲墊u的表面溢出’而可防止晶片銲墊η斑 接合墊1 2發生短路。 /、 參照第9圖來說明設在第i電鍍膜"a之兩側面的凸 卩14D的作$。第9目（Α)是表示在本步驟中鋒材19從 1電鍍膜14 Α流出之狀態的立丨丨葙闰 — 圖。 〜的視圖，第9圖（Β)是其俯視 牡參照第9圖⑷及第9圖（Β)，藉由將半導體元件^ ::已：融的銲材19上部’銲枋19會從第！電鑛膜"Α ^出。在此’由於在第i電鍍膜14A的兩側面（在此是卢 右的兩側面）形成有凸部14D， 工 几加U此*于材19會先從形成有 凸部“D的部位流出，並且 成有 , , 1 〇 ^ ^ J寻無偏地流出。由此， 在干材19的厚度可保持一定，而 半導俨开杜透過#材19而固接的 牛¥肢兀件13可保持平行性而安 度伴持一 A 猎由使銲材1 9的厚 保# 疋，可提升半導體元件13的埤挪从#丄 衣+¥體兀件13，可利用半導體 女 確進行其位置辨識。因此，可表面的光反射正 行的打線接合步驟。 $仃在位置辨識後所進 本發明的第4步驟是如第10圖 13盥預期> & Α ㈡所不，進行半導體元件 〃預期之接合墊12的打線接合。 具體而言是藉由利用熱壓接的球 的楔形接人 味形接合及利用超音波 3才六浴接合，對於安裝在各 13之電極衣置部45的半導體元件 本Γ:預期的接合墊12-起進行打線接合。 本V私是利用照射於半導體元 1 3表面的光的反射 314862 20 1228949 ，行位置辨識’由於在前步驟，半導體元件13才目對於導電 箔40是平行安裝，因此可正確進行半導體元件η的位薏 辨識。 本發明的第5步驟是如第n圖所示，以覆蓋半導體元 件13，亚填充於分離凹槽41及凹槽14的方式，利用絕緣 性樹脂1 6共同進行成型。 本步驟是如第u圖（A)所示，絕緣性樹脂16是完全覆 蓋半導體元件丨3以及複數個晶片銲墊u及接合墊12，而 且在分離凹槽41及凹槽14填充有絕緣性樹脂丨6,並且遍 分離凹槽41 Μ而穩固結合？而且是利用絕緣性樹脂16 支持著晶片銲墊i i及接合墊1 2。 …而且，本步驟可藉由轉注成型法（tr㈣则ld)、射出 去（injeCtl〇n m〇ld)、或膠埋法（potting)來實現。就樹 曰材料而·τ ’環氧樹脂等熱硬化性樹脂可藉由轉注成型法 來貫現’聚酿亞胺樹脂(polyimide resin)、聚苯硫喊 (=yPhenylene sulfide)㈣可塑性樹脂可藉由射出成型法 采貫現。 &再者，本步驟在進行轉注成型法或射出成型法時，如 弟11、圖（B)所示，各區塊42是將電路裝置部45收納在— 模具，並且在各區塊利用-個絕緣性樹脂丨6 於夂π i。因此’比起如習知的轉注成型法等個別對 趴。電路裝置部進行成型的方法， 、 詈。 j °系求削減大量的樹脂 本步驟的 特被在於：覆蓋絕緣性樹脂1 6之前是并 314862 21 1228949 導電圖案5 1的導電泛1 a 不需要的支持基板來形^支持基板。過去是採用原本 支持基板的導電落是電圖案，但在本發明中，作為 有可盡量節省構成材料而“爛而的材枓。因此，具 低。 “4而作業的優點’亦可實現成本的降 而且，分離凹槽41形 導電荡40不會各自 ？泊的尽度遂淺’所以 μ 隹成導電圖案51。因此，κ貼道币 《“〇可-體處理’而具有 , 搬送至模具、安豕1^月曰16進订成型時， , 1 ;果具的作業變得非常輕鬆的特徵。 本㈣的第6步驟在於去除導電 性樹脂露出為止。 月甶罝到絶緣 本步驟是以化璺& 面、，0 \ 千陸及/或物理性去除導電IS 40的背 ’亚且为離成導電圖案51。此步驟是藉由 钱刻1射之金屬蒸發等來進行。^由心、研削、 etcl/ ^ 全面對於導電箔40進行濕式蝕刻（wet 吏絕緣性樹脂16從分離凹槽4i露出。第"圖 而：：亚線顯不此露出的面。結果便會形成導電圖案W 刀^。於^形成導電圖案51之背面露出在絕緣性樹脂 矣“、.. -允万、刀離凹槽41的絕緣性樹脂16的 表面與導電圖㈣的表面會形成實f上相—致的構造。 :進仃導電圖案51的背面處理，並獲得例如第i圖所 構造。亦即’將銲錫等導電材料附著在依需要而 L出的V電圖案51，而完成電路裝置。 本發明的第7步驟是參照第12圖（a)、（B)，在晶片銲 314862 22 1228949 塾 1 1 12 及接合墊12的背面設置外部電極。 U及:先參照第12圖(A)，在絕緣性樹脂16之晶片銲墊 外部、合墊12B露出的面塗布光阻劑18，並且在要形成 墊二極北17的部位設置開口部21。具體而言，在晶片銲 露出的矩陣狀的第1開口部21八，在接合墊咖 小开^部位則設置第2開口部21B。"開口部2ΐβ的大 口部地比接合墊12大。因此，即使設在光阻劑Η的開 a之平面位置發生偏移，形成在接合墊12背面的第 部電極的位置也會因為接合墊12背面的濕潤性而受到 、1 ’因此第2外部電極丨7B可正確形成。 開。,下來，參照第12圖(B)，將銲材覆蓋在光阻劑的各 冲2 1而使其熔融，藉此形成第1外部電極1 7 A及第2 泰冲電極1 7B。在此，形成於晶片銲墊i i背面的第^外部 :極17A的位置及大小是由第！開口部21 a所限制。而形 曰在接合墊12背面的第2外部電極17β的位置及大小則 疋由接合墊12背面的濕潤性所限制。 ^本發明的第8步驟是如第12圖（C)所示，將絕緣性樹 1 6依各個電路裝置部4 5切割而分離。 本步驟是使區塊42真空吸附在切割裝置的載置台，並 且利用切割刀片49沿著各電路裝置部45間的切割線（一點 鏈線）切割分離凹槽41的絕緣性樹脂16，並分離成個別的 電路裝置。 ^在本步驟中，切割刀片49只要以可大致切斷絕緣性樹 知1 6的切削深度進行，並且在從切割裝置取出區塊42之 23 314862 1228949 後】用滾筒進行巧克力破 前述第】步驟所# w的欠厂ώ 刀。彳訏疋預先辨識名 此為基準進行：:Γ 置對準標記47,然後以 進仃切割。雖然已眾所週知，但 切割所有的切割線之後，將載置台旋轉9。度二=向 的切割線進行切割。 度再&者杈方向 【發明之效果】 ，發明可發揮以下所示的效果。 弟卜本發明是以包圍半導體元件Μ的方式在 曰 墊11的周邊部設置第帝 、于 ^ 弟鍍膜14Β，以防止用來固接丰蓬 體兀牛1 3的銲材1 9流出，因此可防止 、 < 、皆# 、皆 ΜJ丨万立因為流出的銲材】9 而V致V電圖案彼此發生短路。 弟2 ’由於可藉由凹槽14防止銲材19流出，因此可 使晶！料11及接合塾12接近，而可使整個裝置小型化。 弟3’由於在可安裝半導體元件13的第 的兩側面^有凸部⑽，因此在安裝半導體元件13的步; 中’可使!干材19從形成有凸部14D的部位流出。故 銲材^等流出，因此可使料19的厚度保持—定。^ 可相對於導電羯並行安裝半導體元件13。 ^ 第4’由絕緣性樹脂16密封的帛2接合墊12B及晶片 鋅墊11是透過配線部20而相連接，因此可增加第2接合 墊12B及晶片銲墊11之側面的面積。故可增加接合墊12B 及晶片銲墊η與絕緣性樹脂16接觸的面積，因此可使兩 者的結合力增大。由此即可防止接合塾12及晶片銲墊u 從絕緣性樹脂1 6剝離。 314862 24 1228949 第5，形成在晶片銲墊u背的第 卜 ^ 外部電極是由光 阻劑1 8之第1開口部21A限制其位置及大 久大小，形成在接 合墊12月面的第2外部電極丨7B是由接人 伐σ墊12背面的濕 潤性而限制其位置及大小。因此即使来 U此即便九阻劑1 8的開口部 21的位置發生偏移’也可防止第2外邻㊉ 乐 邓#電極17Β發生學、 形。 【圖式簡單說明】 的俯視圖（A)、剖視圖 的俯視圖（A)、後視圖 的後視圖（A)、剖視圖 第1圖是說明本發明之電路裝置 (B) ° 第2圖是說明本發明之電路裝置 (B)、剖視圖（C)。 第3圖是說明本發明之電路穿置 (B) ° 路裝置的製造方法的剖視圖 兒路裝置的製造方法的剖視 弟4圖是說明本發明之電 (A)、俯視圖（B)。 第5圖是說明本發明之 圖0 弟6圖是說明本發明之 (A)、俯視圖（B)。 弟7圖是說明本發明之 (A)、俯視圖（B)。 弟8圖是說明本發明之 (A)、俯視圖（B)。 包路裝置的製造方法的剖視圖 兔路裝置的製造方法的剖視圖 电略裝置的製造方法的剖視圖 314862 25 1228949 第9圖是說明本發明之 (A)、俯視圖（B)。 电路裝置的製造方法的剖視圖 第1 0圖是說明本發明之 圖（A)、俯視圖（B)。 電路裝置的製造方法的剖視 置的製造方法的剖視 置的製造方法的剖視 第11圖是說明本發明之電路拿 圖（A)、俯視圖（B)。 第1 2圖是說明本發明之電路裳 圖（A)、剖視圖（B)、俯視圖（c)。 第13圖是說明習知電路裝置的剖視圖。 第14圖是說明習知電路裝置的剖視圖。 10 電路裝置 12 接合墊 1 2B第2接合墊 14 凹槽 14B第2電鍍膜 14D 凸部 16 17A 18 20 21 A 40 42 絕緣性樹脂 第1外部電極 光p且胃j 配線部 第1開口部 導電箔 區塊 11 晶片鲜塾 12A 第1接合墊 13 半導體元件 14A 第1電鍍膜 14C 弟3電鍍膜 15 金屬細線 17 外部電椏 17B 第2外部電 19 鮮材 21 開口部 21B 第 2開π _ 41 分離凹樺 *曰 43 開缝 314862 26 索引孔 框狀圖案 切割刀片 光阻劑（_ #刻遮罩） 半導體晶片 引線端子 CSP 第2電極 第1背面電極 樹脂層 45 電路裝置部 47 位置對準標記 5 1 導電圖案 61 封裝型半導體裝置 6 3 樹脂層 6 5 玻璃環氧基板 67 第1電極 69 晶片銲墊 71 第2背面電極 TH 貫穿孔 27 314862

Claims (1)

  1. ^228949 拾、 申請專利範圍： l〜種電路裝置，其特徵為具有： 可透過辉材安获主道^ _ 接近前述晶片二塾而:的晶片録墊； ^ 日片如墊而設置的接合墊；以芬 形成在前述晶片銲墊及前述接合墊之矣 模，其中， 墊之表面的電 與w述晶片銲墊之用來 1電鍍膜周圍分開而設置用來防止：逑半導體元件的 電鑛膜，並利用兩電鐘媒== 述鮮材流出的第 膜溢出的前述銲材流出。 止处w述第1電《 2. 如申請專利範圍第】項之電路 電鑛膜的兩側面設置凸部，使前’二中」在前述第 而使銲材擴展至周圍。 ’L 才攸别述凸部流d 3. 如申請專利範圍第2項之 部使前述銲材擴展至周圍，使」其中’利用前述凸 平行狀態。 θ使則述半導體元件维持 4.如利範圍第2項之電路襄置 兀件疋1C晶片。 八甲則述半導體 5·如申請專利範圍第】項之 元件是透過金屬細線與預二f置，其中，前述半導體 6· -種電路裝置，其特徵為具有則述接合墊作電性連接。 可安裝半導體元件 而設置，並且與前述 片^塾，·接近前述晶片鮮塾 〒墊电性分離的第1接合墊； 3]4862 28 1228949 接近前述晶片銲墊而設置，计 w且轉前述晶片_塾_ _形 成的第2接合墊，·以及使前试s u ^ “ 处日日片銲墊、前述第1接八 塾及前述帛2 #合墊的f 广弟1接口 件、前述Μ銲墊、前㈣^述半導體元 的絕緣性樹脂， ”接合塾及前述第2接合塾 藉由使前述第2接合敖^ 部與前述晶片料相連接，2過寬度狹窄形成的配線 M使珂述第2接人執*々、十、 絕緣性樹脂接觸的面積增 、， 口墊/、刖处 7. 8. 9. 10 11 緣性樹月旨的接合。、亚且強化接合塾與前述絕 如申請專利範圍第6項之電 合塾是沿著前述晶片鲜塾之路相；^’其中，前述第1接 個。 子向的兩個邊設置複數 如申請專利範圍第6項之電 合塾是沿著前述晶片鲜塾q目對㈣^料第2接 複數個。 另外兩個邊設置 如申請專利範圍第6項之 凡件是透過金屬細線使預期的 ^ 1述+導體 合墊作電性連接。 ;L 接合墊及第2接 如申請專利範圍第6項之電路農置 — 合墊及前述第2接合塾是形成圓形。、，刖述弟1接 一種電路裝置，其特徵為具有· 可安裳半導體元件的晶片銲 :設置的接合塾·，設在前述晶片録塾之園:述…塾 包極，設在前述接合墊之北 面的第1外部 月面的第2外部電極；以及在 314862 29 1228949 對應於前+ μ a & 兩外部電極的部位形成 —，並且覆蓋背 面的光阻劑 、十、丄亚且使設在對應於前述第2外部電極之邻仿& > 述光阻劑的„ η加L 位之口fM立的刖 . 開卩大於前述接合墊，並利用m π 部露出的前什拉人& 1〜用攸刖述開口 ^ J述接合墊之背面的濕潤性、以 耵述接合墊背而十从加 及作為塗布於 、f ^ 月面之外部電極之材料的 述弟2外部電極的大小。 材里末限制則 12·如申請專利範圍第u項之電 、， 外部電極是由-、+、丄 置，、中，丽述第1 u—接― 則述光阻劑的開口部限制位置及大j 。 • |路裝置的製造方法，其特徵為具有： 準備導電箔的步驟； 在韵述導電箔形成比其厚八 可播士、— A /3<i的刀離凹槽’以开）Λ 了構成稷數個電路裝置部的a x形成 騾； 曰曰片1于墊及接合墊的步 在對應於預定固接的半導 片銲墊表面形成證】币 ^件之區域的前述晶 形成弟1電鍍 式形士斤ο 、 ^ ^以包圍前述區域的太 式形成第2電鍍膜的步驟； I匕坟的方 透過銲材將半導體元件固 的步驟； 、則述弟1電鍍膜上 進行前述半導體元件與 、… 線接合的步驟； 、、/勺則述導電圖案之打 —利用絕緣性樹脂以覆蓋前述半導體 於丽述分離凹槽的方式 a 亚且填充 去、门進仃成型的步驟； 去除刖述導電箔的背 1幻則述絕緣性樹脂露出 314862 30 1228949 為止的步驟；以及 藉由切割前述絕緣性樹脂而分離成各電路裝置的 步驟。 1 4.如申請專利範圍第1 3項之電路裝置的製造方法，其 中，在前述第1電鍍膜的周端部設置凸部，並且使前述 銲材從前述凸部流出，藉此使前述半導體元件維持平行 狀態。 1 5 .如申請專利範圍第1 3項之電路裴置的製造方法，其 中，使從前述凸部流出的前述銲材沿著前述第2電鍍膜 流動，藉此防止前述録材從前述晶片銲墊表面流出。 1 6.如申請專利範圍第1 3項之電路裝置的製造方法，其 中，前述銲材是銲錫或銀（Ag)膠。 31 314862
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