CN104779224B - 一种功率器件的qfn封装结构 - Google Patents
一种功率器件的qfn封装结构 Download PDFInfo
- Publication number
- CN104779224B CN104779224B CN201510177211.7A CN201510177211A CN104779224B CN 104779224 B CN104779224 B CN 104779224B CN 201510177211 A CN201510177211 A CN 201510177211A CN 104779224 B CN104779224 B CN 104779224B
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- semiconductor chip
- glue groove
- pin
- sided semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Abstract
Description
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510177211.7A CN104779224B (zh) | 2015-04-15 | 2015-04-15 | 一种功率器件的qfn封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201510177211.7A CN104779224B (zh) | 2015-04-15 | 2015-04-15 | 一种功率器件的qfn封装结构 |
Publications (2)
Publication Number | Publication Date |
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CN104779224A CN104779224A (zh) | 2015-07-15 |
CN104779224B true CN104779224B (zh) | 2017-07-28 |
Family
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Family Applications (1)
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CN201510177211.7A Active CN104779224B (zh) | 2015-04-15 | 2015-04-15 | 一种功率器件的qfn封装结构 |
Country Status (1)
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CN (1) | CN104779224B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107833960A (zh) * | 2017-10-23 | 2018-03-23 | 山东晶泰星光电科技有限公司 | 一种具有溢流通道和溢流槽的led支架及其制造方法 |
CN117529804A (zh) * | 2021-09-07 | 2024-02-06 | 华为技术有限公司 | 芯片封装结构和用于制备芯片封装结构的方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3072291B1 (ja) * | 1999-04-23 | 2000-07-31 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置およびその製造方法 |
CN1574319A (zh) * | 2002-08-07 | 2005-02-02 | 三洋电机株式会社 | 电路装置及其制造方法 |
CN100492632C (zh) * | 2002-08-07 | 2009-05-27 | 三洋电机株式会社 | 电路装置及其制造方法 |
CN103681388A (zh) * | 2012-09-19 | 2014-03-26 | 瑞萨电子株式会社 | 制造半导体器件的方法 |
CN104064533A (zh) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | 一种双面半导体器件的qfn封装结构及方法 |
CN104485287A (zh) * | 2014-12-08 | 2015-04-01 | 宜兴市东晨电子科技有限公司 | 包含溢流槽的新型qfn框架的制备方法 |
CN204516748U (zh) * | 2015-04-15 | 2015-07-29 | 江苏晟芯微电子有限公司 | 一种功率器件的qfn封装结构 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7808089B2 (en) * | 2007-12-18 | 2010-10-05 | National Semiconductor Corporation | Leadframe having die attach pad with delamination and crack-arresting features |
JP5813335B2 (ja) * | 2011-02-08 | 2015-11-17 | 新光電気工業株式会社 | リードフレーム、半導体装置、リードフレームの製造方法及び半導体装置の製造方法 |
-
2015
- 2015-04-15 CN CN201510177211.7A patent/CN104779224B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3072291B1 (ja) * | 1999-04-23 | 2000-07-31 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置およびその製造方法 |
CN1574319A (zh) * | 2002-08-07 | 2005-02-02 | 三洋电机株式会社 | 电路装置及其制造方法 |
CN100492632C (zh) * | 2002-08-07 | 2009-05-27 | 三洋电机株式会社 | 电路装置及其制造方法 |
CN103681388A (zh) * | 2012-09-19 | 2014-03-26 | 瑞萨电子株式会社 | 制造半导体器件的方法 |
CN104064533A (zh) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | 一种双面半导体器件的qfn封装结构及方法 |
CN104485287A (zh) * | 2014-12-08 | 2015-04-01 | 宜兴市东晨电子科技有限公司 | 包含溢流槽的新型qfn框架的制备方法 |
CN204516748U (zh) * | 2015-04-15 | 2015-07-29 | 江苏晟芯微电子有限公司 | 一种功率器件的qfn封装结构 |
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CN104779224A (zh) | 2015-07-15 |
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Effective date of registration: 20160601 Address after: 215300 Jiangsu province north of the city of Yushan town of Kunshan city Hanpu Road No. 998, room 3 Applicant after: Suzhou Juda senchip Microelectronics Co. Ltd. Address before: 225500 hi tech innovation center, Jiangyan District, Taizhou, Jiangsu Applicant before: Jiangsu Senchip Microelectronics Co., Ltd. |
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Effective date of registration: 20180920 Address after: 215316 Han Po Road, hi tech Industrial Park, Kunshan Development Zone, Jiangsu (No. 998) Patentee after: Kunshan Juda Electronic Co., Ltd. Address before: 215300 room 3, Han Po Road, Yushan Town, Yushan Town, Kunshan, Jiangsu Patentee before: Suzhou Juda senchip Microelectronics Co. Ltd. |
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