JP5197953B2 - リードフレーム及びその製造方法、及び半導体装置 - Google Patents
リードフレーム及びその製造方法、及び半導体装置 Download PDFInfo
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- JP5197953B2 JP5197953B2 JP2006352872A JP2006352872A JP5197953B2 JP 5197953 B2 JP5197953 B2 JP 5197953B2 JP 2006352872 A JP2006352872 A JP 2006352872A JP 2006352872 A JP2006352872 A JP 2006352872A JP 5197953 B2 JP5197953 B2 JP 5197953B2
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- metal film
- lead frame
- die pad
- chip
- metal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 210
- 238000004519 manufacturing process Methods 0.000 title claims description 54
- 239000002184 metal Substances 0.000 claims abstract description 298
- 239000002313 adhesive film Substances 0.000 claims abstract description 95
- 238000003825 pressing Methods 0.000 claims abstract description 7
- 238000007789 sealing Methods 0.000 claims description 43
- 239000011347 resin Substances 0.000 claims description 40
- 229920005989 resin Polymers 0.000 claims description 40
- 239000000853 adhesive Substances 0.000 description 19
- 238000000034 method Methods 0.000 description 18
- 230000001070 adhesive effect Effects 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
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Description
図13は、本発明の第1の実施の形態に係るリードフレームの断面図である。図13において、Aは半導体チップが載置される領域(以下、「チップ載置領域」とする)を示している。
図20は、本発明の第2の実施の形態に係るリードフレームの平面図である。図20において、第1の実施の形態のリードフレーム10と同一構成部分には同一符号を付す。
図22は、本発明の第3の実施の形態に係るリードフレームの平面図である。図22において、第1の実施の形態のリードフレーム10と同一構成部分には同一符号を付す。
図26は、本発明の第4の実施の形態に係る半導体装置の断面図であり、図27は、図26に示す半導体装置の平面図である。図26及び図27において、先に説明した第1の実施の形態のリードフレーム10と同一構成部分には同一符号を付す。また、図27では、説明の便宜上、リードフレーム本体61上に設けられた封止樹脂63の図示を省略する。
図34は、本発明の第5の実施の形態に係る半導体装置の断面図であり、図35は、図34に示す半導体装置の平面図である。図34及び図35において、第4の実施の形態の半導体装置60と同一構成部分には同一符号を付す。また、図35では、説明の便宜上、リードフレーム本体61上に設けられた封止樹脂63の図示を省略する。
11 接着フィルム
12,61 リードフレーム本体
13 第1の金属膜
15,31,41 第2の金属膜
17 ダイパッド部
17A チップ載置面
17B,18B,19B,23A,63A 下面
18 リード部
18A,22A 上面
19 フレーム部
22 下部金型
23 上部金型
51 第3の金属膜
60,80 半導体装置
62,82 半導体チップ
63 封止樹脂
66 金属ワイヤ
67 接着剤
69 電極パッド
84 第1の金属ワイヤ
85 第2の金属ワイヤ
87 第1の電極パッド
88 第2の電極パッド
A チップ載置領域
B,D 半導体装置形成領域
C 切断領域
M1 厚さ
W1 幅
Claims (8)
- 半導体チップが載置されるチップ載置面を有する複数のダイパッド部と、前記複数のダイパッド部を支持するフレーム部と、前記フレーム部に設けられ、前記複数のダイパッド部をそれぞれ囲むように配置された複数のリード部とを有するリードフレーム本体と、
前記半導体チップが載置される側とは反対側に位置する前記リードフレーム本体の面に貼り付けられた接着フィルムと、
前記接着フィルムが設けられた側とは反対側に位置する前記リード部の上面に設けられ、第1の金属ワイヤを介して前記半導体チップと電気的に接続される第1の金属膜と、を備えたリードフレームであって、
前記複数のダイパッド部の前記チップ載置面は、前記半導体チップが載置されるチップ載置領域を有し、
前記複数のダイパッド部の前記チップ載置領域の中央部を含む前記チップ載置領域の一部に、前記第1の金属膜と厚さの略等しい第2の金属膜を設け、
前記複数のリード部の前記上面を除く面は前記第1の金属膜から露出しており、前記複数のダイパッド部の前記チップ載置面を除く面は前記第2の金属膜から露出していることを特徴とするリードフレーム。 - 前記複数のダイパッド部の前記チップ載置領域の外側に位置する部分の前記チップ載置面に、前記第1の金属膜と厚さの略等しい第3の金属膜を設け、
第2の金属ワイヤを介して、前記第3の金属膜と前記半導体チップとが電気的に接続されることを特徴とする請求項1記載のリードフレーム。 - 半導体チップが載置されるチップ載置面を有する複数のダイパッド部と、前記複数のダイパッド部を支持するフレーム部と、前記フレーム部に設けられ、前記複数のダイパッド部をそれぞれ囲むように配置された複数のリード部とを有するリードフレーム本体と、
前記半導体チップが載置される側とは反対側に位置する前記リードフレーム本体の面に貼り付けられた接着フィルムと、
前記接着フィルムが設けられた側とは反対側に位置する前記リード部の上面に設けられ、第1の金属ワイヤを介して前記半導体チップと電気的に接続される第1の金属膜と、を備え、
前記複数のダイパッド部の前記チップ載置面は、前記半導体チップが載置されるチップ載置領域を有し、
前記複数のリード部の前記上面を除く面は前記第1の金属膜から露出しており、前記複数のダイパッド部の前記チップ載置面を除く面は前記第2の金属膜から露出しているリードフレームの製造方法であって、
前記第1の金属膜を形成する第1の金属膜形成工程と、
前記複数のダイパッド部の前記チップ載置領域の中央部を含む前記チップ載置領域の一部に、前記第1の金属膜と厚さの略等しい第2の金属膜を形成する第2の金属膜形成工程と、
前記第1及び第2の金属膜形成後に、押圧により前記接着フィルムを前記リードフレーム本体に貼り付ける接着フィルム貼付工程と、を含むことを特徴とするリードフレームの製造方法。 - 前記第1及び第2の金属膜を同時に形成することを特徴とする請求項3に記載のリードフレームの製造方法。
- 前記複数のダイパッド部の前記チップ載置領域の外側に位置する部分の前記チップ載置面に、第2の金属ワイヤを介して前記半導体チップと電気的に接続される第3の金属膜を形成する第3の金属膜形成工程をさらに設け、
前記第3の金属膜の厚さを前記第1の金属膜の厚さと略等しくしたことを特徴とする請求項3記載のリードフレームの製造方法。 - 前記第1の金属膜、前記第2の金属膜、及び前記第3の金属膜を同時に形成することを特徴とする請求項5に記載のリードフレームの製造方法。
- 半導体チップと、
前記半導体チップが載置されるチップ載置面を有するダイパッド部と、前記ダイパッド部を囲むように設けられたリード部とを有するリードフレーム本体と、
前記リード部の上面に設けられ、第1の金属ワイヤを介して前記半導体チップと電気的に接続される第1の金属膜と、
前記リードフレーム本体に設けられ、前記半導体チップを封止する封止樹脂と、を備えた半導体装置であって、
前記ダイパッド部の前記チップ載置面は、前記半導体チップが載置されるチップ載置領域を有し、
前記ダイパッド部の前記チップ載置領域の中央部を含む前記チップ載置領域の一部に、前記第1の金属膜と厚さが略等しい第2の金属膜を設け、
前記リード部の前記上面を除く面は前記第1の金属膜から露出しており、前記ダイパッド部の前記チップ載置面を除く面は前記第2の金属膜から露出していることを特徴とする半導体装置。 - 前記第2の金属膜の外側に位置する部分の前記チップ載置面に、第2の金属ワイヤを介して前記半導体チップと電気的に接続される第3の金属膜を設け、
前記第3の金属膜の厚さを前記第1及び第2の金属膜の厚さと略等しくしたことを特徴とする請求項7記載の半導体装置。
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