CN1677665A - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

Info

Publication number
CN1677665A
CN1677665A CNA2005100061059A CN200510006105A CN1677665A CN 1677665 A CN1677665 A CN 1677665A CN A2005100061059 A CNA2005100061059 A CN A2005100061059A CN 200510006105 A CN200510006105 A CN 200510006105A CN 1677665 A CN1677665 A CN 1677665A
Authority
CN
China
Prior art keywords
passive component
conductive pattern
circuit arrangement
separating tank
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005100061059A
Other languages
English (en)
Inventor
加藤敦史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1677665A publication Critical patent/CN1677665A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
    • B26F3/00—Severing by means other than cutting; Apparatus therefor
    • B26F3/04—Severing by squeezing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D1/00—Cutting through work characterised by the nature or movement of the cutting member or particular materials not otherwise provided for; Apparatus or machines therefor; Cutting members therefor
    • B26D1/0006—Cutting members therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D1/00—Cutting through work characterised by the nature or movement of the cutting member or particular materials not otherwise provided for; Apparatus or machines therefor; Cutting members therefor
    • B26D1/0006—Cutting members therefor
    • B26D2001/0066—Cutting members therefor having shearing means, e.g. shearing blades, abutting blades
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Forests & Forestry (AREA)
  • Mechanical Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一种电路装置及其制造方法，在电路装置上安装无源元件时，由于电极部进行镀锡，故利用安装接合部焊料进行固定，不能以单层结构使配线交叉，存在安装面积扩大、或在印刷线路板上安装时回流温度的限制、由封装后的焊锡裂纹引起的可靠性恶化的问题。将无源元件的电极部镀金，在电极部上直接固定接合引线。由此，谋求安装密度的提高。另外，即使是通过采用不使用支承衬底的封装结构，在分离槽上粘接无源元件，而固定接合引线的结构，也可以抑制封装件厚度的增大。

Description

电路装置及其制造方法
技术领域
本发明涉及含有无源元件的电路装置及其制造方法，特别是涉及提高了配线密度的电路装置及其制造方法。
背景技术
参照图9说明现有的电路元件。图9(A)是电路装置的平面图，图9(B)是图9(A)的B-B线剖面图。
如图9(A)，在例如支承衬底110上的规定封装区域120上配置例如IC等半导体元件101和多个导电图案103。导电图案103具有固定接合引线108等的焊盘部103a及/或固定无源元件106的两电极部107的安装接合部103b。无源元件是例如片状电容、无源元件等。
无源元件106和半导体元件101介由导电图案103连接。即利用焊锡等焊料160将无源元件106的电极部107固定在安装接合部103b上，并从安装接合部103b延长导电图案103。然后，利用接合引线108等连接焊盘部103a和半导体元件101的电极焊盘102。另外，无源元件106相互之间通过两端具有安装接合部103b的导电图案103连接。
如图9(B)，无源元件106的端部侧面镀锡，形成电极部107。而且，在安装无源元件106时，通过焊锡等焊料(或导电性粘接剂)将其固定在安装接合部103b(导电图案103)上(例如参照专利文献1)。
专利文献1：特开2003-297601号公报
无源元件106的电极部107由廉价的镀锡构成。而且，由于锡的熔点低，而不能进行高温热压装，故在安装无源元件106时，利用焊料(或导电性粘接剂)106将其固定在导电图案103上。
特别是，在进行采用焊料160的安装时，会在电极部107上形成由焊料160构成的焊痕。因此，为了使无源元件106与半导体元件101或其他无源元件、或导电图案103电连接，必须在无源元件106的电极部107下方设置比电极部107大的安装接合部103b。或设置具有接合引线108连接的焊盘部103a的导电图案103。由此，安装面积不能缩小，安装无源元件106的电路装置的制品的安装密度降低。
另外，在配线复杂，且导电图案103交叉设置时，需要如图9(A)虚线所示必须采用多层结构，并介由通孔TH连接，或在单层结构时，将导电图案103大幅度迂回配置。即，为了连接无源元件，而必须增加成本或工时数，构成多层结构，或进一步扩大安装面积。
另外，在通过焊料、特别是焊锡进行固定时，特别是在具有树脂密封的结构的装置中具有如下问题。
不能将例如在印刷线路板等上安装时的回流温度设为焊锡的熔点以上。这是由于当形成焊锡的熔点以上的回流温度时，焊锡的再熔融会造成短路或封装破坏。
另外，在因树脂密封后的热量封装件产生变形时，焊锡或Ag膏上会产生裂纹，使焊锡、Ag膏等可靠性降低。
另外，在固定装置使用以锡为主成分的无铅焊锡的电路装置还有问题。例如，在由无铅焊锡固定封装件的外部端子(外部电极)和印刷线路板等安装衬底时，或由焊锡形成外部电极本身时，若在封装件内部的固定使用焊锡，则必须使该焊锡比无铅焊锡的熔点高。但是，采用高熔点焊锡进行的安装存在破坏元件等问题。
另外，在封装件内部的固定采用无铅焊锡时，封装件外部的固定装置为采用低熔点的焊锡安装，固定强度不完善。
另外，无铅焊锡的种类少，都没有熔点差。即，当利用无铅焊锡固定封装件内的无源元件，且外部端子(外部电极)也利用无铅焊锡固定在安装衬底上时，内部的无铅焊锡会产生再熔融。
发明内容
本发明的第一方面提供一种电路装置，其包括：被埋入绝缘树脂内的导电图案；与该导电图案电连接的半导体元件；接合引线；被埋入所述绝缘树脂的除埋入所述导电图案的区域以外的区域，且两侧面设置了电极部的无源元件，其中，所述无源元件的底面位于所述导电图案的表面下方，并在所述无源元件的电极部固定所述接合引线的一端。
另外，所述导电图案、半导体元件、无源元件及接合引线被所述绝缘树脂覆盖，并被一体地支承。
所述无源元件的底面粘接粘接材料。
所述无源元件底面的所述粘接材料和所述导电图案的背面露出在同一面上。
所述接合引线的另一端被连接在所述半导体元件或所述导电图案上。
所述接合引线的另一端被固定在其它所述无源元件的电极部上。
所述无源元件的电极部镀金。
另外，在被固定与所述无源元件上的接合引线的下方配置所述导电图案的一部分。
本发明的第二方面提供一种电路装置的制造方法，包括：准备导电箔，至少在构成电路元件的封装区域的所述导电箔上形成比该导电箔的厚度浅的分离槽，形成利用该分离槽分离的导电图案的工序；在所述分离槽上粘接无源元件的工序；在所述无源元件的电极部固定接合引线的一端，并将另一端固定在所述半导体元件或所述导电图案或其它无源元件上的工序；利用绝缘树脂共通模制，将所述电路元件的封装区域整体覆盖，并填充所述分离槽的工序；蚀刻所述分离槽下方的所述导电箔直至所述分离槽，将所述导电图案一一分离，同时从所述导电图案分离所述无源元件的工序；通过切割而按每个所述电路元件的封装区域分离所述绝缘树脂的工序。
另外，所述无源元件通过蚀刻所述分离槽下方露出所述粘接材料。
所述导电箔由铜、铝、铁镍的任意一种构成。
通过化学或物理蚀刻形成选择性地形成在所述导电箔上的所述分离槽。
另外，所述接合引线被热压装在所述无源元件的电极部上。
在本发明中，可得到如下所示的效果。
第一，可利用接合引线将无源元件、半导体元件、导电图案或其它无源元件直接电连接。即，可不需要用于固定无源元件电极部的安装接合部或用于和半导体元件的电极焊盘连接的焊盘部，而实现安装面积的降低。
第二，由于通过在无源元件上直接固定接合引线来实现和其它构成要素的电连接，故可在该接合引线的下方配置导电图案的一部分。目前，由于利用导电图案连接无源元件和其它构成要素，故在与连接在无源元件上的导电图案交叉时，必须构成两层配线，但根据本发明，这可通过单层来实现，可提高安装密度。
第三，无源元件一般比半导体元件厚，当实现采用接合引线的电连接时，回线高度增高，但可通过在导电图案表面的下方粘接无源元件抑制封装件厚度的增大。具体地说，由于可通过采用未使用安装衬底的封装件并在分离槽内粘接无源元件降低导电图案的厚度，故即使采用接合引线也可以降低回路高度，可将封装件的厚度薄型化。
第四，由于无源元件的安装使用粘接剂或粘接片，故可消除在印刷线路板上安装电路装置的模块时将回流温度设为焊锡的熔点以下的限制。
第五，由于可不使用焊料来固定，故可防止由树脂封装件的应力产生的焊料的开裂，提高可靠性。
第六，由于在无源元件的侧面部不形成由焊料构成的焊痕，故可减小无源元件的安装面积，可提高装置整体的安装密度。
第七，在固定装置使用无铅焊锡的电路装置中，外部端子(外部电极)和安装衬底的固定可采用无铅焊锡。或外部电极自身可采用无铅焊锡。
由于无铅焊锡的种类少，没有熔点差，故不能在封装件内部和封装件外部两侧使用无铅焊锡。根据本实施例，由于利用接合引线进行封装件内部无源元件的电连接，故可在外部端子和安装衬底的连接时采用无铅焊锡。
第八，由于不需要为进行现有无源元件的电连接而必要的安装接合部，故可接近半导体元件配置无源元件。因此，例如无源元件采用片状电容等时噪声的吸收良好。
另外，根据本发明的制造方法，分离导电图案的分离槽在制造工序的初期阶段具有底部，导电图案是连续的导电箔，可在其底部粘接无源元件。分离槽底部是制造工序中除去的部分，可通过以规定厚度的粘接剂固定无源元件在导电图案间配置无源元件，并通过绝缘树脂支承。例如，在支承衬底上进行安装时，半导体元件和无源元件的安装面构成同一面，封装件厚度增大。但是，根据本实施例，可将无源元件的固定面设置在导电图案表面(半导体元件的固定面)的下方。由此，即使将比较厚的无源元件与半导体元件集成时，也可以使封装件薄型化。
按每个封装区域进行分离的切割仅切断绝缘树脂层即可，而不切断导电箔，从而可以使切割片的寿命增长。且也不产生切断导电箔时产生的金属毛刺。
另外，由于与在陶瓷衬底上安装时比较，可省略通孔形成工序、导体印刷工序(陶瓷衬底时)等，故与现有技术相比，具有可大幅缩短制造工序的优点。另外，也不需要结构模具，是交货期极短的制造方法。
附图说明
图1是本发明电路装置的平面图(A)、剖面图(B)；
图2是说明本发明电路装置制造方法的剖面图(A)、平面图(B)；
图3是说明本发明电路装置制造方法的剖面图；
图4是说明本发明电路装置制造方法的剖面图(A)、平面图(B)；
图5是说明本发明电路装置制造方法的剖面图；
图6是说明本发明电路装置制造方法的剖面图；
图7是说明本发明电路装置制造方法的剖面图(A)、平面图(B)；
图8是说明本发明电路装置制造方法的剖面图；
图9是现有电路装置的平面图(A)、剖面图(B)。
符号说明
1    半导体元件
2    电极焊盘
3    导电图案
3a   焊盘部
6    无源元件
7    电极部
8    接合引线
9    粘接材料
10   电路装置
20   封装区域
31   绝缘树脂
33   绝缘树脂
34   背面电极
101  半导体元件
102  电极焊盘
103   导电图案
103a  焊盘部
103b  安装接合部
106   无源元件
107   电极部
108   接合引线
110   支承衬底
TH    通孔
具体实施方式
参照图1～图8说明本发明电路装置的一实施例。
图1是本实施例电路装置的图示，图1(A)是平面图，图1(B)是图1(A)的A-A线剖面图。
本实施例的电路装置10由半导体元件1、导电图案2、无源元件6、接合引线8构成。
如图1(A)，本实施例的电路装置10中，在虚线所示的封装区域20内，至少将IC等半导体元件1及导电图案3和无源元件6埋入绝缘树脂内并由绝缘树脂支承，构成规定的电路。导电图案3端部具有固定接合引线8的焊盘部3a。
在本实施例中，无源元件6是指例如片状电阻器、片状电容、电感、热敏电阻、天线、振荡器等元件两端具有电极部7的片状元件。电极部7在细长形成的无源元件6的两端部形成，且电极部7的表面镀金。而且，无源元件6被例如绝缘性粘接材料粘接在封装区域20内的未配置导电图案3的区域。
在本实施例中，是将无源元件6的电极部7由焊料或Ag膏直接固定在导电图案(安装接合部)上，而且通过将接合引线8的一端固定在电极部7上实现电连接。
在无源元件6上固定的接合引线8的另一端连接在半导体元件1的电极焊盘2及/或导电图案3的焊盘部3a上。或利用接合引线8连接无源元件6的电极部7相互之间。
因此，电极部7实施了镀金，以使电极部7可利用接合引线8接合，即通过接合引线8的材料(Au或Al等)决定电极部7最表面的金属。
即，这有利于无源元件6不使用焊料或Ag膏等，而使用金属细线连接的情况。
由此，不再需要目前固定无源元件电极部的安装接合部103b(图9的虚线圆标记)。即，作为导电图案3的焊盘部3a不是可固定电极部7的尺寸，只要可确保可进行引线接合的面积即可。
另外，在本实施例中，在连接从半导体元件1远离的位置的无源元件6和半导体元件1时，也可以使导电图案3环绕。因此，必须设置接近半导体元件1的电极焊盘2的焊盘部3a(图1(A)的虚线圆标记)，在此进行引线接合。但是，即使在这样环绕导电图案3时，也可以将例如导电图案3配置在与无源元件6连接的接合引线8的下方。即可防止安装面积的增大。
另外，参照图1(B)的剖面图说明半导体元件1及无源元件6的状态。
半导体元件1根据用途被导电性或绝缘性的粘接剂等固定在构成岛的导电图案3上。
如前所述，无源元件6被粘接材料9粘接在封装区域20内的导电图案3以外的区域。另外，由后述可知，本实施例的无源元件6虽然粘接在粘接剂上，但利用绝缘树脂31支承。
无源元件6的粘接剂是粘接树脂或粘接片。即，与焊料160不同，不形成焊痕。因此，在安装无源元件6时，必要的安装面积与无源元件6的平面大小程度相同。
如图所示，无源元件6和半导体元件1在接近的位置利用接合引线8直接连接。
另外，可在一端固定于无源元件6的接合引线8的下方配置导电图案3的一部分。目前，在配线象这样交叉时，必须将导电图案形成多层配线结构，介由通孔连接，但在本实施例中可利用单层结构进行配线交叉。
这样，在本实施例中，在无源元件6上固定接合引线8来实现电连接，但特别是片状电容等无源元件6的厚度一般比半导体元件1厚。因此，当粘接在与半导体元件1同一面，即与半导体元件1同样地粘接在导电图案3上时，在导电图案3的厚度和无源元件6的厚度上，增加接合引线8的回线高度形成的厚度构成电路装置10的高度，封装厚度增大。
因此，在本实施例中采用不具有安装衬底的封装结构，在导电图案3表面的下方固定无源元件6。
由此，由于可在下方固定导电图案3的厚度量的无源元件6，故可不增厚封装件厚度而安装本实施例的电路装置。
以下进一步详述，如图所示，导电图案3被埋入绝缘树脂31内，并由其支承，且背面自绝缘树脂31流出。此时，导电图案3是以Cu为主材料的导电箔、以Al为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。
如后所详述的，在导电图案3间通过半蚀刻设置分离槽32，并在分离槽32内填充绝缘树脂31，使其与导电图案侧面嵌合来实现牢固的结合。即，绝缘树脂31使导电图案3的背面露出来密封电路装置10的整体，在此，是密封半导体元件1、无源元件6、接合引线8。
绝缘树脂31可采用通过传递模模制形成的热硬性树脂或通过注入模模制形成的热塑性树脂。具体地说，可使用环氧树脂等热硬性树脂、聚酰亚胺树脂、硫化聚苯等热塑性树脂。另外，绝缘树脂只要是可使用模具固定的树脂、可进行浸渍、涂敷覆盖的树脂，则可采用所有树脂。在该封装件中，绝缘树脂31密封半导体元件1等，同时还具有支承电路装置整体的作用。这样，通过利用绝缘树脂31密封整体，可防止半导体元件1自导电图案3分离。
半导体元件1根据其用途由绝缘性或导电性粘接剂9固定在封装区域20内的导电图案3表面，接合引线8的一端热压装在电极焊盘上，另一端与导电图案3或无源元件6连接。
无源元件6利用粘接剂9被粘接在封装区域20内的导电图案3以外的区域，即分离槽32内。另外，如前所述的粘接是制造工序上的粘接，粘接无源元件6的是在分离槽32下方的最终结构中除去的导电箔。
即分离槽32是最终作为绝缘树脂31的背面露出的部分，在无源元件6的下方粘接剂9与导电图案3的背面在同一面上露出。即无源元件6被绝缘树脂31支承。
接合引线8的一端直接固定在无源元件6的电极部7上，另一端与半导体元件1的电极焊盘、导电图案3、其他无源元件6的电极部7的任意一者连接。
另外，调整绝缘树脂31的厚度，以使其从电路装置20的接合引线8的最顶部起覆盖大约100μm左右厚。该厚度考虑强度既可增厚，也可以减薄。
在本实施例中，无源元件6以导电图案3的厚度量被配置在半导体元件1的下方。因此，即使在比半导体元件1厚(高)的无源元件6上固定接合引线8，也可以抑制封装件厚度的增大。
另外，可在例如固定于无源元件6上的接合引线8的下方配置导电图案3的一部分，以单层结构实现交叉的配线。
绝缘树脂31的背面和导电图案3的背面、无源元件6的粘接剂9的背面形成实际上一致的结构。而且，在背面设置将所希望的区域开口的绝缘树脂33。然后，在露出的导电图案3上被覆焊锡等导电材料，形成背面电极34，完成电路装置10。
此时，构成背面电极34的一部分并作为和安装衬底连接的连接装置的焊锡可采用以锡为主成分的无铅焊锡。无铅焊锡的种类少，熔点无太大差异。因此，在图中所示的结构中，若封装件内部的固定装置也使用无铅焊锡，则在将封装件固定在安装衬底上后，封装件内部的无铅焊锡就会再熔融。但是，在本实施例中，封装件内部的无源元件6被不再熔融的粘接材料(粘接剂9)固定，并通过接合引线实现电连接。即背面电极34可使用无铅焊锡。
以下参照图2～图8说明本发明电路装置的制造方法。
本发明电路装置的制造方法包括：准备导电箔，至少在作为电路元件的封装区域的导电箔上形成比导电箔的厚度浅的分离槽，并形成由分离槽分离的导电图案的工序；在分离槽上粘接无源元件的工序；将接合引线的一端固定在无源元件的电极部，并将另一端固定在半导体元件或导电图案或其它无源元件上的工序；利用绝缘树脂共通模制，将电路元件的封装区域整体覆盖，并填充分离槽的工序；蚀刻分离槽下方的导电箔直至到达所述分离槽，将导电图案一个个分离，同时从所述导电图案分离无源元件的工序；通过切割按每个电路元件的封装区域分离绝缘树脂的工序。
第一工序(参照图2～图4)：准备导电箔，至少在构成电路元件的封装区域的导电箔上形成比导电箔的厚度浅的分离槽，形成利用分离槽分离的导电图案的工序。
首先，如图2(A)，准备片状的导电箔30。考虑粘接剂9的粘附性、接合性、镀附性来选择该导电箔30的材料，材料采用以Cu为主材料的导电箔、以Al为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。另外，也可以是其它的导电材料，最好为可蚀刻的导电材料。
导电箔30的厚度考虑到之后的蚀刻最好为10μm～300μm程度，在此采用了70μm(2盎司)的铜箔。但是，基本上也可以采用300μm以上或10μm以下的导电箔。只要可形成比导电箔30的厚度浅的分离槽32即可，这一点将后述。
另外，片状导电箔30可以以规定的宽度例如45mm被卷成筒状准备，并将其运送到后述的各工序，也可以准备截割成规定大小的长方形状导电箔30，运送到后述的各工序。
具体地说，如图2(B)所示，在长方形状导电箔30上间隔排列配置4～5个形成多个封装区域的块42。在各块42间设置缝隙43，吸收由模制工序等的加热处理产生的导电箔30的应力。另外，在导电箔30的上下周端以一定的间隔设置定位孔44，其用于各工序中的定位。
然后，形成每块的导电图案3。
首先，如图3所示，在Cu箔30上形成光致抗蚀剂(耐蚀刻掩膜)PR，构图光致抗蚀剂PR，以使除形成导电图案3的区域以外的导电箔30露出。
然后，如图4(A)所示，介由光致抗蚀剂PR选择地蚀刻导电箔30。
由蚀刻形成的分离槽32的深度例如为50μm，其侧面或底面形成粗糙面，以提高和之后工序中形成的绝缘树脂31或粘接剂9的粘接性。
另外，该分离槽32的侧壁虽然示意性地以直线形图示，但根据除去方法不同而形成不同的结构。该除去工序可采用湿蚀刻、干蚀刻、切割进行。湿蚀刻时，蚀刻剂主要采用氯化铁或氯化铜，所述导电箔在该蚀刻剂中被浸渍，或由该蚀刻剂进行喷射。在此，由于湿蚀刻通常为非各向异性蚀刻，故侧面形成弯曲结构。
干蚀刻时，可以各向异性、非各向异性进行蚀刻。虽然目前通常认为，不能通过反应性离子蚀刻清除Cu，但可通过溅射除去。另外，根据溅射的条件，可通过各向异性、非各向异性蚀刻。
另外，在图3中，也可以选择性地覆盖对蚀刻液具有耐蚀性的导电覆膜(未图示)以代替光致抗蚀剂。如在构成导电路的部分选择性地被覆，则该导电覆膜形成蚀刻保护膜，可不采用抗蚀剂而蚀刻分离槽。该导电覆膜的材料是Ag、Ni、Au、Pt或Pd等。并且，这些耐蚀性导电覆膜具有可直接活用为小焊盘、接合焊盘的特征。
例如使Ag覆膜与Au粘接。由此，如在芯片背面覆盖Au覆膜，则可直接在导电图案3上的Ag覆膜上热压装芯片。另外，由于可在Ag导电覆膜上粘接Au细线，故也可以进行引线接合。因此，这些导电覆膜具有可直接活用作小焊盘、接合焊盘的优点。
图4(B)表示具体的导电图案3之一例。本图对应放大图2(B)所示的一个块42的图例。涂黑的部分是导电图案3。另外，虚线区域是构成一个电路装置10的封装区域20，在一个块42上将多个封装区域20配列为5行10列的矩阵状，并在每个封装区域20上设置相同的导电图案3。在各块的周边设置框状图案46，与稍稍离开，在其内侧设置切割时的定位标记47。柜状图案46用于和模制模具的嵌合，还具有在导电箔30的背面蚀刻后增强绝缘树脂31的作用。
第二工序(参照图5)：在分离槽内粘接无源元件的工序。
首先，如图5所示，在所希望的导电图案(接合部)3上固定半导体元件1。在此，裸的半导体元件1利用导电性或绝缘性的粘接剂等装在导电图案3上。
然后，利用例如绝缘性粘接剂9在分离槽32底部粘接无源元件6。另外，只要可涂敷在各电极部7使无源元件6的电极部7相互之间绝缘，则也可以利用导电性粘接剂9。在此，粘接剂9的厚度t1比在之后的工序中用于将导电箔30分离为各个导电图案3的从起自背面的蚀刻的精加工线(X)到无源元件6底面的高度(t2)更厚。由此，在之后的工序中，在蚀刻分离槽32下方的导电箔30，一个个分离导电图案3，同时露出导电图案3背面的工序中，无源元件6自导电图案3分离，在背面露出粘接剂9。
第三工序(参照图6)：将接合引线的一端固定在无源元件的电极部，并将另一端固定在半导体元件或导电图案或其它无源元件上的工序。
半导体元件1的电极焊盘与所希望的导电图案3电连接。即利用Au、Al等接合引线8的热压装等连接电极焊盘和导电图案3的焊盘部3a。
另外，在本实施例中，不将无源元件6固定在导电图案3上，而利用接合引线8来实现与其它的构成要素的电连接。无源元件6的电极部7上镀金，并可通过热压装Au、Al等接合引线进行连接。由此，由于不再需要用于固定无源元件6的导电图案3(安装接合面)，也可以交叉配线，故可实现安装面积的降低。
另外，在本实施例中，由于无源元件6的电连接是使用Au、Al等接合引线进行热压装，故半导体元件1也选择相同的连接方法。但是，本发明不限于此，半导体元件1也可以利用基于超声波的楔焊等由其它金属细线固定。
另外，由于如前所述无源元件6比半导体元件1的厚度厚，故当粘接在导电图案3上时，有可能因无源元件6本身的厚度或接合引线8的回线高度等增大封装件厚度。但是，通过如本实施例所述粘接在分离槽32上可降低导电图案3的量的厚度。
在本工序中，由于在各块42上集成有多个导电图案3，故具有可极高效地进行电路元件10的固定及引线接合的优点。
第四工序(参照图7)：利用绝缘树脂将电路元件的封装区域整体覆盖，并填充分离槽进行共通模制的工序
首先，如图7(A)所示，绝缘树脂31完全覆盖封装区域内的半导体元件1、无源元件6、导电图案3、接合引线8。而且，在导电图案3的分离槽32内填充绝缘树脂31，使其与导电图案3的侧面的弯曲构造嵌合而牢固地接合。然后，由绝缘树脂31支承导电图案3。
在本工序中，可通过传递模模制、注入模模制或浸渍实现。作为树脂材料，环氧树脂等热硬性树脂可利用传递模模制实现，聚酰亚胺树脂、硫化聚苯等热塑性树脂可利用注入模模制实现。
另外，在本工序中，在进行传递模模制或注入模模制时，如图7(B)所示，各块42在一个通用的模制模具60中装入封装区域20，并按每个块利用一个绝缘树脂31共通地进行模制。因此，与如现有的传递模模制等那样分别模制各封装区域20的方法相比，可实现树脂量的大幅消减，实用模制模具的通用化。
调整覆盖在导电箔30表面上的绝缘树脂31的厚度，从电路元件10的接合引线8的最顶端起覆盖大约100μm左右。该厚度也可以根据强度加厚或减薄。
此时，与半导体元件1相比，较厚的无源元件6被粘接在分离槽32底部，故可将其以导电图案3的厚度量固定在半导体元件1的下方，可抑制接合引线8最顶端的高度增大。
另外，在覆盖绝缘树脂31之前，作为导电图案3的导电箔30形成支承衬底。作为支承衬底的导电箔30是作为电极材料必要的材料。因此，具有可极其节省构成材料而作业的优点，也可以实现成本的降低。
由于分离槽32形成得比导电箔的厚度浅，故导电箔30没有作为导电图案3被一一分离。因此，片状导电箔30可一体处理，在模制绝缘树脂31时，向模具的运送、向模具的安装操作是非常方便的。
第五工序(参照图8)：蚀刻分离槽下方的导电箔直至到达所述分离槽，一一分离导电图案，同时从所述导电图案分离无源元件的工序。
在本工序中，湿蚀刻导电箔30直至分离槽32下方的导电箔30到达分离槽，即直至图7中虚线所示的蚀刻精加工线X。此时，由于粘接剂9的厚度t1形成得比从无源元件6的底部到蚀刻的精加工的予定线X的距离t2厚(图7)，故通过进行蚀刻，以一一分离导电图案3，除去分离槽32下方的导电箔30，将无源元件6从导电图案3分离，在绝缘树脂31的背面露出粘接剂9。然后，无源元件6上虽然粘接3粘接剂9，但由于除去了作为被粘接件的导电箔30，故实际上通过绝缘树脂31支承。
另外，该蚀刻的结果导电图案3形成以大约40μm的厚度被分离，并在绝缘树脂31上露出导电图案3的背面的结构。
即，被填充入分离槽32的绝缘树脂31背面和导电图案3背面及无源元件6的粘接剂9背面形成实际上一致的结构。因此，本发明的电路装置10具有在安装时可利用焊锡等的表面张力直接水平移动而自调节的特征。
第六工序(参照图1(B))：通过按每个电路元件的封装区域切割绝缘树脂进行分离的工序。
再进行导电图案3的背面处理。即，在由于必要而露出的导电图案51上被覆焊锡等导电材料，形成背面电极34。背面电极34可采用例如无铅焊锡。然后，通过按每个封装区域20上切割绝缘树脂31而一一分离，完成电路装置10。
另外，在本实施例中说明了在导电图案3上固定半导体元件1的例子，但本发明不限于此，例如在衬底为浮置的半导体元件1的情况下，也可以与无源元件6同样将半导体元件1固定在分离槽32部分。

Claims (13)

1、一种电路装置，其特征在于，包括：被埋入绝缘树脂内的导电图案；与该导电图案电连接的半导体元件；接合引线；无源元件，被埋入所述绝缘树脂的除埋入有所述导电图案的区域以外的区域，且两侧面设置有电极部的，其中，所述无源元件的底面位于所述导电图案的表面下方，并在所述无源元件的电极部固定所述接合引线的一端。
2、如权利要求1所述的电路装置，其特征在于，所述导电图案、半导体元件、无源元件及接合引线被所述绝缘树脂覆盖并一体支承。
3、如权利要求1所述的电路装置，其特征在于，在所述无源元件的底面粘接粘接材料。
4、如权利要求1所述的电路装置，其特征在于，所述无源元件底面的所述粘接材料和所述导电图案背面在同一面露出。
5、如权利要求1所述的电路装置，其特征在于，所述接合引线的另一端连接在所述半导体元件或所述导电图案上。
6、如权利要求1所述的电路装置，其特征在于，所述接合引线的另一端固定在其它所述无源元件的电极部上。
7、如权利要求1所述的电路装置，其特征在于，所述无源元件的电极部镀金。
8、如权利要求1所述的电路装置，其特征在于，在被固定于所述无源元件的接合引线的下方配置导电图案的一部分。
9、一种电路装置的制造方法，其特征在于，包括：准备导电箔，至少在作为电路元件的封装区域的所述导电箔上形成比该导电箔的厚度浅的分离槽，并形成利用该分离槽分离的导电图案的工序；在所述分离槽上粘接无源元件的工序；在所述无源元件的电极部固定接合引线的一端，并将另一端固定在所述半导体元件或所述导电图案或其它无源元件上的工序；将所述电路元件的封装区域全部覆盖，并利用绝缘树脂填充所述分离槽共通模制的工序；蚀刻所述分离槽下方的所述导电箔直至所述分离槽，将所述导电图案一个个分离，同时从所述导电图案分离所述无源元件的工序；通过切割按每个所述电路元件的封装区域分离所述绝缘树脂的工序。
10、如权利要求9所述的电路装置的制造方法，其特征在于，所述无源元件通过蚀刻所述分离槽下方露出所述粘接材料。
11、如权利要求9所述的电路装置的制造方法，其特征在于，所述导电箔由铜、铝、铁镍的任意一种构成。
12、如权利要求9所述的电路装置的制造方法，其特征在于，通过化学或物理蚀刻形成选择性地形成在所述导电箔上的所述分离槽。
13、如权利要求9所述的电路装置的制造方法，其特征在于，所述接合引线被热压装在所述无源元件的电极部上。
CNA2005100061059A 2004-03-29 2005-01-28 电路装置及其制造方法 Pending CN1677665A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP096959/2004 2004-03-29
JP2004096959A JP2005286057A (ja) 2004-03-29 2004-03-29 回路装置およびその製造方法

Publications (1)

Publication Number Publication Date
CN1677665A true CN1677665A (zh) 2005-10-05

Family

ID=34988800

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005100061059A Pending CN1677665A (zh) 2004-03-29 2005-01-28 电路装置及其制造方法

Country Status (5)

Country Link
US (1) US20050212107A1 (zh)
JP (1) JP2005286057A (zh)
KR (1) KR20050096851A (zh)
CN (1) CN1677665A (zh)
TW (1) TWI259507B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009269B (zh) * 2006-01-24 2010-05-12 富士通微电子株式会社 半导体器件及其制造方法
CN101179066B (zh) * 2006-11-10 2010-05-12 全懋精密科技股份有限公司 芯片嵌埋式封装结构
CN106356358A (zh) * 2015-07-13 2017-01-25 艾马克科技公司 半导体封装及其制造方法
CN109273504A (zh) * 2018-09-27 2019-01-25 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100809691B1 (ko) * 2006-07-28 2008-03-06 삼성전자주식회사 수동 소자를 구비한 반도체 패키지 및 이것으로 구성되는반도체 메모리 모듈
KR101251659B1 (ko) * 2006-09-20 2013-04-05 엘지이노텍 주식회사 인쇄회로기판과 인쇄회로기판을 이용한 피씨비 카드,그리고 인쇄회로기판의 제조방법 및 ｐｃｂ 카드의제조방법
KR101251660B1 (ko) * 2006-09-20 2013-04-05 엘지이노텍 주식회사 인쇄회로기판과 인쇄회로기판을 이용한 피씨비 카드,그리고 인쇄회로기판의 제조방법 및 ｐｃｂ 카드의제조방법
KR100764684B1 (ko) * 2006-11-01 2007-10-08 인티그런트 테크놀로지즈(주) 반도체 패키지 제조방법, 반도체 장치 및 그 제조방법
US7911044B2 (en) * 2006-12-29 2011-03-22 Advanced Chip Engineering Technology Inc. RF module package for releasing stress
JP2009038111A (ja) * 2007-07-31 2009-02-19 Toshiba Corp 半導体パッケージ、プリント配線板構造および電子機器
JP5375891B2 (ja) * 2011-08-01 2013-12-25 富士通セミコンダクター株式会社 半導体装置
JP2014165210A (ja) * 2013-02-21 2014-09-08 Fujitsu Component Ltd モジュール基板
JP2020009879A (ja) * 2018-07-06 2020-01-16 太陽誘電株式会社 回路基板および回路モジュール

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910001419B1 (ko) * 1987-03-31 1991-03-05 가부시키가이샤 도시바 수지봉합형 집적회로장치
JPH11233712A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びその製法とそれを使った電気機器
US6833611B2 (en) * 2000-07-12 2004-12-21 Advanced Semiconductor Engineering, Inc. Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009269B (zh) * 2006-01-24 2010-05-12 富士通微电子株式会社 半导体器件及其制造方法
CN101179066B (zh) * 2006-11-10 2010-05-12 全懋精密科技股份有限公司 芯片嵌埋式封装结构
CN106356358A (zh) * 2015-07-13 2017-01-25 艾马克科技公司 半导体封装及其制造方法
CN106356358B (zh) * 2015-07-13 2021-04-09 艾马克科技公司 半导体封装及其制造方法
CN109273504A (zh) * 2018-09-27 2019-01-25 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置

Also Published As

Publication number Publication date
JP2005286057A (ja) 2005-10-13
TW200532750A (en) 2005-10-01
US20050212107A1 (en) 2005-09-29
TWI259507B (en) 2006-08-01
KR20050096851A (ko) 2005-10-06

Similar Documents

Publication Publication Date Title
CN1677665A (zh) 电路装置及其制造方法
CN1674277A (zh) 电路装置
CN1705104A (zh) 电路装置及其制造方法
KR101469770B1 (ko) 전력 소자 패키지 및 그 제조 방법
CN1187806C (zh) 电路装置的制造方法
CN1244258C (zh) 电路装置及其制造方法
CN1264923A (zh) 半导体器件及其制造方法
CN1674278A (zh) 电路装置
US8860196B2 (en) Semiconductor package and method of fabricating the same
CN1753177A (zh) 功率半导体模块及其制造方法
CN1705108A (zh) 电路装置及其制造方法
CN1750737A (zh) 其上安装有芯片封装模块的印刷电路板及其制造方法
CN1497717A (zh) 电路装置及其制造方法
JP2006128455A (ja) 半導体装置およびその製造方法
US20150280093A1 (en) Light emitting device, method for manufacturing same, and body having light emitting device mounted thereon
CN1342037A (zh) 使用金属氧化物半导体场效应晶体管的保护电路装置及其制造方法
CN104584207A (zh) 电子部件封装以及其制造方法
CN1536658A (zh) 半导体器件及其制造方法
US20140299995A1 (en) Wiring device for semiconductor device, composite wiring device for semiconductor device, and resin-sealed semiconductor device
CN1509134A (zh) 电路装置、电路模块及电路装置的制造方法
CN1276090A (zh) 半导体装置及其制造方法
US8471371B2 (en) Semiconductor wiring assembly, semiconductor composite wiring assembly, and resin-sealed semiconductor device
JP4596846B2 (ja) 回路装置の製造方法
KR100923784B1 (ko) 방열 특성이 우수한 금속 회로 기판 및 그 제조 방법
CN1510746A (zh) 电路装置及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication