TWI570822B - 基板結構及其製法 - Google Patents

基板結構及其製法 Download PDF

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TWI570822B
TWI570822B TW103102603A TW103102603A TWI570822B TW I570822 B TWI570822 B TW I570822B TW 103102603 A TW103102603 A TW 103102603A TW 103102603 A TW103102603 A TW 103102603A TW I570822 B TWI570822 B TW I570822B
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substrate
electrical contact
substrate structure
protective layer
insulating protective
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TW103102603A
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TW201530669A (zh
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張辰安
孫崧桓
吳建宏
陳以婕
廖文楷
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矽品精密工業股份有限公司
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Priority to TW103102603A priority Critical patent/TWI570822B/zh
Priority to CN201410046315.XA priority patent/CN104810338A/zh
Priority to US14/463,049 priority patent/US9398689B2/en
Publication of TW201530669A publication Critical patent/TW201530669A/zh
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Description

基板結構及其製法
本發明係有關一種基板結構及其製法，尤指一種具有絕緣保護層之基板結構及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態。其中，球柵陣列式(Ball grid array,BGA)，例如PBGA、EBGA、FCBGA等，為一種先進的半導體封裝技術，其特點在於採用一封裝基板來安置半導體元件，並於該封裝基板背面植置多數個成柵狀陣列排列之錫球(Solder ball)，使相同單位面積之承載件上可容納更多輸入/輸出連接端(I/O connection)以符合高度集積化(Integration)之半導體晶片之需求，並藉該些錫球將整個封裝單元焊結並電性連接至外部電子裝置。
再者，為了符合半導體封裝件輕薄短小、多功能、高速度及高頻化的開發方向，半導體晶片封裝用之電路板(或封裝基板)已朝向細線路及小孔徑發展。
第1圖係為習知封裝基板1之剖視示意圖。如第1圖所示，提供一具有複數電性接觸墊100與線路101之基板 本體10。接著，形成一防銲層11於該基板本體10上，再形成複數開孔110於該防銲層11上，且該開孔110之孔徑R小於該電性接觸墊100之寬度A，使各該電性接觸墊100對應外露於各該開孔110。之後，形成複數如銲球13於各該開孔110中之電性接觸墊100上，使該銲球13電性連接該電性接觸墊100，以完成習知覆晶封裝(Flip Chip Package)用之封裝基板1，令該封裝基板1藉由回銲該些銲球13以結合其他電子元件，例如半導體晶片(圖略)。
習知封裝基板1利用該銲球13作為電性連接元件，具有縮短電性傳導路徑、提升效能及縮小半導體封裝件等優點，因而成為現行之封裝趨勢。
然而，於回銲該銲球13時，該銲球13因加熱而產生熱膨脹現象，且該銲球13之銲料會沿著該線路101的路徑延展與擴散而流入該防銲層11底下，並且由於該防銲層11與該銲球13之材質相異，導致於熱膨脹係數(Coefficient of Thermal Expansion,CTE)差異之情況下，使該防銲層11發生碎裂(Crack)，如圖所示之碎裂處K。
再者，由於該防銲層11容易發生碎裂現象，致使製程中之化學藥劑會經由該碎裂處K接觸該基板本體10，因而污染該基板本體10。或者，水氣會從該碎裂處K進入該基板本體10中，致使該線路101發生氧化或短路等問題。
又，在進行信賴性測試(如高溫儲存、落摔等試驗)時，容易自該防銲層11之碎裂處K產生應力變化，而造成該防銲層11大範圍的龜裂與不良等問題。
另外，雖可利用擴大該開孔110之方式，使該電性接觸墊100完全外露於該開孔110’(即該開孔110’之孔徑R’大於該電性接觸墊100之寬度A，如第1’圖所示)，以避免該銲球13之銲料沿該線路101的路徑流入該防銲層11底下，但若該開孔110’的孔徑R’太小，該銲球13依然會受熱膨脹而擠壓該防銲層11，致使該防銲層11發生碎裂，並於後續製程中衍生出該防銲層11整層發生大範圍龜裂與不良的問題，但若為此將該開孔110’繼續擴大，則會造成該基板本體10之佈線空間縮小而不敷使用，且該電性接觸墊100之固定力不佳而容易脫落。
另一方面，同理地，該銲球13亦會發生相同問題於該半導體晶片上。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的問題。
鑑於上述習知技術之種種缺失，本發明提供一種基板結構，係包括：基板本體，係具有複數電性接觸墊；絕緣保護層，係設於該基板本體上，且該絕緣保護層具有複數開孔，使各該電性接觸墊對應外露於各該開孔；以及複數環體，係設於各該開孔中且對應環繞各該電性接觸墊之邊緣。
本發明復提供一種基板結構之製法，係包括：提供一具有複數電性接觸墊之基板本體；形成絕緣保護層於該基板本體上；以及形成複數開孔於該絕緣保護層上，且形成 至少一環體於各該開孔中，使各該電性接觸墊對應外露於各該開孔，且該環體對應環繞該電性接觸墊之邊緣。
前述之製法中，該環體與該開孔係為同時形成，例如，移除該絕緣保護層之部分材質以形成該開孔，且保留該開孔中之該絕緣保護層之另一部分材質以作為該環體。
前述之基板結構及其製法中，該基板本體上復具有複數電性連接該電性接觸墊之線路，使該環體係經過該線路；或者，該電性接觸墊與該線路間具有交界處，令該環體係經過該交界處。
前述之基板結構及其製法中，該絕緣保護層之材質係為防銲材或介電材。
前述之基板結構及其製法中，該開孔之孔徑大於該電性接觸墊之寬度。
前述之基板結構及其製法中，該環體係對應位於該電性接觸墊之邊緣外。
前述之基板結構及其製法中，該環體與該絕緣保護層係為相同材質，例如，該環體之材質係為聚亞醯胺、苯並環丁烯或聚對二唑苯。
前述之基板結構及其製法中，復包括形成複數導電元件於各該環體中，以令該導電元件電性連接該電性接觸墊。
前述之基板結構及其製法中，該基板本體係為線路板或半導體基材。
前述之基板結構及其製法中，該基板本體為半導體基材時，該基板本體具有線路重佈結構，且該線路重佈結構 係電性連接該電性接觸墊。另外，前述之基板結構及其製法中，復包括設於該基板本體上之金屬線，係連接該電性接觸墊且該絕緣保護層設於部分該金屬線上，使該金屬線外露於該開孔中，且該環體經過該金屬線。
由上可知，本發明之基板結構及其製法，藉由在該絕緣保護層之開孔中形成環體，以形成導電元件於各該環體中，故當回銲該導電元件時，該環體會侷限該導電元件向外擴張，因而該導電元件不會擠壓該絕緣保護層，而能避免該絕緣保護層發生碎裂之問題。
因此，於進行其它製程時，化學藥劑不會接觸該基板本體，因而不會污染該基板本體，且水氣亦不會進入該基板本體中，故能避免該線路發生氧化或短路等問題。
再者，於進行信賴性測試(如高溫儲存、落摔等試驗)時，該絕緣保護層不會產生超出預期的應力變化，因而能避免該絕緣保護層發生大範圍的龜裂與不良等問題。
又，當該開孔的孔徑太小時，該導電元件之向外擴張仍會受該環體限制，而不會擠壓該絕緣保護層，故無需將該開孔的孔徑擴大，因而能增加該基板本體之佈線空間。
另外，藉由形成金屬線，使該絕緣保護層(或該環體)能壓固該金屬線與該線路，以協助固定該電性接觸墊，而避免該電性接觸墊脫落。
1‧‧‧封裝基板
10、20、20’‧‧‧基板本體
100、200‧‧‧電性接觸墊
101、201‧‧‧線路
11‧‧‧防銲層
110、110’、210‧‧‧開孔
13‧‧‧銲球
2‧‧‧基板結構
200a‧‧‧邊緣
202‧‧‧金屬線
21‧‧‧絕緣保護層
210a‧‧‧環內區
210b‧‧‧環外區
22、22’、32‧‧‧環體
23‧‧‧導電元件
24‧‧‧線路重佈結構
240‧‧‧鈍化層
241‧‧‧線路重佈層
25‧‧‧半導體基底
250‧‧‧接點
D、R、R’‧‧‧孔徑
A、W‧‧‧寬度
S‧‧‧交界處
K‧‧‧碎裂處
第1圖係為習知封裝基板的剖視示意圖；第1’圖係為第1圖之另一態樣； 第2A至2D圖係為本發明之基板結構之製法之剖視示意圖；其中，第2D’圖係為第2D圖之另一態樣；以及第3A至3C係為第2C圖之不同態樣之上視圖；其中，第3A’圖係為第3A圖之另一態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之基板結構2之製法之剖視示意圖。
如第2A圖所示，提供表面上具有複數電性接觸墊200與複數線路201之一基板本體20。
於本實施例中，該基板本體20係為線路板，其具有複 數介電層(圖略)及複數內部線路層(圖略)，且該些電性接觸墊200與該些線路201係設於最外層之介電層上並電性連接該內部線路層。
於其它實施例中，該基板本體20亦可為半導體基材，例如半導體晶圓、晶片、具有矽穿孔(Through-Silicon Via,TSV)之中介板等，其具有複數鈍化層240(如第2D’圖所示)及複數內部積體線路(圖略)或線路重佈層241(如第2D’圖所示)(redistribution layer,RDL)，且該些電性接觸墊200與該些線路201係設於最外層之鈍化層240上並電性連接該內部積體線路、或者該些電性接觸墊200與該些線路201係作為線路重佈層。
再者，該些線路201係電性連接該些電性接觸墊200。
另外，由於各該電性接觸墊200周圍及其上之製程相同，故於圖式中僅圖示單一電性接觸墊200以作說明，特此述明。
如第2B圖所示，形成一絕緣保護層21於該基板本體20上。
於本實施例中，該絕緣保護層21之材質係為防銲材或介電材，例如聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚對二唑苯(Polybenzoxazole,PBO)。
如第2C圖所示，形成複數開孔210於該絕緣保護層21上，且形成複數環體22於各該開孔210中，使各該電性接觸墊200對應外露於各該開孔210，且各該環體22對 應環繞各該電性接觸墊200之邊緣200a以外露該電性接觸墊200。
於本實施例中，該開孔210之孔徑D大於該電性接觸墊200之寬度W，使該電性接觸墊200完全外露於該開孔210，以避免後續製程之銲料沿該線路201的路徑流入該絕緣保護層21底下。
再者，該環體22係為幾何形狀，如圓形(如第3A圖所示之環體22)、八邊形(如第3B圖所示之環體22’)等，且該環體22與該開孔210係為同時形成，即當移除該絕緣保護層21之部分材質以形成該開孔210時，保留該開孔210中之該絕緣保護層21之另一部分材質以作為該環體22。具體地，該絕緣保護層21係可定義有環內區210a與環外區210b，如第2B圖所示，即當移除該環內區210a與環外區210b之絕緣保護層21材質後，即形成該環體22。
又，該環體22與該絕緣保護層21係為相同材質，故該環體22之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚對二唑苯(Polybenzoxazole,PBO)。
另外，該環體22係對應位於該電性接觸墊200之邊緣200a外，且該環體22經過該線路201。
如第2D圖所示，形成複數如銲球、金屬塊等之導電元件23於各該環體22中之電性接觸墊200上，使該導電元件23電性連接該電性接觸墊200，以令該基板結構2藉由該些導電元件23結合其它電子元件(圖略)，例如，半 導體晶圓、晶片、具有矽穿孔(Through-Silicon Via,TSV)之中介板、或線路板。
於其它製法實施例中，如第2D’圖所示，當該基板本體20’係為半導體基材時，該基板本體20’包含一如晶圓或晶片之半導體基底25、設於該半導體基底25上之至少一接點250與設於該半導體基底25上之線路重佈結構24，該線路重佈結構24係具有複數鈍化層240與設於該鈍化層240上之線路重佈層(RDL)241，且該線路重佈層241電性連接該接點250、該電性接觸墊200與該線路201。
本發明之製法，藉由在該絕緣保護層21之開孔210中形成環體22,22’，以限制該導電元件23之範圍，故當回銲該導電元件23而使該導電元件23受熱膨脹時，該環體22,22’會侷限該導電元件23向外擴張，且即使該導電元件23之體積膨脹過大而擠壓該環體22,22’，也僅會造成該環體22,22’碎裂，而不會造成該絕緣保護層21碎裂。
進一步說明，當該基板本體20’係為半導體基材時，藉由形成該環體22,22’以限制該導電元件23之範圍，故當回銲該導電元件23時，能避免該絕緣保護層21與該線路重佈結構24(或線路重佈層241)碎裂。例如，若無該環體22,22’之設計，該導電元件23之銲料會沿著該線路201的路徑延展與擴散而流入該絕緣保護層21底下，使該絕緣保護層21或該線路重佈層241發生碎裂。
因此，該絕緣保護層21能保持良好之保護功能，故於進行其它製程時，由於該絕緣保護層21或該線路重佈結構 24不會發生碎裂現象，致使製程中之化學藥劑不會接觸該基板本體20,20’，因而不會污染該基板本體20,20’。或者，水氣亦不會進入該基板本體20,20’中，故能避免該線路201或該線路重佈層241發生氧化或短路等問題。
再者，於進行信賴性測試(如高溫儲存、落摔等試驗)時，該絕緣保護層21保持良好之結構完整性，故該絕緣保護層21不會產生超出預期的應力變化，因而能避免該絕緣保護層21發生大範圍的龜裂與不良等問題。
又，藉由該環體22,22’之設計，當該開孔210的孔徑D太小，該導電元件23之向外擴張仍會受該環體22,22’限制，而不會擠壓該絕緣保護層21，因而能避免該絕緣保護層21發生碎裂。故而，無需將該開孔210的孔徑D擴大，因而能增加該基板本體20,20’之佈線空間，以避免該基板本體20,20’之佈線空間縮小而不敷使用的問題。
如第3A’圖所示，該電性接觸墊200與該線路201間具有交界處S，藉由該環體32經過該交界處S，使該導電元件23於植設時即能直接抵靠在該環體32上，以避免該導電元件23因潤濕作用而往該線路201的方向移動。
如第3C圖所示，該基板本體20上可選擇性地形成一金屬線202(例如，於第2C圖之製程中，當該開孔210的孔徑D較大時)，其連接該電性接觸墊200之邊緣200a，且該絕緣保護層21設於部分該金屬線202上，使該金屬線202外露於該開孔210中，而該環體22經過該金屬線202。藉由該絕緣保護層21(或該環體22)壓住固定該金屬線 202與該線路201，以協助固定該電性接觸墊200之邊緣200a之兩側，而避免當該開孔210的孔徑D過大時而造成該電性接觸墊200脫落。
另外，本發明之製法中，於其它實施例中，該環體22,22’,32可與該開孔210分別形成，且該環體22,22’,32之材質不同於該絕緣保護層21之材質。例如，先形成該開孔210，再將該環體22,22’,32放置於該開孔210中。
本發明復提供一種基板結構2，係包括：一基板本體20,20’、設於該基板本體20,20’上之一絕緣保護層21、複數環體22,22’,32以及複數電性接觸墊200。
所述之基板本體20,20’係為線路板或半導體基材，其復具有複數電性連接該電性接觸墊200之線路201，使該電性接觸墊200與該線路201間具有交界處S。當該基板本體20’為半導體基材時，該基板本體20’具有線路重佈結構24，且該線路重佈結構24係電性連接該些電性接觸墊200。
所述之絕緣保護層21係具有複數開孔210，使各該電性接觸墊200對應外露於各該開孔210，且該開孔210之孔徑D大於該電性接觸墊200之寬度W，又該絕緣保護層21之材質係為苯並環丁烯、聚醯亞胺或聚苯並噁唑。
所述之環體22,22’,32係設於各該開孔210中且對應環繞各該電性接觸墊200之邊緣200a，例如，該環體22,22’係對應位於該電性接觸墊200之邊緣200a外且該環體22經過該線路201、或者該環體32係經過該交界處S。再者， 該環體22,22’,32係為幾何形狀，且該環體22,22’,32與該絕緣保護層21係為相同材質，例如該環體22,22’,32之材質係為苯並環丁烯、聚醯亞胺或聚苯並噁唑。
所述之基板結構2復包括設於各該環體22,22’,32中之複數導電元件23，其電性連接該電性接觸墊200。
綜上所述，本發明之基板結構及其製法，主要藉由在該絕緣保護層之開孔中形成環體，以將該導電元件形成於該環體中，故當回銲該導電元件時，該環體會侷限該導電元件向外擴張，以避免該絕緣保護層發生碎裂。因此，該絕緣保護層能保持良好之保護功能與結構完整性，故能避免化學藥劑、水氣等侵入該基板本體中，且能避免該絕緣保護層發生大範圍的龜裂與不良等問題。
再者，藉由該環體之設計，不論該開孔的孔徑尺寸大小，該導電元件均會受該環體限制而不會擠壓該絕緣保護層，故能依需求縮小該開孔的孔徑，以增加該基板本體之佈線空間。
又，當該開孔太大時，可於該電性接觸墊之周圍連接該金屬線與線路，以藉由該絕緣保護層(或該環體)壓固該金屬線與該線路，而提升該電性接觸墊之固定能力，故能避免該電性接觸墊脫落。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。
2‧‧‧基板結構
20‧‧‧基板本體
200‧‧‧電性接觸墊
200a‧‧‧邊緣
201‧‧‧線路
21‧‧‧絕緣保護層
210‧‧‧開孔
22‧‧‧環體
23‧‧‧導電元件

Claims (24)

  1. 一種基板結構，係包括：基板本體，係具有複數電性接觸墊；絕緣保護層，係設於該基板本體上，且該絕緣保護層具有複數開孔，使各該電性接觸墊對應外露於各該開孔；以及複數環體，係設於各該開孔中且對應各該電性接觸墊之邊緣。
  2. 如申請專利範圍第1項所述之基板結構，其中，該基板本體上復具有複數電性連接該電性接觸墊之線路。
  3. 如申請專利範圍第2項所述之基板結構，其中，該環體係經過該線路。
  4. 如申請專利範圍第2項所述之基板結構，其中，該電性接觸墊與該線路間具有交界處，且該環體係經過該交界處。
  5. 如申請專利範圍第1項所述之基板結構，其中，該絕緣保護層之材質係為防銲材或介電材。
  6. 如申請專利範圍第1項所述之基板結構，其中，該環體係對應位於該電性接觸墊之邊緣外。
  7. 如申請專利範圍第1項所述之基板結構，其中，該環體與該絕緣保護層係為相同材質。
  8. 如申請專利範圍第1項所述之基板結構，其中，該環體之材質係為聚亞醯胺、苯並環丁烯或聚對二唑苯。
  9. 如申請專利範圍第1項所述之基板結構，復包括設於 各該環體中之複數導電元件，其電性連接該電性接觸墊。
  10. 如申請專利範圍第1項所述之基板結構，其中，該基板本體係為線路板或半導體基材。
  11. 如申請專利範圍第10項所述之基板結構，其中，該基板本體為半導體基材時，該基板本體具有線路重佈結構，且該線路重佈結構係電性連接該電性接觸墊。
  12. 一種基板結構之製法，係包括：提供一具有複數電性接觸墊之基板本體；形成絕緣保護層於該基板本體上；以及形成複數開孔於該絕緣保護層上，且形成複數環體於各該開孔中，使各該電性接觸墊對應外露於各該開孔，且該環體對應該電性接觸墊之邊緣。
  13. 如申請專利範圍第12項所述之基板結構之製法，其中，該基板本體上復具有複數電性連接該電性接觸墊之線路。
  14. 如申請專利範圍第13項所述之基板結構之製法，其中，該環體係經過該線路。
  15. 如申請專利範圍第13項所述之基板結構之製法，其中，該電性接觸墊與該線路間具有交界處，且該環體係經過該交界處。
  16. 如申請專利範圍第12項所述之基板結構之製法，其中，該絕緣保護層之材質係為防銲材或介電材。
  17. 如申請專利範圍第12項所述之基板結構之製法，其 中，該環體係對應位於該電性接觸墊之邊緣外。
  18. 如申請專利範圍第12項所述之基板結構之製法，其中，該環體與該絕緣保護層係為相同材質。
  19. 如申請專利範圍第12項所述之基板結構之製法，其中，該環體之材質係為聚亞醯胺、苯並環丁烯或聚對二唑苯。
  20. 如申請專利範圍第12項所述之基板結構之製法，復包括形成複數導電元件於各該環體中，以令該導電元件電性連接該電性接觸墊。
  21. 如申請專利範圍第12項所述之基板結構之製法，其中，該基板本體係為線路板或半導體基材。
  22. 如申請專利範圍第21項所述之基板結構之製法，其中，該基板本體為半導體基材時，該基板本體具有線路重佈結構，且該線路重佈結構係電性連接該電性接觸墊。
  23. 如申請專利範圍第12項所述之基板結構之製法，其中，該環體與該開孔係為同時形成。
  24. 如申請專利範圍第23項所述之基板結構之製法，其中，移除該絕緣保護層之部分材質以形成該開孔，且保留該開孔中之該絕緣保護層之另一部分材質以作為該環體。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562256B (en) * 2015-09-07 2016-12-11 Siliconware Precision Industries Co Ltd Substrate structure
US20170186701A1 (en) * 2015-12-26 2017-06-29 Intel Corporation Crack resistant electronic device package substrates
TWI582928B (zh) * 2016-01-19 2017-05-11 矽品精密工業股份有限公司 基板結構及其製法
US11322465B2 (en) * 2019-08-26 2022-05-03 Cirrus Logic, Inc. Metal layer patterning for minimizing mechanical stress in integrated circuit packages
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CN114388373A (zh) * 2020-10-22 2022-04-22 长鑫存储技术有限公司 半导体封装方法及半导体结构
CN117178637A (zh) * 2021-07-28 2023-12-05 华为技术有限公司 电路基板、相关的电路组件和电子设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201322399A (zh) * 2011-11-29 2013-06-01 Powertech Technology Inc 可光學檢測銲罩開口偏移在容許範圍內之封裝基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4528035B2 (ja) * 2004-06-18 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置
US7749885B2 (en) * 2006-12-15 2010-07-06 Micron Technology, Inc. Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers
JP4980709B2 (ja) * 2006-12-25 2012-07-18 ローム株式会社 半導体装置
CN102088012B (zh) * 2009-12-07 2013-04-17 精材科技股份有限公司 电子元件封装体及其制造方法
US8283781B2 (en) * 2010-09-10 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US9252094B2 (en) * 2011-04-30 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar
CN103107154B (zh) * 2013-01-23 2015-07-08 上海交通大学 用于tsv铜互连的应力隔离焊垫结构及其制备方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201322399A (zh) * 2011-11-29 2013-06-01 Powertech Technology Inc 可光學檢測銲罩開口偏移在容許範圍內之封裝基板

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