CN103151333A - 后钝化互连结构 - Google Patents

后钝化互连结构 Download PDF

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Publication number
CN103151333A
CN103151333A CN2012101327098A CN201210132709A CN103151333A CN 103151333 A CN103151333 A CN 103151333A CN 2012101327098 A CN2012101327098 A CN 2012101327098A CN 201210132709 A CN201210132709 A CN 201210132709A CN 103151333 A CN103151333 A CN 103151333A
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layer
pseudo
opening
semiconductor device
area
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CN103151333B (zh
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陈宪伟
蔡豪益
李明机
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种半导体器件，该半导体器件包括设置半导体衬底上的钝化层以及设置钝化层上的互连结构。该互连结构包括相互电分离的接合焊盘区域和伪区域。保护层设置在该互连结构的上面并且包括暴露接合焊盘区域的一部分的第一开口以及暴露伪区域的一部分的第二开口。金属层形成在接合焊盘区域的所暴露部分和伪区域的所暴露部分上。凸块形成在位于接合焊盘区域上面的金属层上。本发明还公开了后钝化互连结构。

Description

后钝化互连结构
本发明涉及2011年10月13日提交的、申请号为13/272,540的美国共同未决申请，其全文通过引用明确并入本文中。
技术领域
本发明涉及半导体技术领域，更具体地，涉及后钝化互连结构。
背景技术
现代集成电路差不多是由成千上万的诸如晶体管和电容器的有源器件构成的。这些器件最初是相互分离的，但是后续互连在一起从而形成功能电路。典型的互连结构包括横向互连件例如金属线(线路)以及纵向互连件诸如通路孔和接触点。互连件越来越多地决定了性能限制以及现代集成电路的密度。在互连结构的顶部，形成焊盘并且焊盘暴露在各自芯片的表面上。通过焊盘形成电连接以将芯片连接到封装衬底或其它管芯。焊盘可用于布线接合和倒装芯片结合。倒装芯片封装利用凸块来建立芯片的I/O焊盘与封装件的衬底或引线框之间的电连接。在结构上，凸块实际上包括凸块本身以及设置在凸块与I/O焊盘之间的“凸块下金属层”(UBM)。
现今，晶圆级芯片规模封装(WLCSP)由于其低成本以及相对简单的工艺而被广泛应用。在典型的WLCSP中，诸如再分配线(RDL)的后钝化互连(PPI)线形成在钝化层上，随后形成聚合物薄膜以及凸块。然而，已知的PPI形成工艺具有聚合物薄膜剥落的问题，这可能导致PPI结构的接口性能差以及造成器件故障。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：
半导体衬底；
钝化层，设置在所述半导体衬底上面；
互连结构，设置在所述钝化层上面，所述互连结构包括相互电分离的接合焊盘区域和伪区域；
保护层，设置在所述互连结构上面，所述保护层包括暴露所述接合焊盘区域的一部分的第一开口以及暴露所述伪区域的一部分的第二开口；
金属层，形成在所述接合焊盘区域的所暴露部分上以及所述伪区域的所暴露部分上；以及
凸块，形成在位于所述接合焊盘区域上面的所述金属层上。
在可选实施方式中，形成在所述保护层的第二开口中的所述金属层是与所述凸块电分离的伪支柱。
在可选实施方式中，所述金属层包括钛层、铜层以及镍层中的至少一个。
在可选实施方式中，所述互连结构包括铜层。
在可选实施方式中，所述互连结构包括与所述接合焊盘区域相邻的多个伪区域。
在可选实施方式中，所述保护层包括与所述第一开口相邻的多个所述第二开口，所述金属层填充多个所述第二开口以形成多个伪支柱。
在可选实施方式中，所述第一保护层包括聚合物。
在可选实施方式中，所述半导体器件进一步包括形成在所述钝化层与所述互连结构之间的聚合物层。
在可选实施方式中，所述半导体器件进一步包括形成在所述半导体衬底上的导电焊盘，其中所述导电焊盘被所述钝化层部分覆盖，并且所述导电焊盘电连接至所述互连结构的所述接合焊盘区域。
在可选实施方式中，所述半导体器件进一步包括：伪焊盘，形成在所述半导体衬底上并与所述导电焊盘电分离，其中所述伪焊盘被所述钝化层部分覆盖，并且所述伪焊盘电连接至所述互连结构的所述伪区域。
在可选实施方式中，所述导电焊盘和所述伪焊盘是由相同的材料形成的。
根据本发明的另一方面，还提供了一种半导体器件，包括：
包括导电焊盘的半导体衬底；
钝化层，形成在所述半导体衬底上并暴露所述导电焊盘的一部分；
后钝化互连(PPI)结构，设置在所述钝化层上面，所述后钝化互连结构包括电连接至所述导电焊盘的所暴露部分的第一区域以及与所述第一区域电分离的第二区域；
聚合物层，设置在所述PPI结构上面，所述聚合物层包括第一开口和第二开口，所述第一开口暴露所述PPI结构的第一区域的一部分以及所述第二开口暴露所述PPI结构的第二区域的一部分；
凸块下金属(UBM)层，形成在所述聚合物层的所述第一开口中；以及
金属层，形成在所述聚合物层的所述第二开口中。
在可选实施方式中，所述半导体衬底包括与所述导电焊盘电分离的伪焊盘，所述钝化层暴露所述伪焊盘的一部分，所述PPI结构的所述第二区域形成在所述伪焊盘的所暴露部分的上方。
在可选实施方式中，所述PPI结构包括与所述第一区域相邻的多个所述第二区域。
在可选实施方式中，所述聚合物层包括多个所述第二开口，分别暴露所述PPI结构的多个所述第二区域。
在可选实施方式中，所述金属层填充所述聚合物层中的多个所述第二开口。
在可选实施方式中，所述金属层包括钛层、铜层以及镍层中的至少一个。
在可选实施方式中，所述半导体器件还包括位于所述钝化层和所述PPI结构之间的另一聚合物层。
在可选实施方式中，所述UBM层和所述金属层是由相同材料层形成的。
附图说明
图1-4示出了根据示例性实施例的形成具有PPI结构的半导体器件的方法的各个中间阶段的截面图。
图5是根据示例性实施例的具有一种可选PPI结构的半导体器件的截面图。
图6是根据示例性实施例的具有另一种可选PPI结构的半导体器件的截面图。
图7是根据示例性实施例的具有另一种可选PPI结构的半导体器件的截面图。
具体实施方式
下面详细讨论本发明实施例的制造和使用。然而，应该理解，本发明实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。在本文的各附图以及说明的实施例中，相同的参考标号用于标示相同的元件。参考标号通过在附图中示出的示例性实施例来详细说明。在可能的情况下，附图以及说明书中使用相同的参考标号以用于指相同或相似的部分。为了清楚和方便说明，附图中可能放大了形状以及厚度。具体地，下面将对形成为根据本发明的装置的一部分的元件或者更直接地对与根据本发明的装置合作的元件进行描述。本领域技术人员可以理解，没有具体示出或者描述的元件可以具有多种不同的形式。在整个说明书中关于“在一个实施例中”或者“在实施例中”的参考意味着：结合实施例描述的具体特征、结构或特性包括在至少一个实施例中。因此，在整个说明书中不同位置出现的“在一个实施例中”或者“在实施例中”并非必然都指同一个实施例。此外，具体特征、结构或特性可以以任何适合的方式结合在一个或更多实施例中。应该认识到，下面的附图并非按照比例来绘制，这些附图仅仅是为了说明。
图1-4示出了根据实施例的形成在半导体器件中的PPI结构的方法的各个中间阶段。
首先参考图1，其示出了根据实施例的具有电路形成在其上的衬底10的一部分。衬底10可包括：例如掺杂或未掺杂的体硅晶圆，或绝缘体上半导体(SOI)衬底的有源层。通常来讲，SOI衬底包括形成在绝缘体层上的诸如硅的半导体材料层。介电层可以是例如BOX(buried oxide埋氧)层或者氧化硅层。介电层设置在衬底上，典型地设置在硅衬底或玻璃衬底上。其它衬底，诸如多层或者梯度衬底也可以被使用。
形成于衬底10上的电路可以是适合具体应用的任何类型的电路。在实施例中，电路包括形成在衬底10上的电子器件并且一层或多层介电层覆盖在电子器件上。金属层可形成在介电层之间以为在电子器件之间的电信号提供路径。电子器件还可形成在一层或多层介电层中。例如，电路可以包括多种互连以实现一种或者多种功能部件的N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二级管、熔丝等。功能部件可以包括存储结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。本领域普通技术人员能够认识到上面提供的用于示例目的的例子仅仅是进一步阐明一些示例性实施例的应用，并非意图以任何方式限制本发明的范围。对于给定应用可使用其它合适的电路。
一个或者多个金属间介电(IMD)层以及关联的金属化层形成在电路上方并与电路互连。IMD层可由低K介电材料形成，例如通过等离子体增强化学气相沉积(PECVD)技术或者高密度等离子体化学气相沉积(HDPCVD)或类似工艺形成的掺氟的硅酸盐玻璃(FSG)；IMD层还可包括中间蚀刻停止层。需要注意的是，一个或者多个蚀刻停止层(未示出)可被设置在相邻的介电层之间。通常来讲，当形成通路孔和/或接触点时，蚀刻停止层提供了停止蚀刻工艺的机制。蚀刻停止层是由在相邻层之间具有不同蚀刻选择度的介电材料形成的。在实施例中，蚀刻停止层可以由SiN、SiCN、SiCO、CN或者它们的组合或者类似物使用化学气相沉积(CVD)或PECVD技术进行沉积而形成的。
金属化层可由铜或铜合金形成，然而它们也可由其它金属形成。此外，金属化层包括形成并图案化在最上面的IMD层之中或之上的顶部金属层，以提供外部电连接并保护在下面的层免受各种环境污染。最上面的IMD层可以由诸如氮化硅、氧化硅以及未掺杂的硅酸盐玻璃等的介电材料形成。
参考图1A，导电焊盘12形成在衬底10上以电连接下面的金属层。导电焊盘12可由铝、铝铜、铝合金、铜、铜合金等形成。诸如钝化层14的一个或更多钝化层形成于导电焊盘12以及暴露的衬底10上。钝化层14可由诸如未掺杂的硅酸盐玻璃、氮化硅、氧化硅、氮氧化硅或者非多孔材料的介电材料通过任何适合的方法诸如CVD，物理气相沉积(PVD)等形成。钝化层14可以是单层也可以是层叠的层。需要注意的是，示出的单层导电焊盘和钝化层仅仅只是为了举例说明的目的。因此，其它实施例可以包括任何数量的导电层和/或钝化层。
然后，钝化层14通过使用光掩模方法、光刻技术、蚀刻工艺或者它们的组合来图案化，使得形成暴露部分导电焊盘12的开口。在一个实施例中，对钝化层14进行图案化使得覆盖导电焊盘12的外围部分并暴露导电焊盘12的中心部分。
接下来，第一保护层16形成在钝化层14上，然后对其图案化以形成另一开口，通过该开口再次暴露导电焊盘12的至少一部分。第一保护层16可以是例如聚合物层。聚合物层可由诸如环氧树脂，聚酰亚胺，苯并环丁烯(BCB)以及聚苯并恶唑(PBO)等的聚合材料形成，然而也可以使用其它相对柔软、通常为有机的介电材料。形成方法包括旋涂法或者其它方法。
之后，PPI结构20形成并图案化在第一保护层16上，并通过第一保护层16的开口电连接至导电焊盘12。PPI结构20是导电层18，导电层18包括互连线区域18L、接合焊盘(landing pad)区域18P以及伪区域18D。互连线区域18L、接合焊盘区域18P以及伪区域18D可同时形成，并且可以由相同的介电材料形成。在随后的工艺中，凸块部件将会形成在接合焊盘区域18P上，并与该接合焊盘区域18P电连接。互连线区域18L电连接至接合焊盘区域18P并通过第一保护层16的开口延伸为电连接至导电焊盘12。伪区域18D与互连线区域18L和接合焊盘区域18P电分离。导电层18包括但不限于例如铜、铝、铜合金或者其它使用电镀、无电镀、溅镀、化学气相沉积方法等的移动导电材料。在一些实施例中，导电层可进一步包括在含铜层的顶部上的含镍层或者氮化硅层(未示出)。在一些实施例中，PPI结构20可用作为电源线、再分配线(RDL)、电感器、电容器或任何无源元件。通过PPI结构20提供的电信号路径，接合焊盘区域18P可以直接在导电焊盘12上或者可以不直接在导电焊盘12上。
图1B是根据示例性实施例的PPI结构20的俯视图。PPI结构20包括与接合焊盘区域18P相邻的至少一个伪区域18D。在一些实施例中，多个伪区域18D形成于第一保护层16上并与接合焊盘区域18P相邻。应该注意的是，伪区域18D的位置仅仅是为了示意目的而提供的，伪区域18D的具体位置以及图案可以不同并且包括例如方形区域、圆形区域、矩形区域以及狭槽形等。例如，伪区域18D可以是具有边长L1大于5μm的方形区域。在实施例中，两个相邻伪区域18D之间的间隔S1大于5μm。示例尺寸仅是为了参考而提供，并不意图是实际尺寸或者实际相对尺寸。
参考图2，然后第二保护层22形成在衬底10上以覆盖PPI结构20和第一保护层16的暴露部分。使用光刻法和/或蚀刻工艺进一步图案化第二保护层22以形成暴露接合焊盘区域18P的一部分的第一开口23a以及暴露至少一个伪区域18D的一部分的第二开口23b。在实施例中，多个第二开口23b形成在第二保护层22中以分别暴露多个伪区域18D。开口23a和23b的形成方法包括光刻、湿法蚀刻或干法蚀刻、激光钻孔等。在一些实施例中，第二保护层22可由诸如环氧树脂，聚酰亚胺，苯并环丁烯(BCB)以及聚苯并恶唑(PBO)等的聚合材料形成，然而也可以使用其它相对柔软、通常为有机的介电材料。在一些实施例中，第二保护层22由选自下述的非有机材料形成：未掺杂的硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅及它们的组合。
接下来，如图3A所示，金属层24沉积并图案化在接合焊盘区域18P和伪区域18D的暴露部分上。在接合焊盘区域18P上，形成在第一开口23a中的图案化金属层24覆盖接合焊盘区域18P的暴露部分以用作凸块将形成在其上的凸块下金属(UBM)层24B。在伪区域18D上，金属层24填充第二开口23b并物理连接伪区域18D以用作为与UBM层24B电分离的伪支柱24D。在一些实施例中，金属层24包括扩散势垒层或粘着剂层，上述层可以包括钛(Ti)、钽(Ta)、氮化钛(TIN)、氮化钽(TAN)等并通过PVD或溅射工艺形成。金属层24还可包括通过PVD或溅射工艺形成于扩散势垒层上的晶种层。晶种层可由铜(Cu)、包括铝的铜合金、铬(Cr)、镍(Ni)、锡(Sn)、金(Au)或其化合物形成。在至少一个实施例中，金属层24包括钛层和铜层。在另一实施例中，金属层24包括钛层、铜层以及镍层。
图3B是根据示例性实施例的图案化金属层24的俯视图。图案化金属层24包括与UBM层24B相邻的至少一个伪支柱24D。在一些实施例中，多个伪支柱24D形成在与UBM层24B相邻的第二保护层22中。应该注意的是，提供的伪支柱24D的位置仅仅是为了示意目的，伪支柱24D的具体位置以及图案可以不同并且包括例如方形柱、圆形柱以及矩形柱等。例如，伪支柱24D可以是具有边长L2大于5μm的方形形状。在实施例中，两个相邻伪支柱24D之间的间隔S2大于5μm。伪支柱24D与UBM层24B之间的距离d1大于10μm或者大于20μm。提供的示例支柱尺寸仅是为了参考，并不意图是实际尺寸或者实际相对尺寸。
如图4A所示，焊料凸块26形成在UBM层24B上。在一个实施例中，焊料凸块26通过将焊球附着在UBM层24B上然后对焊料进行回焊而形成。在可选实施例中，焊料凸块26通过电镀焊料然后对焊料回焊而形成。焊料凸块26可包括无铅预焊料层、SnAg或者包含锡、铅、银、铜、镍以及铋或其组合的合金的焊料。图4B是根据示例性实施例的焊料凸块26的俯视图。焊料凸块26分别形成在接合焊盘区域18P内的UBM层24B上。由PPI结构20的导电层18形成的导引区(trace)18”设置在两个相邻的互连线区域18L之间。在实施例中，导引区18”具有大于5μm或者大于10μm的宽度W1。在另一实施例中，导引区18”与相邻的互联线区域18L之间的间隔S3大于5μm或者大于10μm。在其它实施例中，两个相邻的焊料凸块26之间的间隔S4大于100μm，例如大于120μm或者150μm。因此，至少一个伪支柱24D布置成与至少一个焊料凸块26相邻。在一些实施例中，形成多个伪支柱24D并且它们与每个焊料凸块26相邻有。提供的示例焊料凸块尺寸仅是为了参考，并不意图是实际尺寸或者实际相对尺寸。
然后在半导体器件上完成凸块结构。本实施例提供包括伪支柱24D的凸块结构以及邻近凸块结构的伪区域18D以增强第二保护层22和第一保护层16之间的粘附力。这可以提高PPI结构20的强度，并且可以减少和/或消除聚合物层的剥落和破裂。因此，在封装工艺中，可以增强连接可靠性以及减少凸块的疲劳。
在凸块形成之后，例如，可以形成密封层，可执行切割工艺以切割单个的管芯，并且可进行晶圆级或者管芯级的堆叠。然而，也应意识到，这些实施例可以使用在不同的情况下。例如，实施例可以使用在管芯对管芯的接合结构、管芯对晶圆的接合结构、晶圆对晶圆的接合结构，管芯级封装、晶圆级封装等中。
图5示出了根据可选实施例的半导体器件中的示例性PPI结构。除非具体说明，否则在本实施例中的参考标号表示与在图1-4所示实施例中的元件相同的元件。
与图4A中示出的结构相比，图5中示出的可选结构不具有第一保护层16。PPI结构20形成在钝化层14上，因此互连线区域18L通过钝化层14的开口电连接至导电焊盘12。
图6示出了根据另一可选实施例的在半导体器件中的示例性PPI结构。除非具体说明，否则在本实施例中的参考标号表示与在图1-4所示实施例中的元件相同的元件。
与图4A中示出的结构相比，图6中示出的可选结构还包括形成在伪区域18D下面的伪焊盘12D。伪焊盘12D与形成在衬底10上的导电焊盘12以及电路电分离。伪焊盘12D和导电焊盘12可同时形成，并可由同一种导电材料形成。形成并图案化钝化层14和第一保护层16以暴露伪焊盘12D的一部分，因此伪区域18D电连接至伪焊盘12D。在实施例中，至少一个伪焊盘12D形成在与接合焊盘区域18P相邻的伪区域18D的下面。在一些实施例中，形成多个与接合焊盘区域18P相邻的伪焊盘12D。
图7示出了根据另一可选实施例的在半导体器件中的示例性PPI结构。除非具体说明，否则在本实施例中的参考标号表示与图5所示实施例中的元件相同的元件。
与图6中示出的结构相比，图7中示出的可选结构不具有第一保护层16。PPI结构20形成在钝化层14上，因此互连线区域18L通过钝化层14中的开口电连接至导电焊盘12。
根据示例性实施例的一个方面，半导体器件包括半导体衬底、设置在半导体衬底上面的钝化层以及设置在钝化层上面的互连结构。互连结构包括相互电分离的接合焊盘区域和伪区域。保护层形成在互连结构上并具有暴露接合焊盘区域的一部分的第一开口以及暴露伪区域的一部分的第二开口。金属层形成在接合焊盘区域的暴露区域和伪区域的暴露区域上。凸块形成在位于接合焊盘区域上的金属层上。
根据示例性实施例的另一个方面，半导体器件包括具有导电焊盘的半导体衬底、形成在半导体上并暴露导电焊盘一部分的钝化层以及设置在钝化层上面的后钝化互连(PPI)结构。PPI结构包括电连接至导电焊盘的所暴露部分的第一区域以及与第一区域电分离的第二区域。聚合物层形成在PPI结构上并具有第一开口和第二开口，其中第一开口暴露PPI结构的第一区域的一部分以及第二开口暴露PPI结构的第二区域的一部分。凸块下金属(UBM)层形成在聚合物层的第一开口中。金属层形成在聚合物层的第二开口中。
在前面详细说明中，通过参考具体示例性实施例描述了本发明。然而，很明显的是，在不背离本发明的精神和范围的情况下可以具有各种变化、结构、工艺以及改变。因此，说明书和附图是用于说明而不是限制。应当理解，在本申请描述的本发明主旨的范围内，本发明能够使用各种其它组合和环境并且可以改变以及调整。

Claims (10)

1.一种半导体器件，包括：
半导体衬底；
钝化层，设置在所述半导体衬底上面；
互连结构，设置在所述钝化层上面，所述互连结构包括相互电分离的接合焊盘区域和伪区域；
保护层，设置在所述互连结构上面，所述保护层包括暴露所述接合焊盘区域的一部分的第一开口以及暴露所述伪区域的一部分的第二开口；
金属层，形成在所述接合焊盘区域的所暴露部分上以及所述伪区域的所暴露部分上；以及
凸块，形成在位于所述接合焊盘区域上面的所述金属层上。
2.根据权利要求1所述的半导体器件，其中形成在所述保护层的第二开口中的所述金属层是与所述凸块电分离的伪支柱。
3.根据权利要求1所述的半导体器件，其中所述金属层包括钛层、铜层以及镍层中的至少一个。
4.根据权利要求1所述的半导体器件，其中所述互连结构包括铜层。
5.根据权利要求1所述的半导体器件，其中所述互连结构包括与所述接合焊盘区域相邻的多个伪区域。
6.一种半导体器件，包括：
包括导电焊盘的半导体衬底；
钝化层，形成在所述半导体衬底上并暴露所述导电焊盘的一部分；
后钝化互连(PPI)结构，设置在所述钝化层上面，所述后钝化互连结构包括电连接至所述导电焊盘的所暴露部分的第一区域以及与所述第一区域电分离的第二区域；
聚合物层，设置在所述PPI结构上面，所述聚合物层包括第一开口和第二开口，所述第一开口暴露所述PPI结构的第一区域的一部分以及所述第二开口暴露所述PPI结构的第二区域的一部分；
凸块下金属(UBM)层，形成在所述聚合物层的所述第一开口中；以及
金属层，形成在所述聚合物层的所述第二开口中。
7.根据权利要求6所述的半导体器件，其中所述半导体衬底包括与所述导电焊盘电分离的伪焊盘，所述钝化层暴露所述伪焊盘的一部分，所述PPI结构的所述第二区域形成在所述伪焊盘的所暴露部分的上方。
8.根据权利要求6所述的半导体器件，其中所述PPI结构包括与所述第一区域相邻的多个所述第二区域。
9.根据权利要求8所述的半导体器件，其中所述聚合物层包括多个所述第二开口，分别暴露所述PPI结构的多个所述第二区域。
10.根据权利要求9所述的半导体器件，其中所述金属层填充所述聚合物层中的多个所述第二开口。
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US20200135659A1 (en) 2020-04-30
US20130147033A1 (en) 2013-06-13
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US10522481B2 (en) 2019-12-31
US20190074255A1 (en) 2019-03-07

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