CN102593044A - 形成金属柱的方法 - Google Patents

形成金属柱的方法 Download PDF

Info

Publication number
CN102593044A
CN102593044A CN2011104339181A CN201110433918A CN102593044A CN 102593044 A CN102593044 A CN 102593044A CN 2011104339181 A CN2011104339181 A CN 2011104339181A CN 201110433918 A CN201110433918 A CN 201110433918A CN 102593044 A CN102593044 A CN 102593044A
Authority
CN
China
Prior art keywords
metal column
organic compound
sidewall
substrate
contact pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011104339181A
Other languages
English (en)
Other versions
CN102593044B (zh
Inventor
林正怡
吴逸文
吕文雄
林志伟
杨宗翰
林修任
郑明达
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102593044A publication Critical patent/CN102593044A/zh
Application granted granted Critical
Publication of CN102593044B publication Critical patent/CN102593044B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11824—Chemical solution deposition [CSD], i.e. using a liquid precursor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11827—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/13693—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/136 - H01L2224/13691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本公开涉及金属柱的制造。制造半导体器件的示例性方法包括的步骤有：提供具有接触焊盘的衬底；形成钝化层，其在衬底上方延伸并且在接触焊盘上有开口；在接触焊盘和部分钝化层上形成金属柱；在金属柱上方形成焊接层；以及使金属柱的侧壁与有机化合物发生反应，以在金属柱的侧壁上形成该有机化合物的自组装单层或自组装多层。

Description

形成金属柱的方法
技术领域
本公开涉及集成电路制造，并且更具体地，涉及金属柱的制造。
背景技术
倒装芯片安装利用凸点建立芯片的接触焊盘与封装衬底之间的电接触。在结构上，凸点结构实际上包括凸点本身以及位于凸点和接触焊盘之间的所谓凸点凸点下金属(UBM)层。UBM层通常包括扩散势垒层(或接合层)和晶种层，按照这种顺序布置在接触焊盘上。基于凸点本身使用的材料，将其归类为焊料凸点、金制凸点、铜柱凸点和使用混合金属的凸点。近来，提出了铜柱凸点技术。与使用焊料凸点的电路相比，利用铜柱凸点与封装衬底连接的电路具有的微小间距有最小概率的凸点桥接，能够减小电路的电容负载，并且使得电子元件能够以高频率运行。
不过，在IC制造中实现这些特征和工艺还有很多挑战。例如，由于铜柱的氧化，使得电子元件与封装衬底间的粘附性较差。相应地，需要一种保护铜柱的方法。
发明内容
在一个实施例中，制造半导体器件的方法包括的步骤有：提供有接触焊盘的衬底，形成钝化层，该钝化层在衬底上延伸并且具有在接触焊盘上的开口；在接触焊盘和部分钝化层上形成金属柱；在金属柱上形成焊接层；并且使金属柱的侧壁与有机化合物发生反应以在金属柱的侧壁上形成有机化合物的自组装单层。
在另一实施例中，制造半导体器件的方法包括步骤：提供有接触焊盘的衬底；形成钝化层，该钝化层在衬底上延伸并且具有在接触焊盘上的开口；在接触焊盘和部分钝化层上形成金属柱；在金属柱上形成焊接层；并且使金属柱的侧壁与有机化合物发生反应，以在金属柱的侧壁上形成有机化合物的自组装多层。
参照附图，通过以下实施例进行详细说明。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的数量和尺寸可以被任意增加或减少
图1描绘了根据本公开多个方面包括金属柱的半导体器件的制造方法的流程图；
图2A-2H示出了根据本公开多个方面的在各制造阶段的半导体器件的金属柱的示意截面图；
图3描绘了根据本公开多个方面包括金属柱的半导体器件的制造方法的流程图；
图4A-4C示出了根据本公开多个方面的在各制造阶段的半导体器件的金属柱的示意截面图。
具体实施方式
可以理解的是，以下公开提供了多种不同实施例或实例，用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。为了简化和清楚起见，可以以不同比例随意地绘出各部件。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
参见图1，描绘了根据本公开的多个方面制造包括金属柱的半导体装置的方法100的流程图。方法100从步骤102开始，该步骤提供具有接触焊盘的衬底。方法100继续进行到步骤104，该步骤形成钝化层，其在衬底上方延伸并且具有在接触焊盘上方的开口。方法100进行到步骤106，该步骤在接触焊盘和部分钝化层上方形成金属柱。方法100进行到步骤108，该步骤在金属柱上方形成焊接层。方法100进行到步骤110，该步骤使金属柱的侧壁与有机化合物发生反应，以在金属柱的侧壁上形成该有机化合物的自组装单层。以下论述说明了根据图1的方法的实施例。
图2A-2H示出了半导体器件200的金属柱220在图1的方法的各制造阶段的示意截面图。可以注意到，图1的方法没有生产出成品半导体器件200。相应地，可以理解的是，还可以在图1的方法100之前、期间和之后提供另外的工艺，并且此处仅仅简单描述部分其他工艺。另外，简化了图2A-2H以更好的理解本公开的发明思想。例如，虽然图形描绘了半导体器件200的金属柱220，可以理解的是，半导体器件200可以是IC封装的一部分，该IC封装进一步包括数个其他元件，例如底部填充、引线框架等。
参见图2A，提供了衬底202。提供衬底202的步骤可以进一步包括在衬底202上部分地制造一个或多个接触焊盘204。衬底202包括硅衬底。可选地，衬底202包括硅锗、砷化镓，或其他合适的半导体材料。而且，衬底202可以是绝缘体上半导体，例如绝缘体上硅(SOI)或蓝宝石上硅。在其他实施例中，衬底202可以包括掺杂外延层、梯度半导体层，和/或进一步包括叠加在另一不同种类半导体层上的半导体层，例如硅锗层上的硅层。在其他实施例中，复合半导体衬底202可以包括多层硅结构，或者硅衬底包括多层复合半导体结构。
衬底202可以进一步包括多个隔离部件(未示出)，例如浅沟隔离(STI)部件或硅的局部氧化(LOCOS)部件。这些隔离部件可以限定并隔离各种微电子元件(未示出)。
可以在衬底202中形成的各种微电子元件的示例包括晶体管(例如p-沟道/n-沟道金属氧化物半导体场效应晶体管(pMOSFET/nMOSFET)、双极结型晶体管(BJTs)、高压晶体管、高频晶体管等)、二极管、电阻器、电容器、感应器、保险丝、和/或其他适合的元件。被执行以形成各种微电子元件的各种工艺包括沉积、光刻法、注入、蚀刻、热处理、和/或其他适合的工艺。使微电子元件相互连接以形成集成电路器件，例如逻辑器件、存储器件(例如静态随机存取存储器或SRAM)、无线射频(RF)器件、输入/输出(I/O)器件、片上系统(SoC)器件、以及其组合，和/或其他适合的器件种类。
衬底202进一步包括层间绝缘(ILD)层、金属间绝缘(IMD)层和叠加在集成电路器件上的金属化结构。金属化结构中的IMD层包括低介电常数(低k)绝缘材料、未掺杂硅酸盐玻璃(USG)、氟掺杂硅酸盐玻璃(FSG)、碳掺杂硅酸盐玻璃、氮化硅、氮氧化硅、或其他通常使用的材料。低k绝缘材料的介电常数(k值)可以大约小于3.9，或大约小于2.3。金属化结构中的金属线可以由铝、铝合金、铜、铜合金、或其他导电材料形成。本领域普通技术人员能够认识到金属化结构的形成细节。
接触焊盘204是形成在上层IMD层203中的顶部金属化层，该层是导电通路的一部分并且具有经过平面化工艺(例如化学机械抛光(CMP))处理的暴露面(如果必要的话)。适用于接触焊盘204的材料包括，但不仅限于，例如铝、铝合金、铜、铜合金、或其他导电材料。接触焊盘204用于结合工艺以连接相应芯片中的集成电路和外部部件。
然后，在衬底202上方延伸形成钝化层206并且将其图案化以形成第一开口208，其层叠在部分接触焊盘204上并露出部分接触焊盘以允许后续的金属柱凸点工艺。钝化层206由非有机材料形成，包括未掺杂硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅、或前述的组合。在部分可选实施例中，钝化层包括聚合物层，例如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并噁唑(PBO)、或类似物，虽然也可以使用其他相对比较软、通常为有机的、绝缘材料。在至少一个实施例中，可以使用化学汽相沉积(CVD)、高密度等离子体CVD(HDP CVD)、次大气压CVD(SACCVD，或次常压CVD)、物理汽相沉积(PVD)或旋涂式工艺形成钝化层206。
参见图2B，在钝化层206中形成第一开口208的工艺之后，在接触焊盘204和钝化层206上方形成凸点下金属层(UBM)层210。UBM层210包括形成的具有单层或多层结构的可应用UBM材料。在本实施例中，UBM层210包括第一凸点下金属层(UBM)子层212和位于第一UBM子层212上方的第二凸点下金属层(UBM)子层214。
在本实施例中，第一UBM子层212形成在接合焊盘204的露出部分上，并且延伸至部分钝化层206。还将第一UBM子层212称为扩散势垒层或粘合层，其包括经过PVD或溅射的钛、钽、氮化钛、氮化钽、或类似物。沉积第一UBM子层212，使其厚度范围为约500至1200埃。在至少一个实施例中，也被称为晶种层的第二UBM子层214由经过PVD或溅射的铜形成。在另一实施例中，第二UBM子层214可以由包括银、铬、镍、锡、金、或其组合的铜合金形成。沉积第二UBM子层214，使其厚度范围为约2000至7000埃。
然后在UBM层210上方形成光敏层216。光敏层216可以是干膜或光刻胶膜，其厚度范围为约40微米(μm)至约120微米(μm)。可以理解的是，在部分实施例中，根据将要形成的金属柱凸点材料的柱体厚度，可以控制光敏层216的厚度并将其选择为预定值。在本实施例中，通过传统工艺图案化光敏层216以形成第二开口218，其环绕钝化层206的第一开口208。第二开口218露出部分UBM层210用以限定金属柱220的窗口(window)(在图2C至2H和图4A至4C中示出)。
需要说明的是，较大横截面的金属柱220提供了较高的机械强度和用于芯片倒装安装的较低电阻。这样，不仅要布置光敏层216使其具有用于形成金属柱220的预定厚度，还要布置第二开口218使其具有比钝化层206的第一开口208更宽的宽度，从而提供较大的横截面以降低金属柱220的电阻。
然后，向第二开口部分地填充具有焊料润湿性的金属材料。参见图2C，在部分实施例中，利用下层的UBM层210作为晶种层沿第二开口218向上形成金属层220。在本实施例中，金属层220包括铜层。铜层基本由包括纯元素的铜、含有不可避免的杂质的铜、以及含有少量元素的铜合金的层组成，这些元素包括钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆。金属层220和第二UBM子层214可以包括同样材料，例如铜。
可以通过溅射、印刷、电镀、化学镀、和/或CVD等方法形成铜层220。例如，执行电化学镀(ECP)以形成金属层220。在一个示例实施例中，金属层220的厚度大于15μm。在另一个示例实施例中，金属层220的厚度大于40μm。例如，金属层220的厚度约为40-60μm或约为60-120μm，不过该厚度可以更大或更小。在下文中将金属层220称为金属柱220。
进一步，在光敏层216的开口218中的金属柱220顶部表面上形成金属覆盖层222。金属覆盖层222可以作为势垒层以防止金属柱220中的铜扩散至接合材料中，例如用于将衬底202和外部部件接合的焊接合金。防止铜扩散可以增加封装的可靠性和接合强度。金属覆盖层222是金属化层，其可以包括镍、锡、金、银、钯、铟、锡铅(SnPb)、镍钯金(NiPdAu)、镍金(NiAu)、其他类似材料、或合金。金属覆盖层222可以包括单层结构或多层结构。在至少一个实施例中，金属覆盖层222的厚度约为1-5μm。
然后，在光敏层216的开口218中的金属覆盖层222上方形成焊接层224。焊接层224作为衬底202的连接终端。焊接层224可以由Sn、SnAg、Sn-Pb、SnAgCu(其中铜的重量百分比小于0.5％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu(其中铜的重量百分比小于0.7％)、SnZnIn、或SnAgSb等。在至少一个实施例中，焊接层224由无铅焊材料层形成。
参见图2D，在光敏层216的开口218中形成焊接层224之后，使用适用的湿式蚀刻或干式蚀刻工艺移除光敏层216，以暴露出部分UBM层210。在光敏层216是干膜时，可以使用碱性溶液将其移除。由此得到的结构包括金属柱220、金属覆盖层222和焊接层224，并且还暴露出金属柱220的侧壁220s。
然后，利用由此得到的结构(包括层220、222、和224)作为硬掩膜，取决于UBM材料的冶金性(metallurgy)通过适用的湿蚀刻和/或干蚀刻工艺回蚀第二UBM子层214的暴露部分。在至少一个实施例中，湿蚀刻工艺包括移除部分第二UBM子层214，该层包括在含有H3PO3和H2O2的溶液中的铜。
进一步，利用由此产生的结构(现在包括层220、222、224和第二UBM子层214)作为硬掩膜，然后通过适用的湿和/或干蚀刻工艺移除部分第一UBM子层212以暴露出钝化层206。在至少一个实施例中，其中第一UBM子层212包括钛、钽、氮化钛或氮化钽，利用F、Cl、或Br基蚀刻剂执行移除部分第一UBM子层212的干蚀刻工艺步骤。
之后，使图2D中的半导体器件200经受回流处理以融化焊接层224，以便在金属柱220上方形成半球状焊料凸点224a(在图2E中示出)，例如通过晶片加热或快速热处理(RTP)。至此的工艺步骤提供了具有凸点结构230的衬底202，凸点结构包括金属柱220、金属覆盖层222和半球状焊接层224。
应该说明的是，包括铜的金属柱220(也被称为铜柱220)有在制造工艺中被氧化的可能。被氧化的铜柱220会导致电子元件与衬底间的低粘附强度。由于高泄漏电流，低粘附强度会引起严重的可靠性问题。被氧化的铜柱220还会导致沿底层材料和铜柱220的接触面的底层开裂。该开裂会扩散至下层的低介电常数(低k)绝缘层或扩散至用于将铜柱220和衬底相接合的焊料。
相应地，以下参见图2F-2H和4A-4C讨论的工艺可以形成侧壁防护层以防护铜柱220的暴露出的侧壁220s。该侧壁防护层保护铜柱220不被氧化并改进器件性能。
图2F示出了在使金属柱220的侧壁220s与有机化合物发生反应以在金属柱220的侧壁220s上形成有机化合物的自组装单层226a之后的图2E的半导体器件200。在至少一个实施例中，有机化合物包括，但不限于首基(head group)、官能团以及首基和官能团之间的尾基，其中首基是硫醇基(-SH)。在部分实施例中，官能团包括CH3、OH、NH2和/或COOH；并且尾基包括具有4至20个碳的碳链。
自组装单层226a的膜形成过程是在溶液或汽相中金属柱220的侧壁220s处的有机化合物的首基的化学吸附，随后尾基的不活跃的(slow)两维接合(two-dimensional organization)以在金属柱220的侧壁220s上形成有机化合物的自组装单层226a。在本实施例中，金属柱220的侧壁220s与有机化合物的反应步骤在约为20至50℃的温度下执行。现在准备焊接金属柱220并保护其不被氧化，直到完成焊接步骤。
此外，可以在使金属柱220的侧壁220s与有机化合物发生反应的步骤之前，执行利用去离子水、柠檬酸和异丙醇(IPA)清洁金属柱220的侧壁220s的步骤。进一步，可以在使金属柱220的侧壁220s与有机化合物发生反应的步骤之后，执行利用IPA处理衬底202的步骤。
然后，锯下衬底202并将其与另一衬底232连接。图2G的结构示出了衬底202被倒转并在底部与衬底232连接。衬底232可以是封装衬底、板(例如印刷电路板(PCB))、另一小片、或其他适合衬底。在本实施例中，预焊接层236安装在封装衬底232上的接触焊盘234上。提供熔接剂(flux)238，使其围绕在衬底202和封装衬底232之间的凸点结构230和预焊接层236周围。
之后，加热图2G的结构使焊料凸点224a和预焊接层236回流以形成接合结构240(图2H)，其连接两个衬底202、232。然后，去除熔接剂238用于更进一步的工艺。衬底202、接合结构240和封装衬底232可以称作封装组件，或者在本实施例中称作倒装芯片封装组件(在图2H中示出)。应该说明的是，在去除熔接剂之前，自组装单层226a隔离了金属柱220的侧壁220s，使其不被氧化，从而保护了金属柱220的侧壁220s。相应地，申请人的制造半导体器件200的方法可以制造金属柱220，其具有保护性的自组装单层226a以避免电子元件与衬底间的低粘附强度并且改进器件性能。
图3是根据本公开多个方面制造包括金属柱的半导体器件的另一示例方法300的流程图。方法300从步骤302开始，该步骤提供了具有接触焊盘的衬底。方法300继续到步骤304，其中形成在衬底上延伸且在接触焊盘上方具有开口的钝化层。方法300继续到步骤306，其中在接触焊盘和部分钝化层上形成金属柱。方法300继续到步骤308，其中在金属柱上形成焊接层。方法300继续到步骤310，其中使金属柱的侧壁与有机化合物发生反应以在金属柱的侧壁上形成有机化合物的自组装多层。以下论述说明了根据图3的方法的实施例。
图4A-4C示出了在图3方法的各制造阶段的半导体器件的金属柱220的示意截面图。要说明的是，图3的方法并没有生产出成品半导体器件400。相应地，可以理解的是，在图3的方法300之前、期间、之后可以提供另外的工艺，并且此处只简单描述了部分其他工艺。另外，简化了图4A至4C以更好的理解本公开的发明思想。例如，虽然图中描绘了半导体器件400的金属柱220，可以理解的是，半导体器件400可以是IC封装的一部分，该IC封装进一步包括数个其他元件，例如底层填料、引线框架等。
图4A示出了使金属柱220的侧壁220s与有机化合物发生反应以在金属柱220的侧壁220s上形成有机化合物426的自组装多层426a之后的半导体器件400。在本实施例中，在大约20至50℃的温度下，在溶液中执行使金属柱220的侧壁220s与有机化合物426发生反应的步骤。溶液包括有机化合物和金属离子，金属离子包括锌离子、铜离子、镍离子、钴离子、铁离子、或前述的组合。在至少一个实施例中，有机化合物包括苯并咪唑或苯并咪唑衍生物，例如1-甲基苯并咪唑或2-三氟甲基苯并咪唑。在另一实施例中，有机化合物包括咪唑或咪唑衍生物，例如烷基咪唑或烷基苯并咪唑。
当向包括铜的金属柱220的侧壁220s施加包括咪唑的溶液时，咪唑和铜表面的铜离子发生反应，形成不溶性铜咪唑合成物，其沉积在金属柱220的侧壁220s上并在其上形成自组装多层426a。进一步，添加至包括咪唑的溶液中的金属粒子帮助促进铜咪唑合成物的形成速度。现在，准备焊接金属柱220并保护其不被氧化，直到完成焊接步骤。
此外，可以在使金属柱220的侧壁220s与有机化合物发生反应步骤之前，执行利用酸性溶液清洁金属柱220的侧壁220s的步骤。进一步，可以在使金属柱220的侧壁220s与有机化合物发生反应步骤之后，执行利用惰性气体干燥衬底202的步骤。
然后，锯下衬底202并将其与另一衬底432连接。图4B的结构示出了翻转衬底202并使其底部与衬底432连接。衬底432可以是封装衬底、板(例如，印刷电路板(PCB))、其他小片、或其他合适的衬底。在本实施例中，预焊接层436安装在封装衬底432上的接触焊盘434上。提供熔接剂438，使其围绕衬底202和封装衬底432之间的凸点结构230和预焊接层436。
之后，加热图4B的结构以回流焊料凸点224a和预焊接层436以形成接合结构440(图4C)，其连接两个衬底202、432。然后去除熔接剂438用于更进一步工艺。可以将衬底202、接合结构440，以及封装衬底432称作封装组件，或在本实施例中称为倒装芯片组件(在图4C中示出)。应该说明的是，在去除熔接剂之前，自组装多层426a隔离金属柱220的侧壁220s，使其不被氧化，从而保护了金属柱220的侧壁220s。相应地，申请人的制造半导体器件400的方法可以制造金属柱220，其有防护性自组装多层426a以避免电子元件与衬底间的低粘附强度并且提高器件性能。
可以理解的是，半导体器件200、400可以经受进一步半导体制造工艺以形成各种部件，例如底层填料、引线框架等。
虽然以示例和相关参考示例的方式描述了本公开，可以理解的是本发明不限于公开的实施例。相反地，本发明试图覆盖各种修改和类似布置(正如对于本领域普通技术人员显而易见的)。而且，应给予随附的权利要求最广泛的解释，以便涵盖所有这样的修改和类似布置。

Claims (10)

1.一种用于制造半导体器件的方法，包括：
提供有接触焊盘的衬底；
形成钝化层，其在所述衬底上方延伸并且在所述接触焊盘上具有开口；
在所述接触焊盘和部分所述钝化层上方形成金属柱；
在所述金属柱上方形成焊接层；以及
使所述金属柱的侧壁与有机化合物发生反应以在所述金属柱的侧壁上形成所述有机化合物的自组装单层。
2.根据权利要求1所述的方法，其中所述有机化合物在溶液中，其中在大约20至50摄氏度的温度下执行使所述使金属柱的侧壁与有机化合物发生反应的步骤。
3.根据权利要求1所述的方法，其中所述有机化合物处于液相。
4.根据权利要求1所述的方法，其中所述有机化合物包括首基、官能团以及所述首基和官能团之间的尾基，其中所述首基是硫醇基(-SH)，其中所述官能团包括CH3、OH、NH2、或COOH，其中所述尾基包括碳数在4至20之间的碳链。
5.根据权利要求1所述的方法，其中所述金属柱是铜柱，所述方法进一步包括：在使所述金属柱的侧壁与有机化合物发生反应之前，利用去离子水、柠檬酸和IPA清洁所述金属柱的侧壁；以及
在使所述金属柱的侧壁与有机化合物发生反应之后，利用IPA处理所述衬底。
6.一种用于制造半导体器件的方法，包括：
提供有接触焊盘的衬底；
形成钝化层，所述钝化层在所述衬底上方延伸并且在所述接触焊盘上具有开口；
在所述接触焊盘和部分所述钝化层上形成金属柱；
在所述金属柱上方形成焊接层；以及
使所述金属柱的侧壁与有机化合物发生反应，以在所述金属柱的侧壁上形成所述有机化合物的自组装多层。
7.根据权利要求6所述的方法，其中所述有机化合物在溶液中，其中所述溶液包括的金属离子有锌离子、铜离子、镍离子、钴离子、铁离子或其组合，其中在约20至50℃的温度下执行使所述金属柱的侧壁与有机化合物发生反应的步骤，其中所述有机化合物包括苯并咪唑或苯并咪唑衍生物。
8.根据权利要求6所述的方法，其中所述有机化合物包括咪唑或咪唑衍生物。
9.根据权利要求6所述的方法，其中所述金属柱是铜柱。
10.根据权利要求6所述的方法，进一步包括：在使所述金属柱的侧壁与有机化合物发生反应之前，利用酸性溶液清洁所述金属柱的侧壁；以及
在使所述金属柱的侧壁与有机化合物发生反应之后，利用惰性气体干燥所述衬底。
CN201110433918.1A 2011-01-11 2011-12-21 形成金属柱的方法 Active CN102593044B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/004,376 US8242011B2 (en) 2011-01-11 2011-01-11 Method of forming metal pillar
US13/004,376 2011-01-11

Publications (2)

Publication Number Publication Date
CN102593044A true CN102593044A (zh) 2012-07-18
CN102593044B CN102593044B (zh) 2015-02-18

Family

ID=46455594

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110433918.1A Active CN102593044B (zh) 2011-01-11 2011-12-21 形成金属柱的方法

Country Status (3)

Country Link
US (1) US8242011B2 (zh)
CN (1) CN102593044B (zh)
TW (1) TWI462248B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572257B (zh) * 2015-10-19 2017-02-21 欣興電子股份有限公司 柱狀結構及其製作方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161136A (ja) * 2009-01-07 2010-07-22 Panasonic Corp 半導体装置及びその製造方法
US8692390B2 (en) * 2011-02-18 2014-04-08 Chipbond Technology Corporation Pyramid bump structure
US8664760B2 (en) 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
US8610285B2 (en) 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
KR20130007124A (ko) * 2011-06-29 2013-01-18 삼성전자주식회사 유기 보호막을 갖는 조인트 구조
US8518818B2 (en) 2011-09-16 2013-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse damascene process
US8970034B2 (en) * 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures
TWI484610B (zh) * 2012-07-09 2015-05-11 矽品精密工業股份有限公司 半導體結構之製法與導電凸塊
KR20140100144A (ko) 2013-02-05 2014-08-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법
JP2014203963A (ja) * 2013-04-04 2014-10-27 三菱マテリアル株式会社 ピラー付バンプを有する基板の製造方法及びピラー付バンプ用表面処理溶液
US20150048499A1 (en) * 2013-08-16 2015-02-19 Macrotech Technology Inc. Fine-pitch pillar bump layout structure on chip
US9190376B1 (en) * 2014-05-15 2015-11-17 International Business Machines Corporation Organic coating to inhibit solder wetting on pillar sidewalls
JP2016213238A (ja) * 2015-04-30 2016-12-15 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US10593638B2 (en) * 2017-03-29 2020-03-17 Xilinx, Inc. Methods of interconnect for high density 2.5D and 3D integration
US10636758B2 (en) 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
TWI734115B (zh) * 2019-05-17 2021-07-21 樂鑫材料科技股份有限公司 背晶薄膜結構、包含其之功率模組封裝體、及背晶薄膜結構的製造方法
JP7255397B2 (ja) * 2019-07-10 2023-04-11 株式会社デンソー 電子装置
FR3104316B1 (fr) * 2019-12-04 2021-12-17 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104317A1 (fr) 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques
FR3104315B1 (fr) * 2019-12-04 2021-12-17 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
US11849566B2 (en) * 2020-10-29 2023-12-19 Denso Corporation Joint structure, electronic device and method for manufacturing the joint structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US6518168B1 (en) * 1995-08-18 2003-02-11 President And Fellows Of Harvard College Self-assembled monolayer directed patterning of surfaces
CN1567583A (zh) * 2003-06-09 2005-01-19 宏起股份有限公司 芯片型电子组件的外端电极材料及其制备方法
US20070228567A1 (en) * 2004-09-28 2007-10-04 Michael Bauer Semiconductor Chip Comprising A Metal Coating Structure And Associated Production Method
US20090023288A1 (en) * 2007-07-19 2009-01-22 Electronics And Telecommunications Research Institute Method of manufacturing nanoelectrode lines using nanoimprint lithography process

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030119692A1 (en) * 2001-12-07 2003-06-26 So Joseph K. Copper polishing cleaning solution
US20030162398A1 (en) * 2002-02-11 2003-08-28 Small Robert J. Catalytic composition for chemical-mechanical polishing, method of using same, and substrate treated with same
US20050003652A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
KR20100091663A (ko) * 2009-02-11 2010-08-19 삼성전자주식회사 표면개질제, 이를 사용하여 제조된 적층 구조, 그 구조의 제조방법 및 이를 포함하는 트랜지스터
US8377816B2 (en) * 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US6518168B1 (en) * 1995-08-18 2003-02-11 President And Fellows Of Harvard College Self-assembled monolayer directed patterning of surfaces
CN1567583A (zh) * 2003-06-09 2005-01-19 宏起股份有限公司 芯片型电子组件的外端电极材料及其制备方法
US20070228567A1 (en) * 2004-09-28 2007-10-04 Michael Bauer Semiconductor Chip Comprising A Metal Coating Structure And Associated Production Method
US20090023288A1 (en) * 2007-07-19 2009-01-22 Electronics And Telecommunications Research Institute Method of manufacturing nanoelectrode lines using nanoimprint lithography process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572257B (zh) * 2015-10-19 2017-02-21 欣興電子股份有限公司 柱狀結構及其製作方法

Also Published As

Publication number Publication date
TW201230271A (en) 2012-07-16
US20120178251A1 (en) 2012-07-12
TWI462248B (zh) 2014-11-21
CN102593044B (zh) 2015-02-18
US8242011B2 (en) 2012-08-14

Similar Documents

Publication Publication Date Title
CN102593044B (zh) 形成金属柱的方法
US11515288B2 (en) Protective layer for contact pads in fan-out interconnect structure and method of forming same
US10290600B2 (en) Dummy flip chip bumps for reducing stress
US9685372B2 (en) Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap
CN102237317B (zh) 集成电路元件与封装组件
KR101539491B1 (ko) 삼차원 칩 스택 및 그 형성방법
TWI459523B (zh) 封裝裝置、積體電路元件及其製作方法
CN102005417B (zh) 用于铜柱结构的自对准保护层
CN105390473B (zh) 集成电路装置及封装组件
CN102456657B (zh) 具有底部凸块金属化(ubm)结构的半导体器件及其形成方法
CN102456653B (zh) 凸点下金属化层(ubm)结构及其形成方法
CN102148201B (zh) 半导体元件、封装结构、及半导体元件的形成方法
CN102347298B (zh) 基板上的凸块结构与其形成方法
KR101708981B1 (ko) 반도체 디바이스 구조 및 제조 방법
CN102254870A (zh) 集成电路元件、其形成方法及封装组件
CN104425437A (zh) 三维芯片堆叠件及其形成方法
CN102237316A (zh) 集成电路元件及凸块结构的形成方法
CN102222647A (zh) 半导体裸片及形成导电元件的方法
TWI419285B (zh) 基板上的凸塊結構與其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant