CN102222647A - 半导体裸片及形成导电元件的方法 - Google Patents

半导体裸片及形成导电元件的方法 Download PDF

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CN102222647A
CN102222647A CN2010105341926A CN201010534192A CN102222647A CN 102222647 A CN102222647 A CN 102222647A CN 2010105341926 A CN2010105341926 A CN 2010105341926A CN 201010534192 A CN201010534192 A CN 201010534192A CN 102222647 A CN102222647 A CN 102222647A
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width
layer
opening
joint sheet
substrate
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CN102222647B (zh
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黄见翎
吴逸文
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种半导体裸片，包括一基底；一接合垫，形成于基底上方，接合垫具有一第一宽度；一聚酰亚胺层，形成于基底和接合垫上方，聚酰亚胺层于接合垫上方具有一第一开口，第一开口有一第二宽度；一硅基保护层，位于聚酰亚胺层上，硅基保护层于接合垫上方具有一第二开口，第二开口有一第三宽度，其中第一开口和第二开口形成一具有侧壁的组合开口，暴露部分接合垫；一凸块下金属化层，位于组合开口的侧壁上方，且接触接合垫的暴露部分；及一导电元件，位于凸块下金属化层上。本发明各实施例可用来改进传统焊锡凸块工艺的缺点；在各实施例中，硅基保护层保护聚酰亚胺层，防止其受到后续等离子体清洁工艺的损伤；聚酰亚胺层中开口的宽度与硅基保护层中开口的宽度相对于接合垫的宽度的比例的适当范围可改进构件的良率。

Description

半导体裸片及形成导电元件的方法
技术领域
本发明涉及一种半导体封装工艺，特别涉及一种倒装芯片封装的导电元件(Conductive feature)的结构和制造方法。
背景技术
倒装芯片技术在半导体元件封装中扮演重要的角色。倒装芯片微电子构件包括电子组件面向下与例如电路板的基底直接电性接触，其使用焊锡凸块作为内连线。倒装芯片封装由于相较于其它封装方法在尺寸、效能和灵活性上的优点，因而被大量采用。
然而，标准的凸块制造方法具有许多缺点。举例来说，聚酰亚胺(polyimide)层可能在制造工艺中产生损坏，聚酰亚胺层的表面上可能会残留一些污染。因此，增加总体组件的失效率(failure rate)。
因此，业界需要改进结构和方法，以形成具有良好电性表现的半导体晶片的导电元件。
发明内容
为了解决现有技术中存在的上述问题，本发明提供一种半导体裸片，包括一基底；一接合垫，位于基底上方，接合垫具有一第一宽度；一聚酰亚胺层，位于基底和接合垫上方，聚酰亚胺层于接合垫上方具有一第一开口，第一开口有一第二宽度；一硅基保护层，位于聚酰亚胺层上，硅基保护层于接合垫上方具有一第二开口，第二开口有一第三宽度，其中第一开口和第二开口形成一具有侧壁的组合开口，暴露部分接合垫；一凸块下金属化层，位于组合开口的侧壁上方，且接触接合垫的暴露部分；及一导电元件，位于凸块下金属化层上。
本发明提供一种半导体裸片，包括一基底；一低介电常数介电层，位于基底上方；一接合垫，位于低介电常数介电层上方，接合垫具有一第一宽度；一聚酰亚胺层，位于基底和接合垫上方，聚酰亚胺层包括具有第二宽度的第一开口；一氮化硅层，直接位于聚酰亚胺层上方，氮化硅层包括一具有第三宽度的第二开口，其中第一开口和第二开口形成一具有侧壁的组合开口，暴露部分接合垫，且第二宽度小于第三宽度；一凸块下金属化层，衬垫组合开口的侧壁，位于氮化硅层的顶部部分上，且接触接合垫的暴露部分；及一导电元件，位于凸块下金属化层上。
本发明提供一种形成导电元件的方法，包括：形成一接合垫于一基底上方，接合垫具有一第一宽度；形成一聚酰亚胺层于基底和接合垫上方，聚酰亚胺层于接合垫上方具有一第一开口，第一开口有一第二宽度；形成一硅基保护层于聚酰亚胺层上，硅基保护层于接合垫上方具有一第二开口，第二开口有一第三宽度，其中第一开口和第二开口形成一具有侧壁的组合开口，暴露部分接合垫；形成一凸块下金属化层于组合开口的侧壁上方，且接触接合垫的暴露部分；及形成一导电元件于凸块下金属化层上。
本发明各实施例可用来改进传统焊锡凸块工艺的缺点；在各实施例中，硅基保护层保护聚酰亚胺层，防止其受到后续等离子体清洁工艺的损伤；聚酰亚胺层中开口的宽度与硅基保护层中开口的宽度相对于接合垫的宽度的比例的适当范围可改进构件的良率。
附图说明
图1-图8显示本发明实施例制造一导电元件的各阶段的剖面图。
主要附图标记说明：
101～基底；          103～内连线层；
105～保护层；        107～接合垫；
108～侧壁；          109～聚酰亚胺层；
111～开口；          113～硅基保护层；
114～侧壁；          115～组合开口；
117～凸块下金属化层；118～顶部部分；
119～导电元件。
具体实施方式
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一较佳实施例，并配合附图，作详细说明如下。
以下详细讨论许多不同实施例的制造和使用，然而，值得注意的是，本揭示提供许多可应用的发明概念，其可以各种特定方式实施。以下所讨论的实施例仅是用来揭示，并不用来限定本发明。
图1-图8显示本发明实施例制造一结构各阶段的剖面图。在此用的“基底”这个名词是指表面上形成有各种膜层和集成电路组件的半导体基底。在一些实施例中，基底包括硅或化合物半导体，例如GaAS、InP、Si/Ge或SiC。膜层的范例包括介电层、掺杂层、金属层、多晶硅层和连接一层或多层的插塞。集成电路组件的范例包括晶体管、电阻和/或电容。基底包括制作于基底表面上的多个半导体裸片(die)，其中每个裸片包括一或多个集成电路。上述半导体裸片以裸片间的切割线(未示出)分隔。以下的工艺步骤将会于基底表面的多个半导体裸片上进行。
请参照图1，提供一表面具有多个半导体裸片(未示出)的基底101。图1的部分基底101仅包括其中一个裸片的部分。形成多个内连线层103于基底101的表面，内连线层103包括一或多个导电层，设置于一或多个介电层中。导电层电性连接集成电路组件，且提供集成电路至上层的电性连接。在一些实施例中，内连线层103中的介电层是由例如低介电常数材料(k值介于2.9至3.8之间)、超低介电常数材料(k值介于2.5至2.9之间)、低介电常数材料的组合，或以类似的材料组成。一般来说，低介电常数材料的介电常数越低，其越容易产生破裂或分层(delamination)。
于内连线层103上方形成一保护层105，以保护集成电路和内连线层103，防止其受到损坏和污染。在一些实施例中，保护层105包括一或多个层，例如氧化物、未掺杂硅玻璃(USG)、氮化硅、二氧化硅或氮氧化硅。保护层105防止或减少集成电路受到的水气、机械和辐射损坏(radiation damage)。
请继续参照图1，形成一接合垫107于保护层105上方，接合垫107具有第一宽度W1。接合垫107接触内连线层103中的导电层，且提供其下的集成电路电性连接。在一实施例中，接合垫107包括电性导电材料，例如铝、铝合金、铜、铜合金或上述的组合。在一些实施例中，接合垫107由以下步骤形成：使用铝、铜或上述合金的靶材进行溅镀沉积工艺，后续以光刻和蚀刻工艺图案化沉积的膜层，以形成接合垫107。
请参照图2，形成一聚酰亚胺(polyimide)层109于保护层105和接合垫107上方。聚酰亚胺层109的厚度约介于3μm～10μm之间。在一些实施例中，聚酰亚胺层109以传统的沉积技术(例如旋转涂布法)沉积于保护层105和接合垫107上方。在沉积工艺后，进行光刻和蚀刻工艺，以于接合垫107上选择性的定义一开口111。聚酰亚胺层109覆盖部分的接合垫107，且保留部分的接合垫107表面于开口111中暴露。开口111具有一第二宽度W2和侧壁108。第二宽度W2与第一宽度W1的比例约为0.15～0.6。聚酰亚胺层109作为一应力缓冲，以减少组装工艺中，传送至保护层105的应力。
请参照图3，形成一硅基保护层113(silicon-based protection layer)于聚酰亚胺层109和接合垫107上方。硅基保护层113的厚度约为0.035μm～1.2μm。当沉积硅基保护层113时，其直接位于聚酰亚胺层109上，且填入开口111，覆盖接合垫107的暴露表面。接着进行光刻和图案化工艺，以定义一组合开口115，其中组合开口115包括宽度为W2的聚酰亚胺层109中的开口，以及宽度为W3的硅基保护层113中的开口。组合开口115暴露部分的接合垫107，且组合开口115具有侧壁114。第三宽度与第一宽度的比例(W3/W1)约为0.15～0.6。硅基保护层113为含硅材料，例如氮化硅、氮氧化硅、氧化硅或碳化硅。硅基保护层113的硬度较聚酰亚胺层109高。硅基保护层113保护聚酰亚胺层109，以防止后续等离子体清洁工艺受到损伤，且可在凸块工艺中，吸收或释放热、机械应力。
构件的良率和聚酰亚胺层109中开口的宽度W2与硅基保护层113中开口的宽度W3相对于接合垫的宽度W1的比例有关。当比例(W3/W1或W2/W1)小于0.15，构件的失效率可能会提升。当比例(W3/W1或W2/W1)大于0.6，其下的内连线层103中的低介电常数介电层，可能会在构装工艺中破裂。
请参照图4，形成一凸块下金属化(under bump metallurgy，UBM)层117(例如包括一第一凸块下金属化层和一第二凸块下金属化层)于硅基保护层113上方，作为组合开口115侧壁114的内衬，且接触接合垫107的暴露部分。在一些实施例中，凸块下金属化层117包括多层导电材料，例如钛层、铜层和镍层。凸块下金属化层117中的各层较佳使用电镀工艺形成，例如电化学镀法(electrochemical plating)，而本实施例另可依照所需材料使用其它的工艺，例如溅镀、蒸镀、无电镀或等离子体辅助化学气相沉积法工艺。
接着，形成一光致刻蚀剂层(未示出)于凸块下金属化层117上方，且进行显影以形成暴露组合开口115中凸块下金属化层117和位于接合垫107的暴露部分上方的孔洞。光致刻蚀剂层作为形成导电元件的金属沉积工艺的铸模(mold)。在一些实施例中，以蒸镀、电镀或网版印刷法沉积一导电材料于上述孔洞中，于凸块下金属化层117上方形成如图5所示的柱形导电元件119。导电材料包括各种金属、金属合金、其它材料和包括锡和铜的导电材料的混合。
在移除光致刻蚀剂层之后，借由反应离子蚀刻工艺移除未被导电元件覆盖的凸块下金属化层117，向下蚀刻凸块下金属化层117暴露的部分至其下的硅基保护层113。导电元件119下剩余的凸块下金属化层117位于组合开口115的侧壁114上方，且也位于硅基保护层113的顶部部分上方，且接触接合垫107的暴露部分。在一实施例中，导电元件119是一铜柱。在另一实施例中，导电元件119是一焊锡，其中焊锡是借由加热形成一焊锡凸块。
图6-图8揭示本发明具有不同尺寸的第一宽度W1和第二宽度W2的形成于凸块下金属化层117上的导电元件119的各范例。图6揭示聚酰亚胺层109的第二宽度W2大体上和硅基保护层113的第三宽度W3相同。组合开口115暴露部分的接合垫107。凸块下金属化层117形成于组合开口115上方，也位于硅基保护层113的顶部部分上方，且接触接合垫107的暴露部分。导电元件119位于凸块下金属化层117上。
图7揭示本发明另一实施例。在此实施例中，聚酰亚胺层109的第二宽度W2大于硅基保护层113的第三宽度W3。在此实施例中，由于硅基保护层113在组合开口115中覆盖聚酰亚胺层109，组合开口115的侧壁114完全由部分的硅基保护层113形成。接合垫107经由组合开口115暴露。在此实施例中，凸块下金属化层117也位于硅基保护层113的顶部部分上，且经由组合开口115接触接合垫107的暴露部分。导电元件119位于凸块下金属化层117上。
图5揭示本发明的另一实施例。在此实施例中，聚酰亚胺层109的第二宽度W2小于硅基保护层113的第三宽度W3。因此，聚酰亚胺层109的顶部部分118经由组合开口115暴露。凸块下金属化层117位于硅基保护层113和聚酰亚胺层109的顶部部分上，且衬垫组合开口115的侧壁114。导电元件119位于凸块下金属化层117上方。在一些其它的实施例中，例如图8所示的实施例，凸块下金属化层117不位于硅基保护层113的顶部部分上。
本发明各实施例可用来改进传统焊锡凸块工艺的缺点。举例来说，在各实施例中，硅基保护层113保护聚酰亚胺层109，防止其受到后续等离子体清洁工艺的损伤。W2/W1和W3/W1适当的范围可改进构件的良率。
虽然本发明已揭示较佳实施例如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可做些许的改变与润饰。另外，本发明不特别限定于特定说明书中描述的实施例的工艺、装置、制造方法、组成和步骤。本领域普通技术人员可根据本发明说明书的揭示，进一步发展出与本发明大体上具有相同功能或大体上可达成相同结果的工艺、装置、制造方法、组成和步骤。因此本发明的保护范围应当视随附的权利要求所界定的范围为准。

Claims (10)

1.一种半导体裸片，包括：
一基底；
一接合垫，位于该基底上方，该接合垫具有一第一宽度；
一聚酰亚胺层，位于该基底和该接合垫上方，该聚酰亚胺层于该接合垫上方具有一第一开口，该第一开口有一第二宽度；
一硅基保护层，位于该聚酰亚胺层上，该硅基保护层于该接合垫上方具有一第二开口，该第二开口有一第三宽度，其中该第一开口和该第二开口形成一具有侧壁的组合开口，暴露部分该接合垫；
一凸块下金属化层，位于该组合开口的侧壁上方，且接触该接合垫的暴露部分；及
一导电元件，位于该凸块下金属化层上。
2.如权利要求1所述的半导体裸片，其中该第二宽度和该第一宽度的比例大体上为0.15～0.6。
3.如权利要求1所述的半导体裸片，其中该第三宽度和该第一宽度的比例大体上为0.15～0.6。
4.如权利要求1所述的半导体裸片，其中该导电元件包括焊锡凸块和铜柱。
5.如权利要求1所述的半导体裸片，其中该硅基保护层包括氮化硅、氮氧化硅、氧化硅或碳化硅。
6.一种半导体裸片，包括：
一基底；
一低介电常数介电层，位于该基底上方；
一接合垫，位于该低介电常数介电层上方，该接合垫具有第一宽度；
一聚酰亚胺层，位于该基底和该接合垫上方，该聚酰亚胺层包括具有第二宽度的第一开口；
一氮化硅层，直接位于该聚酰亚胺层上方，该氮化硅层包括一具有第三宽度的第二开口，其中该第一开口和该第二开口形成一具有侧壁的组合开口，暴露部分该接合垫，且该第二宽度小于该第三宽度；
一凸块下金属化层，衬垫该组合开口的侧壁，位于该氮化硅层的顶部部分上，且接触该接合垫的暴露部分；及
一导电元件，位于该凸块下金属化层上。
7.如权利要求6所述的半导体裸片，其中该第二宽度和该第一宽度的比例大体上为0.15～0.6，该第三宽度和该第一宽度的比例大体上为0.15～0.6。
8.一种形成导电元件的方法，包括：
形成一接合垫于一基底上方，该接合垫具有一第一宽度；
形成一聚酰亚胺层于该基底和该接合垫上方，该聚酰亚胺层于该接合垫上方具有一第一开口，该第一开口有一第二宽度；
形成一硅基保护层于该聚酰亚胺层上，该硅基保护层于该接合垫上方具有一第二开口，该第二开口有一第三宽度，其中该第一开口和该第二开口形成一具有侧壁的组合开口，暴露部分该接合垫；
形成一凸块下金属化层于该组合开口的侧壁上方，且接触该接合垫的暴露部分；及
形成一导电元件于该凸块下金属化层上。
9.如权利要求8所述的形成导电元件的方法，其中该硅基保护层包括氮化硅、氮氧化硅、氧化硅或碳化硅。
10.如权利要求8所述的形成导电元件的方法，其中该第二宽度和该第一宽度的比例大体上为0.15～0.6，该第三宽度和该第一宽度的比例大体上为0.15～0.6。
CN201010534192.6A 2010-04-16 2010-11-02 半导体裸片及形成导电元件的方法 Active CN102222647B (zh)

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CN105190879A (zh) * 2013-03-13 2015-12-23 德克萨斯仪器股份有限公司 铜柱附连基板
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CN103354224A (zh) * 2013-05-29 2013-10-16 南通富士通微电子股份有限公司 半导体器件扇出倒装芯片封装结构
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