US20080308932A1 - Semiconductor package structures - Google Patents

Semiconductor package structures Download PDF

Info

Publication number
US20080308932A1
US20080308932A1 US11/761,722 US76172207A US2008308932A1 US 20080308932 A1 US20080308932 A1 US 20080308932A1 US 76172207 A US76172207 A US 76172207A US 2008308932 A1 US2008308932 A1 US 2008308932A1
Authority
US
United States
Prior art keywords
encapsulation material
substrate
semiconductor structure
solder structures
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/761,722
Inventor
Mirng-Ji Lii
Hsin-Hui Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US11/761,722 priority Critical patent/US20080308932A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LII, MIRNG-JI, LEE, HSIN-HUI
Publication of US20080308932A1 publication Critical patent/US20080308932A1/en
Priority to US12/614,727 priority patent/US8524595B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H01L2224/81211—Applying energy for connecting using a reflow oven with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8192—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to semiconductor structures, and more particularly to semiconductor package structures and method for forming the package structures
  • CPUs central processing units
  • LCDs liquid crystal displays
  • LEDs light emitting diodes
  • laser diodes other devices or chip sets.
  • CPUs central processing units
  • LCDs liquid crystal displays
  • LEDs light emitting diodes
  • semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements.
  • package techniques incorporating with small-dimension integrated circuits would provide desired chip packages.
  • FIG. 1 is a cross-sectional view of a traditional package structure.
  • the package structure 101 includes solder balls 120 bonded on substrate 110 .
  • the substrate 110 with the solder balls 120 is then flipped and mounted on substrate 100 .
  • an under-filler material 130 is filled between the substrates 100 and 110 , protecting the solder balls 120 from particle contamination and electrically isolating the adjacent solder balls 120 .
  • the underfill also provides mechanical support and helps prevent failure of the solder joints.
  • a semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate.
  • a first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures.
  • the first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.
  • FIG. 1 is a cross-sectional view of a traditional package structure.
  • FIGS. 2A-2E are schematic drawings showing an exemplary method for forming a package structure.
  • FIGS. 2F-2H are schematic cross-sectional views of exemplary package structures.
  • FIG. 3 is a schematic graph showing at least one thermal process for treating exemplary package structures.
  • FIGS. 2A-2E are schematic drawings showing an exemplary method for forming a package structure.
  • At least one dielectric layer such as dielectric layer 203 is formed over a substrate 200 such as semiconductor wafer with diameter 8 inch, 12 inch or greater than 12 inch.
  • At least one metal trace layer such as metal trace layers 207 are formed over the dielectric layer 203 .
  • At least one pad such as pads 209 are formed over the metal trace layers 207 .
  • At least one isolation layer such as isolation layer 211 is formed over the dielectric layer 203 .
  • At least one passivation layer such as passivation layer 205 is formed over the metal trace layers 207 .
  • the passivation layer 205 may have a surface substantially level with at least one of the surfaces of the pads 209 .
  • At least one solder structure such as solder structures 213 are formed over the pads.
  • the substrate 200 can be a silicon substrate, a Ill-V compound substrate, a silicon/germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example.
  • a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example.
  • at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof are formed below the dielectric layer 203 and electrically coupled to each other.
  • the dielectric layer 203 may be a dielectric layer of an interconnect structure.
  • the dielectric layer 203 may be referred to as an inter-metal dielectric (IMD) layer.
  • the material of the dielectric layer 203 may comprise oxide, nitride, oxynitride, low-k dielectric material, ultra low-k dielectric material or other dielectric material or various combinations thereof.
  • the dielectric layer 203 may be formed by, for example, a chemical vapor deposition (CVD) step, a spin-on glass (SOG) step, or other method that is adequate to form a dielectric layer or various combinations thereof.
  • at least one metallic layer (not shown) is formed within and/or under the dielectric layer 203 .
  • the metallic layer may be provided for electrical connection between the metal trace layer 207 and at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) formed below the dielectric layer 203 and electrically coupled thereto.
  • the metal trace layers 207 may be provided for electrical connection between the pads 209 and the metallic layer (not shown) formed within and/or under the dielectric layer 203 .
  • the material of the metal trace layers 207 may comprise at least one of copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof.
  • the metal trace layers 207 may be formed by, for example, a chemical vapor deposition (CVD) step, a physical vapor deposition (PVD) step, an electroplating step, an electroless-plating step or other step that is adequate to for a thin film layer or various combinations thereof.
  • the pads 209 are provided for electrical connection with the metal trace layers 207 and the solder structures 213 .
  • the material of the pads 209 may comprise at least one material such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof.
  • the pads 209 may be formed by, for example, a chemical vapor deposition (CVD) step, a physical vapor deposition (PVD) step, an electroplating step, an electroless-plating step or other step that is adequate to for a thin film layer or various combinations thereof.
  • at least one of the pads 209 may include an under bump metallization (UBM) layer formed under the solder structure 213 .
  • UBM under bump metallization
  • the isolation layer 211 may be provided to desirably isolate two adjacent metal trace layers 207 .
  • the isolation layer 211 may be a stress buffer for releasing stresses of the package structure.
  • the material of the isolation layer 211 may comprise, for example, polymide, oxide, nitride, oxynitride, or other material that is adequate to provide desired electrical isolation and/or stress release or various combinations thereof.
  • the passivation layer 205 is provided to protect the pads 209 , the metal trace layers 207 , the dielectric layer 203 and/or any diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) formed below the dielectric layer 203 .
  • the material of the passivation layer 205 may comprise at least one of oxide, nitride, oxynitride, polyimide, or other material that is adequate to provide desired protection or various combinations thereof.
  • the passivation layer 205 may be formed by, for example, a chemical vapor deposition (CVD) step, a spin-on glass (SOG) step, or other method that is adequate to form a film layer or various combinations thereof.
  • the passivation layer 205 may have a thickness “t” between about 0.5 ⁇ m and about 100 ⁇ m. Other dimension of the thickness “t” of the passivation layer 205 may be used in other embodiments. The scope of the invention is not limited thereto.
  • the solder structures 213 are formed over the pads 209 .
  • the solder structures 213 may comprise, for example, solder balls and/or solder bumps.
  • the solder structures 213 may comprise at least one material such as eutectic tin-lead (Sn—Pb) solder, high lead solder, lead free solder, metal pillar such as copper pillar or other solder material or various combinations thereof.
  • the solder structures 213 may have a height between about 0.1 millimeter (mm) and about 0.6 mm. Other dimension of the height of the solder structures 213 may be used in other embodiments. The scope of the invention is not limited thereto.
  • an encapsulation material 220 is formed over the passivation layer 205 , partially covering the solder structures 213 .
  • the encapsulation material 220 may comprise resin-containing epoxy or polymer-based material like a mixture of resin powder and flux.
  • the flux may include de-oxidation material.
  • the encapsulation material 220 may be formed by, for example, a spin-coating step.
  • the encapsulation material 220 may have a thickness between about 1 ⁇ 3 of the height of the solder structure 213 and about 9/10 of the height of the solder structures. In other embodiments, the encapsulation material 220 may have a thickness larger than about 10 um, preferred between about 10 ⁇ m and about 30 ⁇ m. In still other embodiments, the encapsulation material 220 may be formed to a desired height, such that the encapsulation material 220 can wrap around a major portion of the solder structures as shown in FIG. 2D or 2 E.
  • the structure shown in FIG. 2B may be subjected to a sawing process so as to create a plurality of individual dies 200 a as shown in FIG. 2C .
  • the sawing process may include a laser sawing step, a water sawing step, a blade sawing step, other method that is adequate to cut the substrate 200 or various combinations thereof.
  • the substrate 230 may be a printed circuit board (PCB), a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example.
  • PCB printed circuit board
  • SiGe silicon/germanium
  • SOI silicon-on-insulator
  • a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example.
  • coefficient of thermal expansion (CTE) of the encapsulation material 220 is between the CTE of substrate 300 and substrate 230 .
  • the substrate 230 may comprise at least one pad (not shown) for electrical connection with the solder structures 213 .
  • at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof are formed below the pad (not shown) and electrically coupled to each other.
  • a thermal process 233 may be applied to the encapsulation material 220 , such that the encapsulation material 220 melts and flows along at least one sidewall such as sidewalls 214 of the solder structures 213 a. Accordingly, the encapsulation material layers 220 a are formed on the sidewalls 214 of the solder structures 213 a.
  • the thermal process 233 may be conducted in a furnace, a rapid thermal processing (RTP) apparatus, oven or other thermal processing apparatus or combinations thereof.
  • RTP rapid thermal processing
  • the thermal process 233 may heat the encapsulation material 220 between about 100° C. and about 160° C. for a processing time “T 1 ” as shown in FIG. 3 .
  • the thermal process 233 may also soften and/or melt the solder structures 213 , such that the height of the solder structures 213 a may be slightly less than that of the solder structures 213 (shown in FIG. 2C ).
  • a gap 240 may be formed between the adjacent encapsulation material layers 220 a.
  • a part (not shown) of the encapsulation material 220 may remain on the surface 205 a of the passivation layer 205 .
  • a reflow process 243 may be applied to the encapsulation material 220 a and/or the solder structures 213 a, such that the reflowed solder structures 213 b may desirably contact the substrate 230 .
  • the reflow process 243 may be conducted within a furnace, a rapid thermal processing (RTP) apparatus, oven or other thermal processing apparatus or combinations thereof.
  • RTP rapid thermal processing
  • the reflow process 243 may desirably soften the solder structures 213 b such that the stacked structure shown in FIG. 2E may be reduced to a desired package height.
  • the reflow process 243 may soften and/or melt the solder structures 213 a , such that the height of the solder structures 213 b may be slightly less than that of the solder structures 213 a (shown in FIG. 2D ).
  • the reflow process 243 may heat the solder structures 213 a (shown in FIG. 2D ) between about 160° C. and about 240° C. for a processing time “T 2 ” as shown in FIG. 3 .
  • Other process temperatures and/or processing time of the reflow process 243 may be used in other exemplary embodiments. The scope of the present invention is not limited thereto.
  • the reflow process 243 may heat the encapsulation material layers 220 a (shown in FIG. 2D ), such that the encapsulation material layers 220 a may flow along the sidewalls 214 of the solder structures 213 a so as to form the encapsulation material layers 220 b and the solder structures 213 b. Accordingly, the gap 240 may be formed between the adjacent encapsulation material layers 220 b. In some embodiments, a part (not shown) of the encapsulation material 220 (shown in FIG. 2A ) may remain on the surface 205 a of the passivation layer 205 . The encapsulation material layers 220 b may be substantially conformal on the sidewalls 214 of the solder structures 213 b.
  • the reflow process 243 described in conjunction with FIG. 2E may be used to form the desired encapsulation material layers 220 b and the solder structures 213 b as shown in FIG. 2E .
  • the thermal process 233 described in conjunction with FIG. 2D may be omitted.
  • the reflow process 243 may have a process temperature between about 100° C. and about 240° C. Other process temperatures and/or processing time of the reflow process 243 may be used in other exemplary embodiments. The scope of the present invention is not limited thereto.
  • the under-filler 130 is filled between the substrates 100 and 110 after the substrate 100 with the solder bumps 120 is bonded on the substrate 100 .
  • the encapsulation material 220 (shown in FIG. 2B ) may be formed before the bonding process and thus may be formed in a semiconductor manufacturing facility, rather than in a package/testing factory.
  • the process for forming the under-filler 130 described in conjunction with FIG. 1 can be omitted. Accordingly, tools and modules for forming the under-filler 130 can be omitted.
  • the under-filler 130 tends to trap moisture generated from the filling process itself and/or absorb moisture from environment. It is found that moisture may contribute to IMD delamination occurring at the die edge of the substrate 110 if the under-filler 130 is not well developed. As the processes described in conjunction with FIGS. 2A-2E do not apply the under-filler 130 between the substrate 230 and passivation layer 205 , no development of an under-filler material is used. Accordingly, the processes described in conjunction with FIGS. 2A-2E are not subject to the concern of the traditional structure shown in FIG. 1 .
  • At least one gap such as gap 240 is formed between the adjacent solder structures 213 b.
  • moisture within the encapsulation material layers 220 b may be desirably expelled from the region between the die 200 a and the substrate 230 .
  • the gap 240 may be circumferential around at least one of the encapsulation material layers 220 b between the die 200 a and the substrate 230 .
  • the underfilling process used in the traditional process can be optionally omitted.
  • FIGS. 2F-2H are schematic cross-sectional views of exemplary package structures.
  • the encapsulation material layers 220 b may lie on the sidewalls 214 of the solder structures 213 b near to the surface of the passivation layer 205 and the surface of the substrate 230 without substantially lying on the middle region of the solder structures 213 b.
  • the encapsulation material layers 220 b may lie on the sidewalls 214 of the solder structures 213 b such that the dimension “a” of the material layers 220 b lying in the region adjacent to the surfaces of the substrate 230 and/or the passication layer 205 is larger than the dimension “b” of the material layers 220 b lying in the middle region of the solder structures 213 b , forming an hourglass shape.
  • the encapsulation material layers 220 b may lie on the sidewalls 214 of the solder structures 213 b such that the dimension “c” of the material layers 220 b lying in the region adjacent to the surface of the substrate 230 is larger than the dimension “d” of the material layers 220 b lying in the region adjacent to the surface of the passivation layer 205 .

Abstract

A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to semiconductor structures, and more particularly to semiconductor package structures and method for forming the package structures
  • 2. Description of the Related Art
  • With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements. Further, package techniques incorporating with small-dimension integrated circuits would provide desired chip packages.
  • FIG. 1 is a cross-sectional view of a traditional package structure. The package structure 101 includes solder balls 120 bonded on substrate 110. The substrate 110 with the solder balls 120 is then flipped and mounted on substrate 100. After the mounting step, an under-filler material 130 is filled between the substrates 100 and 110, protecting the solder balls 120 from particle contamination and electrically isolating the adjacent solder balls 120. The underfill also provides mechanical support and helps prevent failure of the solder joints.
    • SUMMARY OF THE INVENTION
  • In accordance with some exemplary embodiments, a semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.
  • The above and other features will be better understood from the following detailed description of the exemplary embodiments of the invention that is provided in connection with the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Following are brief descriptions of exemplary drawings. They are mere exemplary embodiments and the scope of the present invention should not be limited thereto.
  • FIG. 1 is a cross-sectional view of a traditional package structure.
  • FIGS. 2A-2E are schematic drawings showing an exemplary method for forming a package structure.
  • FIGS. 2F-2H are schematic cross-sectional views of exemplary package structures.
  • FIG. 3 is a schematic graph showing at least one thermal process for treating exemplary package structures.
    •  DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
  • This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus/device be constructed or operated in a particular orientation.
  • FIGS. 2A-2E are schematic drawings showing an exemplary method for forming a package structure.
  • Referring to FIG. 2A, at least one dielectric layer such as dielectric layer 203 is formed over a substrate 200 such as semiconductor wafer with diameter 8 inch, 12 inch or greater than 12 inch. At least one metal trace layer such as metal trace layers 207 are formed over the dielectric layer 203. At least one pad such as pads 209 are formed over the metal trace layers 207. At least one isolation layer such as isolation layer 211 is formed over the dielectric layer 203. At least one passivation layer such as passivation layer 205 is formed over the metal trace layers 207. In some embodiments, the passivation layer 205 may have a surface substantially level with at least one of the surfaces of the pads 209. At least one solder structure such as solder structures 213 are formed over the pads.
  • The substrate 200 can be a silicon substrate, a Ill-V compound substrate, a silicon/germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. In some embodiments, at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) are formed below the dielectric layer 203 and electrically coupled to each other.
  • In some embodiments, the dielectric layer 203 may be a dielectric layer of an interconnect structure. The dielectric layer 203 may be referred to as an inter-metal dielectric (IMD) layer. The material of the dielectric layer 203 may comprise oxide, nitride, oxynitride, low-k dielectric material, ultra low-k dielectric material or other dielectric material or various combinations thereof. The dielectric layer 203 may be formed by, for example, a chemical vapor deposition (CVD) step, a spin-on glass (SOG) step, or other method that is adequate to form a dielectric layer or various combinations thereof. In some embodiments, at least one metallic layer (not shown) is formed within and/or under the dielectric layer 203. The metallic layer may be provided for electrical connection between the metal trace layer 207 and at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) formed below the dielectric layer 203 and electrically coupled thereto.
  • The metal trace layers 207 may be provided for electrical connection between the pads 209 and the metallic layer (not shown) formed within and/or under the dielectric layer 203. The material of the metal trace layers 207 may comprise at least one of copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. The metal trace layers 207 may be formed by, for example, a chemical vapor deposition (CVD) step, a physical vapor deposition (PVD) step, an electroplating step, an electroless-plating step or other step that is adequate to for a thin film layer or various combinations thereof.
  • The pads 209 are provided for electrical connection with the metal trace layers 207 and the solder structures 213. The material of the pads 209 may comprise at least one material such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. The pads 209 may be formed by, for example, a chemical vapor deposition (CVD) step, a physical vapor deposition (PVD) step, an electroplating step, an electroless-plating step or other step that is adequate to for a thin film layer or various combinations thereof. In some embodiments, at least one of the pads 209 may include an under bump metallization (UBM) layer formed under the solder structure 213.
  • The isolation layer 211 may be provided to desirably isolate two adjacent metal trace layers 207. In some embodiments, the isolation layer 211 may be a stress buffer for releasing stresses of the package structure. The material of the isolation layer 211 may comprise, for example, polymide, oxide, nitride, oxynitride, or other material that is adequate to provide desired electrical isolation and/or stress release or various combinations thereof.
  • The passivation layer 205 is provided to protect the pads 209, the metal trace layers 207, the dielectric layer 203 and/or any diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) formed below the dielectric layer 203. The material of the passivation layer 205 may comprise at least one of oxide, nitride, oxynitride, polyimide, or other material that is adequate to provide desired protection or various combinations thereof. The passivation layer 205 may be formed by, for example, a chemical vapor deposition (CVD) step, a spin-on glass (SOG) step, or other method that is adequate to form a film layer or various combinations thereof. In some embodiments, the passivation layer 205 may have a thickness “t” between about 0.5 μm and about 100 μm. Other dimension of the thickness “t” of the passivation layer 205 may be used in other embodiments. The scope of the invention is not limited thereto.
  • The solder structures 213 are formed over the pads 209. The solder structures 213 may comprise, for example, solder balls and/or solder bumps. In some embodiments, the solder structures 213 may comprise at least one material such as eutectic tin-lead (Sn—Pb) solder, high lead solder, lead free solder, metal pillar such as copper pillar or other solder material or various combinations thereof. In some embodiments, the solder structures 213 may have a height between about 0.1 millimeter (mm) and about 0.6 mm. Other dimension of the height of the solder structures 213 may be used in other embodiments. The scope of the invention is not limited thereto.
  • Referring to FIG. 2B, an encapsulation material 220 is formed over the passivation layer 205, partially covering the solder structures 213. The encapsulation material 220 may comprise resin-containing epoxy or polymer-based material like a mixture of resin powder and flux. In some embodiments, the flux may include de-oxidation material. The encapsulation material 220 may be formed by, for example, a spin-coating step.
  • In some embodiments, the encapsulation material 220 may have a thickness between about ⅓ of the height of the solder structure 213 and about 9/10 of the height of the solder structures. In other embodiments, the encapsulation material 220 may have a thickness larger than about 10 um, preferred between about 10 μm and about 30 μm. In still other embodiments, the encapsulation material 220 may be formed to a desired height, such that the encapsulation material 220 can wrap around a major portion of the solder structures as shown in FIG. 2D or 2E.
  • After forming the solder structures 213, the structure shown in FIG. 2B may be subjected to a sawing process so as to create a plurality of individual dies 200 a as shown in FIG. 2C. The sawing process may include a laser sawing step, a water sawing step, a blade sawing step, other method that is adequate to cut the substrate 200 or various combinations thereof.
  • Referring to FIG. 2C, the structure shown in FIG. 2B may be flipped, such that the solder structures 213 contact a substrate 230. The substrate 230 may be a printed circuit board (PCB), a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. In some embodiments for providing desired mechanical support, coefficient of thermal expansion (CTE) of the encapsulation material 220 is between the CTE of substrate 300 and substrate 230.
  • In some embodiments, the substrate 230 may comprise at least one pad (not shown) for electrical connection with the solder structures 213. In other embodiments, at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) are formed below the pad (not shown) and electrically coupled to each other.
  • Referring to FIG. 2D, a thermal process 233 may be applied to the encapsulation material 220, such that the encapsulation material 220 melts and flows along at least one sidewall such as sidewalls 214 of the solder structures 213 a. Accordingly, the encapsulation material layers 220 a are formed on the sidewalls 214 of the solder structures 213 a. In some embodiments, the thermal process 233 may be conducted in a furnace, a rapid thermal processing (RTP) apparatus, oven or other thermal processing apparatus or combinations thereof.
  • In some embodiments, the thermal process 233 may heat the encapsulation material 220 between about 100° C. and about 160° C. for a processing time “T1” as shown in FIG. 3. In some embodiments, the thermal process 233 may also soften and/or melt the solder structures 213, such that the height of the solder structures 213 a may be slightly less than that of the solder structures 213 (shown in FIG. 2C).
  • Referring again to FIG. 2D, as the encapsulation material layers 220 a flows along the sidewalls 214 of the solder structures 213 a, a gap 240 may be formed between the adjacent encapsulation material layers 220 a. In some embodiments, a part (not shown) of the encapsulation material 220 may remain on the surface 205 a of the passivation layer 205.
  • Referring to FIG. 2E, another thermal process such as a reflow process 243 may be applied to the encapsulation material 220 a and/or the solder structures 213 a, such that the reflowed solder structures 213 b may desirably contact the substrate 230. In some embodiments, the reflow process 243 may be conducted within a furnace, a rapid thermal processing (RTP) apparatus, oven or other thermal processing apparatus or combinations thereof.
  • In some embodiments, the reflow process 243 may desirably soften the solder structures 213 b such that the stacked structure shown in FIG. 2E may be reduced to a desired package height. The reflow process 243 may soften and/or melt the solder structures 213 a, such that the height of the solder structures 213 b may be slightly less than that of the solder structures 213 a (shown in FIG. 2D).
  • In some embodiments, the reflow process 243 may heat the solder structures 213 a (shown in FIG. 2D) between about 160° C. and about 240° C. for a processing time “T2” as shown in FIG. 3. Other process temperatures and/or processing time of the reflow process 243 may be used in other exemplary embodiments. The scope of the present invention is not limited thereto.
  • In other embodiments, the reflow process 243 may heat the encapsulation material layers 220 a (shown in FIG. 2D), such that the encapsulation material layers 220 a may flow along the sidewalls 214 of the solder structures 213 a so as to form the encapsulation material layers 220 b and the solder structures 213 b. Accordingly, the gap 240 may be formed between the adjacent encapsulation material layers 220 b. In some embodiments, a part (not shown) of the encapsulation material 220 (shown in FIG. 2A) may remain on the surface 205 a of the passivation layer 205. The encapsulation material layers 220 b may be substantially conformal on the sidewalls 214 of the solder structures 213 b.
  • In some embodiments, the reflow process 243 described in conjunction with FIG. 2E may be used to form the desired encapsulation material layers 220 b and the solder structures 213 b as shown in FIG. 2E. In the embodiments, the thermal process 233 described in conjunction with FIG. 2D may be omitted. In some embodiments, the reflow process 243 may have a process temperature between about 100° C. and about 240° C. Other process temperatures and/or processing time of the reflow process 243 may be used in other exemplary embodiments. The scope of the present invention is not limited thereto.
  • Referring again to FIG. 1, the under-filler 130 is filled between the substrates 100 and 110 after the substrate 100 with the solder bumps 120 is bonded on the substrate 100. Unlike the under-filler 130, the encapsulation material 220 (shown in FIG. 2B) may be formed before the bonding process and thus may be formed in a semiconductor manufacturing facility, rather than in a package/testing factory. By reflowing the encapsulation material 220 so as to form the encapsulation material layers 220 b, the process for forming the under-filler 130 described in conjunction with FIG. 1 can be omitted. Accordingly, tools and modules for forming the under-filler 130 can be omitted.
  • It is found that the under-filler 130 tends to trap moisture generated from the filling process itself and/or absorb moisture from environment. It is found that moisture may contribute to IMD delamination occurring at the die edge of the substrate 110 if the under-filler 130 is not well developed. As the processes described in conjunction with FIGS. 2A-2E do not apply the under-filler 130 between the substrate 230 and passivation layer 205, no development of an under-filler material is used. Accordingly, the processes described in conjunction with FIGS. 2A-2E are not subject to the concern of the traditional structure shown in FIG. 1.
  • Further, at least one gap such as gap 240 is formed between the adjacent solder structures 213b. With the thermal process 233 and/or the reflow process 243, moisture within the encapsulation material layers 220 b may be desirably expelled from the region between the die 200 a and the substrate 230. In some embodiments, the gap 240 may be circumferential around at least one of the encapsulation material layers 220 b between the die 200 a and the substrate 230.
  • Referring again to FIG. 1, after forming the bumps 120 on a wafer which is sawed to provide a plurality of dies 110. The die 110 is then flipped and bonded on the substrate 100. Then the underfill 130 is filled between the die 110 and the substrate 100. Unlike the traditional process, the encapsulation material layer 220 is formed at the wafer level of the substrate 200 as shown in FIG. 2B. The substrate 200 is then subject to a dicing process resulting to a plurality of dies 200 a with the encapsulation material layer 220 formed thereover. The die 200 a is then flipped and then subject to at least one of the thermal process 233 and the reflow process 243 as shown in FIGS. 2D and 2E, respectively, so as to flow the encapsulation material layer 220 substantially around the solder structures 213 b. Therefore, the underfilling process used in the traditional process can be optionally omitted.
  • FIGS. 2F-2H are schematic cross-sectional views of exemplary package structures.
  • Referring to FIG. 2F, the encapsulation material layers 220 b may lie on the sidewalls 214 of the solder structures 213 b near to the surface of the passivation layer 205 and the surface of the substrate 230 without substantially lying on the middle region of the solder structures 213 b.
  • Referring to FIG. 2G, the encapsulation material layers 220 b may lie on the sidewalls 214 of the solder structures 213 b such that the dimension “a” of the material layers 220 b lying in the region adjacent to the surfaces of the substrate 230 and/or the passication layer 205 is larger than the dimension “b” of the material layers 220 b lying in the middle region of the solder structures 213 b, forming an hourglass shape.
  • Referring to FIG. 2H, the encapsulation material layers 220 b may lie on the sidewalls 214 of the solder structures 213 b such that the dimension “c” of the material layers 220 b lying in the region adjacent to the surface of the substrate 230 is larger than the dimension “d” of the material layers 220 b lying in the region adjacent to the surface of the passivation layer 205.
  • Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention which may be made by those skilled in the field of this art without departing from the scope and range of equivalents of the invention.

Claims (18)

1. A semiconductor structure, comprising:
a plurality of solder structures between a first substrate and a second substrate; and
a first encapsulation material substantially around a first one of the solder structures and a second encapsulation material substantially around a second one of the solder structures, wherein the first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.
2. The semiconductor structure of claim 1, wherein the first encapsulation material is separated from the second encapsulation material.
3. The semiconductor structure of claim 1, wherein the gap is around the first encapsulation material between the first and second substrates.
4. The semiconductor structure of claim 1, wherein at least one of the first encapsulation material and the second encapsulation material has a first thickness adjacent to the first substrate larger than a second thickness adjacent to the second substrate.
5. The semiconductor structure of claim 1, wherein the first encapsulation material has a first thickness adjacent to the first substrate is larger than a second thickness adjacent to a middle region of the first one of the solder structures.
6. The semiconductor structure of claim 1, wherein the first encapsulation material is substantially conformal over at least one sidewall of the first one of the solder structures.
7. The semiconductor structure of claim 1, wherein at least one of the first encapsulation material and the second encapsulation material comprises a mixture of resin powder and flux.
8. The semiconductor structure of claim 7, wherein the flux comprises de-oxidation material.
9. The semiconductor structure of claim 1, wherein at least one of the first encapsulation material and the second encapsulation material has a coefficient of thermal expansion (CTE) from about a CTE of the first substrate to about a CTE of the second substrate.
10. The semiconductor structure of claim 1, wherein at least one of the first encapsulation material and the second encapsulation material has a melting temperature between about 100° C and about 240° C.
11. A semiconductor structure comprising:
a plurality of solder structures between a first substrate and a second substrate; and
a first resin encapsulation material substantially around a first one of the solder structures and a second resin encapsulation material substantially around a second one of the solder structures, wherein the first one and the second one of the solder structures are near to each other, a gap is between the first resin encapsulation material and the second resin encapsulation material and at least one of the first resin encapsulation material and the second resin encapsulation material has a first thickness adjacent to the first substrate larger than a second thickness adjacent to the second substrate.
12. The semiconductor structure of claim 11, wherein at least one of the first resin encapsulation material and the second resin encapsulation material further comprises flux.
13. The semiconductor structure of claim 12, wherein the flux comprises at least one of epoxy and polyimide.
14. The semiconductor structure of claim 11, wherein at least one of the first resin encapsulation material and the second resin encapsulation material has a coefficient of thermal expansion (CTE) from about a CTE of the first substrate to about a CTE of the second substrate.
15. The semiconductor structure of claim 11, wherein at least one of the first resin encapsulation material and the second resin encapsulation material has a melting temperature between about 100° C. and about 240° C.
16. A semiconductor structure comprising:
a plurality of solder structures formed over a passivation layer of a die; and
an encapsulation material layer formed over the passivation layer and the solder structures, at least partially exposing the solder structures, wherein the encapsulation material has a thickness between about one third of a height of the solder structures and about nine tenths of the height of the solder structures.
17. The semiconductor structure of claim 16, wherein the encapsulation material comprises a mixture of resin powder and flux.
18. The semiconductor structure of claim 17, wherein the flux comprises de-oxidation material.
US11/761,722 2007-06-12 2007-06-12 Semiconductor package structures Abandoned US20080308932A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/761,722 US20080308932A1 (en) 2007-06-12 2007-06-12 Semiconductor package structures
US12/614,727 US8524595B2 (en) 2007-06-12 2009-11-09 Semiconductor package structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/761,722 US20080308932A1 (en) 2007-06-12 2007-06-12 Semiconductor package structures

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/614,727 Continuation US8524595B2 (en) 2007-06-12 2009-11-09 Semiconductor package structures

Publications (1)

Publication Number Publication Date
US20080308932A1 true US20080308932A1 (en) 2008-12-18

Family

ID=40131527

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/761,722 Abandoned US20080308932A1 (en) 2007-06-12 2007-06-12 Semiconductor package structures
US12/614,727 Active 2028-10-03 US8524595B2 (en) 2007-06-12 2009-11-09 Semiconductor package structures

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/614,727 Active 2028-10-03 US8524595B2 (en) 2007-06-12 2009-11-09 Semiconductor package structures

Country Status (1)

Country Link
US (2) US20080308932A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100055846A1 (en) * 2007-06-12 2010-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
US20110254159A1 (en) * 2010-04-16 2011-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive feature for semiconductor substrate and method of manufacture
CN103201833A (en) * 2010-11-05 2013-07-10 英特尔公司 Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US20150171037A1 (en) * 2011-09-28 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of Connectors without UBM
US10756153B2 (en) * 2017-07-31 2020-08-25 Lg Display Co., Ltd. Organic light emitting display device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008054415A1 (en) * 2008-12-09 2010-06-10 Robert Bosch Gmbh Arrangement of two substrates with a SLID bond connection and method for producing such an arrangement
TWI445147B (en) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng Semiconductor device
US9048135B2 (en) 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
TWI478303B (en) * 2010-09-27 2015-03-21 Advanced Semiconductor Eng Chip having metal pillar and package having the same
US9411750B2 (en) 2012-07-30 2016-08-09 International Business Machines Corporation Efficient calibration of a low power parallel data communications channel
US8889486B2 (en) * 2012-09-05 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package structures
US9536850B2 (en) * 2013-03-08 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
US9331043B1 (en) * 2015-01-30 2016-05-03 Invensas Corporation Localized sealing of interconnect structures in small gaps
US9474034B1 (en) 2015-11-30 2016-10-18 International Business Machines Corporation Power reduction in a parallel data communications interface using clock resynchronization
US10643863B2 (en) * 2017-08-24 2020-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US11121089B2 (en) * 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297560B1 (en) * 1996-10-31 2001-10-02 Miguel Albert Capote Semiconductor flip-chip assembly with pre-applied encapsulating layers
US6578755B1 (en) * 2000-09-22 2003-06-17 Flip Chip Technologies, L.L.C. Polymer collar for solder bumps
US6605525B2 (en) * 2001-05-01 2003-08-12 Industrial Technologies Research Institute Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed
US6940177B2 (en) * 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
US20060113632A1 (en) * 2001-09-07 2006-06-01 Keiichi Kimura Semiconductor device and voltage regulator
US7091062B2 (en) * 2003-10-15 2006-08-15 Infineon Technologies Ag Wafer level packages for chips with sawn edge protection

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060844A (en) * 1990-07-18 1991-10-29 International Business Machines Corporation Interconnection structure and test method
US7041771B1 (en) * 1995-08-11 2006-05-09 Kac Holdings, Inc. Encapsulant with fluxing properties and method of use in flip-chip surface mount reflow soldering
US5704116A (en) * 1996-05-03 1998-01-06 Motorola, Inc. Method of holding a component using an anhydride fluxing agent
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
JP3070514B2 (en) * 1997-04-28 2000-07-31 日本電気株式会社 Semiconductor device having protruding electrode, method of mounting semiconductor device, and mounting structure thereof
US5985456A (en) * 1997-07-21 1999-11-16 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6017634A (en) * 1997-07-21 2000-01-25 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing agent and carboxyl-reactive neutralizing agent as adhesive
US6265776B1 (en) * 1998-04-27 2001-07-24 Fry's Metals, Inc. Flip chip with integrated flux and underfill
JP4239310B2 (en) * 1998-09-01 2009-03-18 ソニー株式会社 Manufacturing method of semiconductor device
US6168972B1 (en) * 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
JP3019851B1 (en) * 1998-12-22 2000-03-13 日本電気株式会社 Semiconductor device mounting structure
US6352881B1 (en) * 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
US6756253B1 (en) * 1999-08-27 2004-06-29 Micron Technology, Inc. Method for fabricating a semiconductor component with external contact polymer support layer
JP2001339012A (en) * 2000-05-30 2001-12-07 Nec Kyushu Ltd Semiconductor device and its manufacturing method
US6680436B2 (en) * 2000-07-12 2004-01-20 Seagate Technology Llc Reflow encapsulant
JP2004523893A (en) * 2000-11-14 2004-08-05 ヘンケル　ロックタイト　コーポレイション Flux and underfill material for wafer coating, and laminated electronic assembly manufactured using the same
US7331502B2 (en) * 2001-03-19 2008-02-19 Sumitomo Bakelite Company, Ltd. Method of manufacturing electronic part and electronic part obtained by the method
US6808959B2 (en) * 2001-05-24 2004-10-26 Nec Electronics Corporation Semiconductor device having reinforced coupling between solder balls and substrate
US6551863B2 (en) * 2001-08-30 2003-04-22 Micron Technology, Inc. Flip chip dip coating encapsulant
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
JP2004103928A (en) * 2002-09-11 2004-04-02 Fujitsu Ltd Substrate, forming method of solder ball, and mounting structure thereof
TWI231555B (en) * 2003-06-30 2005-04-21 Advanced Semiconductor Eng Wafer level package and fabrication process thereof
TW592013B (en) * 2003-09-09 2004-06-11 Advanced Semiconductor Eng Solder bump structure and the method for forming the same
US20050082670A1 (en) * 2003-09-11 2005-04-21 Nordson Corporation Method for preapplying a viscous material to strengthen solder connections in microelectronic packaging and microelectronic packages formed thereby
US7118833B2 (en) * 2003-09-26 2006-10-10 Flipchip International, Llc Forming partial-depth features in polymer film
US7126164B2 (en) * 2003-09-26 2006-10-24 Flipchip International Llc Wafer-level moat structures
KR100630698B1 (en) * 2004-08-17 2006-10-02 삼성전자주식회사 Semiconductor package improving a solder joint reliability and method for manufacturing the same
US7417305B2 (en) * 2004-08-26 2008-08-26 Micron Technology, Inc. Electronic devices at the wafer level having front side and edge protection material and systems including the devices
US7329951B2 (en) * 2005-04-27 2008-02-12 International Business Machines Corporation Solder bumps in flip-chip technologies
WO2006129630A1 (en) * 2005-05-31 2006-12-07 Sumitomo Bakelite Co., Ltd. Encapsulating resin composition for preapplication, semiconductor device made with the same, and process for producing the same
US7749806B2 (en) * 2005-09-22 2010-07-06 Chipmos Technologies Inc. Fabricating process of a chip package structure
JP4137112B2 (en) * 2005-10-20 2008-08-20 日本テキサス・インスツルメンツ株式会社 Manufacturing method of electronic parts
KR100748558B1 (en) * 2006-06-19 2007-08-10 삼성전자주식회사 Chip size package and method of fabricating the same
US20080308932A1 (en) * 2007-06-12 2008-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
CN101965632B (en) * 2008-10-27 2012-09-26 松下电器产业株式会社 Semiconductor mounting structure and method for manufacturing same
US8436255B2 (en) * 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297560B1 (en) * 1996-10-31 2001-10-02 Miguel Albert Capote Semiconductor flip-chip assembly with pre-applied encapsulating layers
US6578755B1 (en) * 2000-09-22 2003-06-17 Flip Chip Technologies, L.L.C. Polymer collar for solder bumps
US6605525B2 (en) * 2001-05-01 2003-08-12 Industrial Technologies Research Institute Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed
US20060113632A1 (en) * 2001-09-07 2006-06-01 Keiichi Kimura Semiconductor device and voltage regulator
US6940177B2 (en) * 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
US7091062B2 (en) * 2003-10-15 2006-08-15 Infineon Technologies Ag Wafer level packages for chips with sawn edge protection

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100055846A1 (en) * 2007-06-12 2010-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
US8524595B2 (en) 2007-06-12 2013-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
US20110254159A1 (en) * 2010-04-16 2011-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive feature for semiconductor substrate and method of manufacture
US8587119B2 (en) * 2010-04-16 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive feature for semiconductor substrate and method of manufacture
CN103201833A (en) * 2010-11-05 2013-07-10 英特尔公司 Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
EP2636063A4 (en) * 2010-11-05 2015-11-11 Intel Corp Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
CN106340497A (en) * 2010-11-05 2017-01-18 英特尔公司 Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
CN106340497B (en) * 2010-11-05 2020-08-04 英特尔公司 Encapsulated die, microelectronic package containing same, and method of making said microelectronic package
US20150171037A1 (en) * 2011-09-28 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of Connectors without UBM
US9673158B2 (en) * 2011-09-28 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of connectors without UBM
US10756153B2 (en) * 2017-07-31 2020-08-25 Lg Display Co., Ltd. Organic light emitting display device

Also Published As

Publication number Publication date
US8524595B2 (en) 2013-09-03
US20100055846A1 (en) 2010-03-04

Similar Documents

Publication Publication Date Title
US8524595B2 (en) Semiconductor package structures
US10950514B2 (en) Packaged semiconductor devices and methods of packaging semiconductor devices
US20180374820A1 (en) Manufacturing method of semiconductor device and semiconductor device thereof
US9269687B2 (en) Packaging methods and packaged semiconductor devices
US20220384377A1 (en) Semiconductor structure and method of manufacturing the same
US11810831B2 (en) Integrated circuit package and method of forming same
US8810025B2 (en) Reinforcement structure for flip-chip packaging
US10074631B2 (en) Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
TWI662667B (en) Package structure and manufacturing method thereof
US9230935B2 (en) Package on package structure and method of manufacturing the same
US20070246821A1 (en) Utra-thin substrate package technology
US9888527B2 (en) Systems for processing semiconductor devices, and methods of processing semiconductor devices
US20220302079A1 (en) Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices
US10002814B2 (en) Apparatuses and methods to enhance passivation and ILD reliability
US9147668B2 (en) Method for fabricating semiconductor structure
US11855006B2 (en) Memory device, package structure and fabricating method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LII, MIRNG-JI;LEE, HSIN-HUI;REEL/FRAME:019703/0635;SIGNING DATES FROM 20070806 TO 20070808

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION