CN106298710B - 基板结构及其制法暨导电结构 - Google Patents
基板结构及其制法暨导电结构 Download PDFInfo
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Abstract
一种基板结构及其制法暨导电结构,该基板结构包括:具有多个电性接触垫的基板本体、形成于该基板本体上的绝缘层、形成于该绝缘层中并电性连接该电性接触垫的导电通孔、形成于该绝缘层中并设于该导电通孔上的线路层、以及形成于该绝缘层上并设于该线路层上且覆盖该导电通孔的导电柱,使该导电通孔、线路层及导电柱为一体成形者,其中,该线路层的宽度大于该导电通孔的宽度,且该导电柱的宽度大于该线路层的宽度,以供超微小芯片或细间距的电性接触垫进行覆晶电性连接。
Description
技术领域
本发明有关一种基板结构,尤指一种具导电凸块的基板结构。
背景技术
传统覆晶式(flip chip)半导体封装技术主要通过于芯片的电性接触垫上形成焊料凸块(solder bump),再透过该焊料凸块直接与封装基板电性连接,相较于打线(wirebonding)方式而言,覆晶技术的电路路径较短,具有较佳的电性品质,同时因可设计为晶背裸露形式,也可提高芯片散热性。
如图1所示的覆晶技术的局部示意图,通过于芯片10的绝缘层11(由第一绝缘层11a与第二绝缘层11b所组成)上形成外露电性接触垫100的开孔,再于该绝缘层11上与该开孔中形成粘附层12、润湿层13与保护层14,并于该电性接触垫100上方形成焊料凸块16,最后蚀刻移除未被该焊料凸块16所覆盖的粘附层12、润湿层13与保护层14,以于该焊料凸块16底下定义出凸块底下金属层(Under Bump Metallurgy,简称UBM)15,使该焊料凸块16牢固接于该电性接触垫100上。
上述中,该粘附层12的材质为钛(Ti)、铬(Cr)或钛钨(TiW),以提供该电性接触垫100与该润湿层13间有较强的粘着性。该润湿层13的材质为镍(Ni)或铜(Cu),其与焊锡的润湿程度较高,故于回焊该焊料凸块16时,该焊料凸块16可完全附着且呈球状。该保护层14的材质为如金、铜等的低电阻金属,其可保护该焊料凸块16及降低电阻值。
惟,随着芯片10的微小化的发展,各该电性接触垫100之间的距离愈小,致使现有覆晶制程无法配合,导致相邻两焊料凸块16容易桥接,故需有更新更进步的封装技术以供更微小的芯片10的使用。
因此,如何克服上述现有技术的桥接问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失,本发明提供一种基板结构及其制法暨导电结构,以供超微小芯片或细间距的电性接触垫进行覆晶电性连接。
本发明的基板结构,包括:基板本体,其具有多个电性接触垫;绝缘层,其形成于该基板本体上,并令所述电性接触垫显露于该绝缘层;至少一导电通孔,其形成于该绝缘层中并电性连接该电性接触垫;线路层,其具有多个线路并形成于该绝缘层中及该导电通孔上,其中,该线路层的各线路的宽度大于该导电通孔的宽度;以及导电柱,其形成于该绝缘层上并设于该线路层上,其中,该导电柱的宽度大于或等于该线路层的宽度,且该导电通孔、线路层及导电柱为一体成形者。
本发明还提供一种基板结构的制法,其包括:提供具有多个电性接触垫的基板本体;形成绝缘层于该基板本体上;于该绝缘层中形成贯穿其中的多个通孔,以令各该电性接触垫外露于各该通孔;形成未贯穿该绝缘层的多个沟槽,且所述沟槽连通所述通孔;以及形成导电材于所述通孔与所述沟槽中及该绝缘层上,以于所述通孔中形成电性连接该电性接触垫的导电通孔,且于所述沟槽中形成电性连接该导电通孔的线路层,并于该绝缘层上形成电性连接该线路层的导电柱,使该导电通孔、线路层及导电柱为一体成形者。
前述的制法中,形成该导电材的方法为电镀、化镀、溅镀、蒸镀或无电镀。
前述的基板结构及其制法中,形成该基板本体的材质为硅、陶瓷或有机材质。
本发明也提供一种导电结构,其与一绝缘层结合,该导电结构包括:导电通孔,其形成于该绝缘层中;线路层,其形成于该绝缘层中并设于该导电通孔上,其中,该线路层的宽度大于该导电通孔的宽度;以及导电柱,其形成于该绝缘层上并设于该线路层上,其中,该导电柱的宽度大于或等于该线路层的宽度,且该导电通孔、线路层及导电柱为一体成形者。
前述的基板结构及其制法暨导电结构中,该导电材(或该导电通孔、线路层及导电柱的材质)为铜材或金材。
前述的基板结构及其制法暨导电结构中,该导电柱的宽度小于20微米。
另外,前述的基板结构及其制法暨导电结构中,还包括形成于该导电柱上的导电元件。
由上可知,本发明的基板结构及其制法暨导电结构中,主要藉由导电材一次形成于所述通孔与所述沟槽中,使该导电通孔、线路层及导电柱为一体成形者,以供超微小芯片或细间距(fine pitch)的电性接触垫进行覆晶电性连接。
附图说明
图1为现有具有焊料凸块的基板结构的剖视图;以及
图2A至图2H为本发明的基板结构的制法的剖视示意图。
符号说明
10 芯片
100,200 电性接触垫
11,21 绝缘层
11a 第一绝缘层
11b 第二绝缘层
12 粘附层
13 润湿层
14 保护层
15 凸块底下金属层
16 焊料凸块
2 基板结构
2’ 导电结构
20 基板本体
21a 第一子层
21b 第二子层
210 氮化硅层
211 氧化层
22 导电通孔
220 通孔
23 线路层
230 沟槽
24 阻障层
25 阻层
250 开口
26 导电柱
27 导电材
28 导电元件
d,r,w 宽度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉此技艺的人士的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2H为本发明的基板结构2的制法的剖视示意图。
如图2A所示,提供一具有多个电性接触垫200的基板本体20。于本实施例中,形成该基板本体20的材质为硅,但于其它实施例中,形成该基板本体20的材质可为陶瓷或有机材质。
如图2B所示,形成一绝缘层21于该基板本体20上,且该绝缘层21分为接触该基板本体20的第一子层21a与形成于该第一子层21a上的第二子层21b。
于本实施例中,该第一子层21a与该第二子层21b均由氮化硅层210与氧化层211所组成。
如图2C所示,形成贯穿该第一与第二子层21a,21b的多个通孔220,以令各该电性接触垫200外露于各该通孔220。于本实施例中,藉由蚀刻方式形成所述通孔220。
如图2D所示,形成多个沟槽230于该绝缘层21的第二子层21b上,且所述沟槽230连通所述通孔220。于本实施例中,藉由蚀刻方式形成所述沟槽230。
如图2E所示,形成阻障层24于该第二子层21b、沟槽230的壁面、通孔220的壁面及电性接触垫200上,再形成一阻层25于该阻障层24上,且该阻层25形成有多个开口250,以令单一开口250暴露多个该通孔220及其周围的表面。
于本实施例中,形成该阻障层24的材质为氮化钽(TaN)或氮化钛(TiN),且该阻层25为干膜(dry film)。
如图2F所示,形成导电材27于所述通孔220、所述沟槽230、及该开口250中,以于所述通孔220中形成电性连接该电性接触垫200的导电通孔22,且于所述沟槽230中形成电性连接该导电通孔22的线路层23,并于所述开口250中形成凸出所述沟槽230及电性连接该线路层23的导电柱26,使该导电通孔22、线路层23及导电柱26为一体成形,其中,单一该导电柱26覆盖多个该导电通孔22。
于本实施例中,该导电材27为铜材或金材,且形成该导电材27的方法为电镀、化镀、溅镀、蒸镀或无电镀。
如图2G所示,移除该阻层25及其下的阻障层24。于本实施例中,该导电柱26的宽度w小于20微米。
如图2H所示,形成导电元件28于该导电柱26上。于本实施例中,该导电元件28含有焊锡材料。
本发明还提供一种基板结构2,包括:一基板本体20、一形成于该基板本体20上的绝缘层21以及与该绝缘层21结合的导电结构2’。
所述的基板本体20具有多个电性接触垫200,且形成该基板本体20的材质为硅、陶瓷或有机材质。
所述的导电结构2’至少包括:至少一导电通孔22、一线路层23以及一导电柱26。
所述的导电通孔22形成于该绝缘层21中并电性连接该电性接触垫200。
所述的线路层23形成于该绝缘层21中并设于该导电通孔22上以电性连接该导电通孔22,其中,该线路层23的宽度d大于该导电通孔22的宽度r。
所述的导电柱26形成于该绝缘层21上并设于该线路层23上且覆盖至少一该导电通孔22,其中,该导电柱26的宽度w大于或等于该线路层23的宽度d,且该导电通孔22、线路层23及导电柱26为一体成形者。
于一实施例中,该导电材27(或该导电通孔22、线路层23及导电柱26的材质)为铜材或金材。
于一实施例中,该导电柱26的宽度w小于20微米。
于一实施例中,该基板结构2(或该导电结构2’)还包括形成于该导电柱26上的导电元件28。
综上所述,本发明的基板结构及其制法暨导电结构,其藉由导电材27一次形成于所述通孔220与所述沟槽230中及该绝缘层21上,使该导电通孔22、线路层23及导电柱26为一体成形者,以令该导电柱26的宽度w小于20微米,以供超微小芯片或细间距的电性接触垫进行覆晶电性连接。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (15)
1.一种基板结构,其特征为,该基板结构包括:
基板本体,其具有多个电性接触垫;
绝缘层,其形成于该基板本体上,并令所述电性接触垫显露于该绝缘层;
多个导电通孔,其形成于该绝缘层中并电性连接该电性接触垫,其中,单一所述电性接触垫上形成单一所述导电通孔;
线路层,其具有多个线路并形成于该绝缘层中及该导电通孔上,其中,该线路层的各线路的宽度大于该导电通孔的宽度;以及
导电柱,其形成于该绝缘层上并设于该线路层上,其中,该导电柱的宽度大于或等于该线路层的宽度,至少二该导电通孔、线路层及导电柱为一体成形,且单一该导电柱覆盖至少二该导电通孔。
2.如权利要求1所述的基板结构,其特征为,形成该基板本体的材质为硅、陶瓷或有机材质。
3.如权利要求1所述的基板结构,其特征为,该导电通孔、线路层及导电柱的材质为铜材或金材。
4.如权利要求1所述的基板结构,其特征为,该导电柱的宽度小于20微米。
5.如权利要求1所述的基板结构,其特征为,该基板结构还包括形成于该导电柱上的导电元件。
6.一种基板结构的制法,其特征为,该制法包括:
提供具有多个电性接触垫的基板本体;
形成绝缘层于该基板本体上;
于该绝缘层中形成贯穿其中的多个通孔,以令各该电性接触垫外露于各该通孔;
形成未贯穿该绝缘层的多个沟槽,且所述沟槽连通所述通孔;以及
形成导电材于所述通孔与所述沟槽中及该绝缘层上,以于所述通孔中形成电性连接该电性接触垫的导电通孔,其中,单一所述电性接触垫上形成单一所述导电通孔,且于所述沟槽中形成电性连接该导电通孔的线路层,并于该绝缘层上形成电性连接该线路层的导电柱,使至少二该导电通孔、线路层及导电柱为一体成形,且单一该导电柱覆盖至少二该导电通孔。
7.如权利要求6所述的基板结构的制法,其特征为,形成该基板本体的材质为硅、陶瓷或有机材质。
8.如权利要求6所述的基板结构的制法,其特征为,该导电材为铜材或金材。
9.如权利要求6所述的基板结构的制法,其特征为,形成该导电材的方法为电镀、化镀、溅镀或蒸镀。
10.如权利要求6所述的基板结构的制法,其特征为,该导电柱的宽度小于20微米。
11.如权利要求6所述的基板结构的制法,其特征为,该制法包括形成导电元件于该导电柱上。
12.一种导电结构,其与一绝缘层结合,其特征为,该导电结构包括:
导电通孔,其形成于该绝缘层中,其中,每个所述导电通孔与基板本体中不同的电性接触垫相对应;
线路层,其形成于该绝缘层中并设于该导电通孔上,其中,该线路层的宽度大于该导电通孔的宽度;以及
导电柱,其形成于该绝缘层上并设于该线路层上,其中,该导电柱的宽度大于或等于该线路层的宽度,至少二该导电通孔、线路层及导电柱为一体成形,且单一该导电柱覆盖至少二该导电通孔。
13.如权利要求12所述的导电结构,其特征为,该导电通孔、线路层及导电柱的材质为铜材或金材。
14.如权利要求12所述的导电结构,其特征为,该导电柱的宽度小于20微米。
15.如权利要求12所述的导电结构,其特征为,该导电结构还包括形成于该导电柱上的导电元件。
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