CN103066043A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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CN103066043A
CN103066043A CN2012103832373A CN201210383237A CN103066043A CN 103066043 A CN103066043 A CN 103066043A CN 2012103832373 A CN2012103832373 A CN 2012103832373A CN 201210383237 A CN201210383237 A CN 201210383237A CN 103066043 A CN103066043 A CN 103066043A
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semiconductor package
conductive pole
package part
chip
conductive
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CN103066043B (zh
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郑明达
林志伟
黄贵伟
蔡钰芃
林俊成
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体封装件，包括：工件，具有导电迹线；和芯片，具有导电柱。将芯片附接至工件，并且焊料接合区域形成在导电柱和导电迹线之间。导电柱和导电迹线之间的距离小于或等于约16μm。

Description

半导体封装件
技术领域
本发明一般地涉及半导体领域，更具体地来说，涉及半导体封装件。
背景技术
集成电路芯片包括形成在衬底上方的半导体器件，如半导体晶圆，以及包括提供集成电路电气接口的金属化接触焊盘。接合凸块是集成电路中互连结构的一部分。凸块提供集成电路器件的接口，通过该接口可以制造与器件的电连接。提供芯片的内部电路和外部电路之间连接的技术，如电路板、其他芯片、或晶圆，包括引线接合，其中引线用来连接芯片接触焊盘和外部电路，以及可能还包括领域内众所周知的其他技术。最近的芯片连接技术，称为倒装芯片技术，采用沉积在芯片接触焊盘上方的焊料凸块提供集成电路器件与外部电路的连接。为了将芯片安装至外部电路，翻转该芯片，以便其顶面朝下且其接触焊盘与外部电路的匹配接触焊盘对准。然后，焊料在倒装芯片和支撑外部电路的衬底之间回流以完成互连。得到的倒装芯片封装件比传统的基于载具的系统小得多，由于芯片直接定位于外部电路上方，使得互连电线可能短得多。因此，电感和电阻热量大大降低，从而使更高速器件成为可能。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体封装件，包括：工件，包括导电迹线；以及芯片，包括导电柱，其中，所述芯片通过形成在所述导电柱和所述导电迹线之间的焊料接合区域附接至所述工件；以及其中，所述导电柱和所述导电迹线之间的距离小于或等于16μm。在该半导体封装件中，所述导电柱和所述导电迹线之间的所述距离小于或等于12μm。
在该半导体封装件中，所述导电柱是伸长的形状。
在该半导体封装件中，所述导电柱包括铜。
在该半导体封装件中，所述工件包括：电介质衬底。
在该半导体封装件中，所述导电迹线包括铜。
在该半导体封装件中，所述导电柱和所述导电迹线之间的所述距离在5μm至16μm之间的范围内。
根据本发明的另一方面，提供了一种半导体封装件，包括：衬底，包括导电迹线；以及芯片，包括凸块结构，其中，所述凸块结构包括：导电柱和形成在所述导电柱上方的焊料层；其中，所述芯片电连接至所述衬底，并且所述凸块结构电连接至所述导电迹线，从而形成迹线上凸块(BOT)互连结构；以及其中，在所述BOT互连结构中，所述导电柱和所述导电迹线之间的距离小于或等于16μm。
在该半导体封装件中，所述凸块结构是伸长的形状。
在该半导体封装件中，所述凸块结构是具有曲边的矩形形状。
在该半导体封装件中，所述导电柱包括铜。
在该半导体封装件中，所述衬底是电介质衬底。
在该半导体封装件中，所述导电迹线包括铜。
在该半导体封装件中，所述距离小于或等于12μm。
根据本发明的又一方面，提供了一种方法，包括：提供包括伸长的导电柱的半导体衬底；以及在所述伸长的导电柱上方形成焊料层；其中，所述焊料层的厚度小于或等于16μm。
在该方法中，所述伸长的导电柱为具有至少一个曲边的矩形形状。
该方法进一步包括：提供包括导电迹线的电介质衬底；以及将所述半导体衬底附接至所述电介质衬底，其中，所述焊料层形成在所述伸长的导电柱和所述导电迹线之间。
在该方法中，所述导电柱和所述导电迹线之间的距离小于或等于16μm。
在该方法中，所述导电迹线包括铜。
在该方法中，所述导电柱包括铜。
附图说明
图1和图2是根据一些实施例制造半导体器件的中间阶段的横截面图。
图3是根据实施例的凸块底部金属(underbump metallurgy，UBM)层和/或导电柱的三个示例性的伸长结构的俯视图。
图4是根据实施例的包括连接至衬底的芯片的半导体封装件的横截面图。
图5是根据实施例的三个示例性的伸长的迹线上凸块导线(bump-on-trace，BOT)互连结构的俯视图。
图6是根据实施例形成半导体封装件的方法的流程图。
具体实施方式
现在，将结合附图详细说明的示例性实施例作为参考。在附图和描述中使用相同的参考数字，以指示相同的或类似的部件。在附图中，为了清楚和方便，可能夸大了形状和厚度。此描述尤其是指根据本发明形成装置的部件的元件，或者更直接地与装置协作的元件。可以理解，未具体地示出的或描述的元件可以采用本领域技术人员众所周知的各种形式。再者，当称为一层位于另一层上方或者位于衬底上方时，它可以是直接位于其他层上方或者位于衬底上方，或者也可以存在中间层。
整个本说明书中引用“一个实施例”或“某个实施例”意味着至少一个实施例包括关于实施例所述的特定部件、结构或特征。因此在本说明书的各个位置出现的短语“在一个实施中”或“在某个实施例中”不一定指同一个实施例。而且，在一个或多个实施例中可以以任意适当的方式组合特定部件、结构或特征。应该理解，以下附图没有按比例绘制；而这些附图只是为了阐明。
图1和图2是根据实施例的集成电路制造工艺中的各个阶段的半导体器件的一部分的横截面图。
参考图1，示出了具有形成在衬底10中和/或上方的电路的芯片100的一部分。衬底10可以是半导体集成电路制造中通常采用的各种类型的半导体衬底中的一种，集成电路可以形成在其中和/或其上。半导体衬底可以是包括半导体材料的任意结构，该半导体材料包括(但不限于)：体硅、半导体晶圆、绝缘体上硅(SOI)衬底、或者硅锗衬底。也可以采用其他半导体材料，包括III族、IV族、和/或V族半导体。尽管未示出，但是可以意识到，衬底10可以进一步包括多个隔离部件，如浅沟槽隔离(STI)部件或者局部硅氧化(LOCOS)部件。隔离部件可以隔离形成在衬底10中和/或上方的各个微电子元件。可以形成在衬底10中的微电子元件类型的实例包括(但不限于)：晶体管，如金属氧化层半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)、电阻器、二极管、电容器、电感器、熔丝，和/或其他适当的元件。实施各种工艺形成各种微电子元件，包括(但不限于)：沉积、蚀刻、注入、退火、和其他合适的工艺中一种或多种。微电子元件互连从而形成集成电路器件，该集成电路器件可以包括：逻辑器件、存储器件(例如，SRAM)、射频(RF)器件、输入/输出(I/O)器件、芯片上系统(SoC)器件、和其他适当类型的器件中一个或多个。衬底10进一步包括覆盖集成电路的互连结构。互连结构包括：层间介电层和覆盖集成电路的金属化结构。金属化结构中的层间介电层可以包括：低k介电材料、未掺杂的硅酸盐玻璃(USG)、氮化硅(SiN))、氮氧化硅(SiON)、和其他常用的材料中的一种或多种。低k介电材料的介电常数(k值)可以小于约3.9，或者小于约2.8。金属化结构中的金属线可以由铜或铜合金形成。
在实施例中，在层间介电层的顶层中或上方形成并且图案化导电焊盘12，该导电焊盘是导电布线的一部分。导电焊盘12包括：提供电连接的接触焊盘，为了便于外部电连接，在该导电焊盘上方形成凸块结构，如UBM结构、焊料凸块或铜柱凸块。导电焊盘12可以由任意适当的导电材料形成，该导电材料包括：铜(Cu)、钨(W)、铝(Al)、铝铜(AlCu)合金、银(Ag)或类似材料中的一种或多种。在一些实施例中，导电焊盘12可以是提供期望引脚或球布局的区域或再分布线的端部。在导电焊盘12上方形成并图案化一个或多个钝化层，如钝化层14。在一个实施例中，开口15设置在钝化层14中，暴露出下面的导电焊盘12的一部分。在至少一个实施例中，钝化层14由非有机材料形成，如未掺杂的硅酸盐玻璃、氮化硅、氮氧化硅、氧化硅、或者其组合。钝化层14可以由任意合适的方法形成，如化学汽相沉积(CVD)、物理汽相沉积(PVD)等。在其他实施例中，钝化层14可以由聚合物层形成，如环氧树脂、聚酰亚胺、苯并环丁烯(benzocyclobutene，BCB)、多聚苯并嗯唑(polybenzoxazole，PBO)等，但是也采用其他相对较软的经常是有机介电材料。本领域的技术人员之一应该意识到，示出的单个焊盘层和单个钝化层仅是为了说明的目的。因此，其他实施例可以包括任意数量的导电焊盘和/或钝化层。
图1示出了形成在钝化层14上方并且通过开口15电连接至导电焊盘12的凸块底部金属(UBM)层16和导电柱18。在实施例中，UBM层16和/或导电柱18的俯视图是伸长的形状。可以采用各种形状实现该伸长结构，各种形状包括(但不限于)：矩形、具有至少一个曲边或圆边的矩形、具有两个凸形曲边的矩形、卵形、椭圆形或任何其他伸长的形状。现在参考图3，示出了UBM层16和/或导电柱18的三个示例性的伸长结构的俯视图。伸长结构110示出了具有两个凸形长曲边的矩形形状。伸长结构120示出了椭圆形凸块结构。类似地，伸长结构130示出了具有两个凸形短曲边的矩形形状。
在实施例中，在钝化层14的表面和导电焊盘12的暴露部分上面形成UBM层16。在实施例中，UBM层16包括扩散势垒层或粘合层，该UBM层可能包括：钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)等，并且通过PVD或溅射形成该UBM层。在实施例中，UBM层16进一步包括通过PVD或溅射形成在扩散势垒层上方的种子层。种子层可以由铜(Cu)或铜合金形成，该铜合金包括：铝(Al)、铬(Cr)、镍(Ni)、锡(Sn)、金(Au)或其组合。在一些实施例中，UBM层16包括钛层和铜种子层。
在实施例中，在UBM层16上方形成导电柱18。在至少一个实施例中，导电柱18包括铜层。铜层包括：纯元素铜、含有不可避免的杂质的铜，和/或含有少量的以下元素的铜合金，如钽、铟(In)、锡(Sn)、锌(Zn)、锰(Mn)、铬(Cr)、钛(Ti)、锗(Ge)、锶(Sr)、铂(Pt)、镁(Mg)、铝(Al)或锆(Zr)。导电柱18可以由溅射、印刷、电镀、化学镀、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)和/或常用的CVD方法形成。在一个实施例中，铜层由电化学电镀(ECP)形成。在示例性实施例中，导电柱18的厚度大于20μm。在另一个示例性实施例中，导电柱18的厚度大于40μm。例如，导电柱18的厚度为约20-50μm，或者厚度为约40-70μm，但是该厚度可能更大或者更小。在至少一个实施例中，导电柱18的尺寸和形状大致与UBM层16的尺寸和形状相同。在一些实施例中，由于制造工艺导致的偏差，导电柱18的尺寸和形状与UBM层16的尺寸和形状不完全相同。
在实施例中，在导电柱18上方形成焊料层20。焊料层20可以通过电镀方法由无铅焊料材料制成，如Sn、SnAg、SnAgCu(铜的重量百分比小于0.3％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnCu、SnZnIn、SnAgSb、以及其他类似的适当材料。在至少一个实施例中，形成具有可控体积的焊料层20。申请人应该理解，当用于给定区域的焊接材料的体积太大时，在一些细节距(fine-pitch)应用中可能发生桥连和虚焊问题。在实施例中，焊料层20形成为小于或等于16μm的可控厚度T。在另一实施例中，厚度T小于或等于12μm。在至少另一个其他实施例中，焊料层20的厚度T控制在约5μm至约16μm的范围内。
在实施例中，焊料回流工艺在等于或高于焊料融化温度的温度下实施。在焊料回流工艺之后，焊料层20融化并且转换为回流焊料层20。在回流工艺之后，厚度和表面形状可能改变。例如，回流焊料层20具有如图2所示的球面。在实施例中，回流焊料层20的最大高度H大于或等于厚度T。在一个实例中，最大高度H小于或等于16μm。在另一个实例中，最大高度H小于或等于12μm。在一些实例中，最大高度H小于或等于21μm。
在实施例中，凸块结构22包括UBM层16、导电柱18、和回流焊料层20，在芯片100上方完成的该凸块结构。然后，将芯片100附接至工件，如电介质衬底、封装衬底、印刷电路板(PCB)、中间板、晶圆、采用晶圆级或芯片级堆叠的另一芯片、封装单元等。例如，实施例可用于芯片与衬底的接合结构、芯片与芯片的接合结构、芯片与晶圆的接合结构、晶圆与晶圆的接合结构、芯片级封装、晶圆级封装等。随后，凸块结构22可以连接至工件上方的导电迹线，因此，半导体封装件中形成迹线上凸块(BOT)互连结构。
图4是根据实施例的包括连接至工件的芯片的半导体封装件的横截面图。
在实施例中，工件200包括衬底202，衬底202可以是封装衬底、PCB、晶圆、芯片、中间板、电介质衬底、封装单元或其他适当衬底。衬底202包括多个导电迹线204，该导电迹线电连接至下面的金属互连。导电迹线204可以由大体上纯的铜、铝铜，或其他金属材料(例如，钨、镍、钯、金)及其合金组成。将导电迹线204的某些区域限定为电连接至凸块结构22的接合区域。在一些实施例中，预焊料层设置在导电迹线204上方。可以将焊料掩模层设置为限定导电迹线204的接合区域。焊料掩模层可以是焊料掩模定义(solder mask defined，SMD)类型或者非焊料掩模定义(non-solder mask defined，NSMD)类型。为了清楚，未在图4中示出焊料掩模层。
在实施例中，如图4所示，通过倒装芯片接合技术，将具有凸块结构22的芯片100上下翻转并且将该芯片附接至工件200，以形成半导体封装件300。示例性的连接工艺包括：焊剂应用、芯片放置、熔化的焊料接合区域的回流，和/或清洗焊剂残留物中的至少一中。可采用高温工艺，如回流或热压接合，来熔化导电柱18上方的焊料层20。因此，熔化的焊料材料将芯片100和工件200接合为一体，并且将凸块结构22电连接至导电迹线204。通过熔化的焊料材料形成的焊料接合区域20″形成在导电柱18和导电迹线204之间。通过焊料接合区域20″将凸块结构22电连接至导电迹线204并且因此，在半导体封装件300中形成迹线上凸块(BOT)互连结构302。在焊料接合之后，底部填充物(未示出)可以填充在芯片100和工件200之间的空间，因此，底部填充物也可以填充在邻接的导电迹线之间的空间中。可选地，底部填充物没有设置在半导体封装件300中。
现在参考图5，示出了三个示例性的BOT互连结构的俯视图。结构302a包括形成在导电迹线204上方的伸长的凸块结构22a，凸块成型为具有两个凸形长曲边的矩形。结构302b包括形成在迹线204上方的椭圆形的凸块结构22b。类似地，结构302c包括形成在导电迹线204上方的伸长的凸块结构22c，凸块成型为具有两个凸形短曲边的矩形。在一些实施例中，伸长的凸块结构的伸长轴同轴延伸，即，与导电迹线204的轴平行或近似平行。
在实施例中，由于在凸块形成期间控制焊料体积，所以可以很好地控制焊料接合区域20的体积以克服桥连和虚焊问题，从而解决产量损失问题。在BOT互连结构302中，从导电柱18的顶面至导电迹线204的顶面测量的距离D可能基本上等于焊料层20的厚度T。在实施例中，距离D小于或等于约16μm。在另一实施例中，距离D小于或等于约12μm。在其他实施例中，距离D在约5μm至约16μm的范围内。从实验结果观察到，当厚度T控制在等于或小于约16μm的值时，距离D可以控制在等于或小于约16μm的值，并且测量中没具有检测到电气短路的桥连问题。当厚度T和距离D控制在等于或小于约12μm的值时可以发现同样的结果。
图6是根据实施例形成半导体封装件的方法的流程图。方法500从步骤510开始，其中，提供具有导电柱的芯片。在实施例中，导电柱包括铜或铜合金。在实施例中，导电柱是伸长的形状。方法500继续至步骤520，其中，在导电柱上方形成具有可控厚度T的焊料层。在实施例中，厚度T小于或等于约16μm。在实施例中，厚度T小于或等于约12μm。在实施例中，厚度T在约5μm至约16μm的范围内。方法500继续至步骤530，其中，芯片附接至具有导电迹线的工件，并且通过焊料层将导电柱电连接至导电迹线。因此，在半导体封装件中形成迹线上凸块(BOT)互连结构。在实施例中，工件是电介质衬底，并且导电迹线包括铜或铜合金。在至少一个实施例中，导电柱和导电迹线之间的距离小于或等于约16μm。
根据实施例，半导体封装件包括：工件，具有导电迹线；和芯片，具有导电柱。芯片通过形成在导电柱和导电迹线之间的焊料接合区域附接至工件。导电柱和导电迹线之间的距离小于或等于16μm。
根据实施例，半导体封装件包括：衬底，具有导电迹线；和芯片，具有凸块结构。凸块结构包括导电柱和形成在导电柱上方的焊料层。芯片电连接衬底，并且凸块结构电连接导电迹线，从而形成迹线上凸块(BOT)互连结构。在BOT互连结构中，导电柱和导电迹线之间的距离小于或等于约16μm。
根据本公开的另一方面，方法包括：提供具有伸长的导电柱的半导体衬底，以及在伸长的导电柱上方形成焊料层。焊料层厚度小于或等于约16μm。
在以上描述中，参考具体的示例性实施例描述了本发明。然而很明显，在不背离本发明的宽泛主旨和范围的情况下，可以做各种更改、结构、工艺、和改变。因此，说明书和附图是为了说明而不用于限定。据了解本发明能够使用各种其它组合和应用环境并且能够在如本文所述的本发明的范围内改变或更改。

Claims (10)

1.一种半导体封装件，包括：
工件，包括导电迹线；以及
芯片，包括导电柱，
其中，所述芯片通过形成在所述导电柱和所述导电迹线之间的焊料接合区域附接至所述工件；以及
其中，所述导电柱和所述导电迹线之间的距离小于或等于16μm。
2.根据权利要求1所述的半导体封装件，其中，所述导电柱和所述导电迹线之间的所述距离小于或等于12μm。
3.根据权利要求1所述的半导体封装件，其中，所述导电柱是伸长的形状。
4.根据权利要求1所述的半导体封装件，其中，所述导电柱包括铜。
5.根据权利要求1所述的半导体封装件，其中，所述工件包括：电介质衬底。
6.根据权利要求1所述的半导体封装件，其中，所述导电迹线包括铜。
7.根据权利要求1所述的半导体封装件，其中，所述导电柱和所述导电迹线之间的所述距离在5μm至16μm之间的范围内。
8.一种半导体封装件，包括：
衬底，包括导电迹线；以及
芯片，包括凸块结构，其中，所述凸块结构包括：导电柱和形成在所述导电柱上方的焊料层；
其中，所述芯片电连接至所述衬底，并且所述凸块结构电连接至所述导电迹线，从而形成迹线上凸块(BOT)互连结构；以及
其中，在所述BOT互连结构中，所述导电柱和所述导电迹线之间的距离小于或等于16μm。
9.根据权利要求8所述的半导体封装件，其中，所述凸块结构是伸长的形状。
10.一种方法，包括：
提供包括伸长的导电柱的半导体衬底；以及
在所述伸长的导电柱上方形成焊料层；
其中，所述焊料层的厚度小于或等于16μm。
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