CN101127345A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN101127345A
CN101127345A CNA200710141086XA CN200710141086A CN101127345A CN 101127345 A CN101127345 A CN 101127345A CN A200710141086X A CNA200710141086X A CN A200710141086XA CN 200710141086 A CN200710141086 A CN 200710141086A CN 101127345 A CN101127345 A CN 101127345A
Authority
CN
China
Prior art keywords
interconnection
insulating barrier
semiconductor device
opening
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA200710141086XA
Other languages
English (en)
Other versions
CN101127345B (zh
Inventor
山形修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of CN101127345A publication Critical patent/CN101127345A/zh
Application granted granted Critical
Publication of CN101127345B publication Critical patent/CN101127345B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种包括半导体的封装形式的半导体装置及其制造方法。该半导体装置包括：半导体衬底，具有有源元件布置于其上和衬垫布置于其表面上并连接至有源元件；布置于半导体衬底上并连接至衬垫的第一互连；以覆盖第一互连的关系布置于半导体衬底上并具有延伸到第一互连的部分的开口的第一绝缘层；布置在开口内和第一绝缘层上并连接至第一互连的第二互连。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置和制造这种半导体装置的方法，更特别地涉及一种具有在半导体衬底上的重布线层(rerouting layer)的封装形式的半导体装置和制造这种半导体装置的方法。
背景技术
对包括数字视频摄像机、数字移动电话和膝上型个人电脑的更小、更薄和更轻的便携式电子装置的需求正不断增加。为了满足该需求，在三年内，最近比如VLSI电路的半导体装置已被按比例缩小百分之七十。另外，已做出研发的努力以进行增加电子电路装置中安装板(印刷线路板)上的部件的封装密度的重要任务，其中半导体装置安装在印刷线路板上。
半导体装置封装形式已从比如双列直插封装(DIP，Dual Inline Package)的引脚插入(lead-insertion)型发展到表面安装型。进一步发展了倒装安装工艺，其中金或焊料的凸点(突出电极)被布置在半导体芯片的衬垫电极上，和半导体芯片以其面向下地通过凸点连接至线路板。
也已做出努力以发展称作封装中系统(SiP，System in Package)的复杂形式的半导体装置封装，其结合有比如电感器和电容器的无源元件和包括匹配电路和滤波器。
例如，日本专利公开No.2003-124236公开了以SiP形式的半导体装置的结构。
如果SiP以晶片级被封装，那么它被设计以提供其中形成在有源元件上的新互连的结构(以下简称重布线)，并提供至有源元件的电极的连接。
如果重布线互连被提供为单层，那么外部终端不能被布置在有源元件的电极上。如果采用单层的重布线互连，为形成重布线互连以提供必要数量的I/O端口，那么必须减少L/S，因此需要改变装置设计、工序和材料。
即使I/O端口的数量是足够的，那么为避免与有源元件的电极干扰，必须减少I/O端口的数量或I/O端口必须在周边区域被排列成两行。结果，安装板必须承载高封装密度的元件。
上述问题能通过采用两层重布线互连来解决。然而，两层重布线互连需要绝缘层被加倍以在其中嵌入互连，导致成本增加。
要形成的绝缘层有必要足够厚以填充台阶。然而，厚绝缘层趋向增加晶片的翘曲(warpage)。增加的晶片的翘曲引起在外部电极形成工艺、测量工艺和减薄工艺中的装置操作问题，和装置操作问题易于降低生产效率。
发明内容
在其中重布线互连形成于半导体衬底上的半导体装置封装中，难于减薄其中嵌入了重布线互连的绝缘层。
按照本发明的实施例，包括半导体的封装形式的半导体装置，包括：半导体衬底，具有有源元件布置在其上和衬垫布置在其表面并连接至有源元件；第一互连，布置在半导体衬底上并连接至衬垫；第一绝缘层，以覆盖第一互连的关系布置在半导体衬底上并具有延伸到第一互连的部分的开口；第二互连，布置在开口内和第一绝缘层上并连接至第一互连。
用上述半导体装置，连接至衬垫的第一互连布置在半导体衬底上，该半导体衬底具有有源元件布置在其上和衬垫布置在其表面上并连接至有源元件。第一绝缘层以覆盖第一互连的关系布置在半导体衬底上并具有延伸到第一互连的部分的开口。第二互连布置在开口中和在第一绝缘层上，并连接至第一互连。
按照本发明的实施例，制造包括半导体的封装形式的半导体装置的方法包括如下步骤：在半导体衬底上形成第一互连，该半导体衬底具有有源元件布置在其上和衬垫布置在其表面上并连接至有源元件，第一互连连接至衬垫；在半导体衬底上以覆盖第一互连的关系形成第一绝缘层，第一绝缘层具有延伸到第一互连的部分的开口；以及在开口内和第一绝缘层上形成第二互连，第二互连被连接至第一互连。
用制造半导体装置的上述方法，连接至衬垫的第一互连形成于半导体衬底上，该半导体衬底具有有源元件布置在其上和衬垫布置在其表面上并连接至有源元件。
然后，第一绝缘层以覆盖第一互连的关系形成于半导体衬底上，第一绝缘层具有延伸到第一互连的部分的开口。
然后，第二互连形成于开口内和第一绝缘层上，第二互连被连接至第一互连。
按照本发明的实施例，在具有布置于半导体衬底上的重布线互连的封装的半导体装置中，其中嵌入重布线互连的绝缘层被制成薄的。
按照本发明的实施例，当具有布置于半导体衬底上的重布线互连的封装的半导体装置通过上述方法制造时，其中嵌入重布线互连的绝缘层被制成薄的。
附图说明
图1A是按照本发明的第一实施例的半导体装置的截面图；
图1B是按照第一实施例的半导体装置的第一互连的放大的部分平面图；
图2A至图2S是说明制造按照第一实施例的半导体装置的方法的步骤的截面图；
图3是按照本发明第二实施例的半导体装置的截面图；以及
图4A至图4F是说明制造按照第二实施例的半导体装置的方法的步骤的截面图。
具体实施方式
下面将参考附图详细描述按照本发明的实施例的半导体装置和制造该半导体装置的方法。
第一实施例
图1以截面图示出了按照本发明的第一实施例的半导体装置，该半导体装置用形成于半导体衬底上的重布线互连被封装。
如图1A所示，衬垫11布置在硅衬底10上，在硅衬底10上布置有包括有源元件的电子电路，衬垫11连接至该电子电路。硅衬底10没有衬垫11的区域用比如氧化硅等的保护层12覆盖。
硅衬底10具有等于或大于4.5mm2的尺寸。
TiCu等的第一互连13连接至衬垫11。例如，每个第一互连13包括具有160nm的厚度的Ti层和具有800nm的厚度的Cu层。每个第一互连的总厚度等于或小于1μm。
图1B以平面图示出每个第一互连13。如图1B所示，第一互连13包括互连区域13a和焊盘(land)区域13b。互连区域13a具有约30μm的宽度。焊盘区域13b具有宽度b和长度c和具有b×c＝约100μm×100μm的尺寸，因此比互连区域13a宽。
聚酰亚胺树脂等的第一绝缘层15以覆盖第一互连13的关系布置在保护层12上。
第一绝缘层15具有被界定在其中的开口15a，开口15a延伸到第一互连13的焊盘区域13b。每个开口15a具有约100μm的直径。图1B示出关于焊盘区域13b的开口15a的布局。
第二互连布置在第一绝缘层15上，被部分地嵌入开口15a并与连接至第一互连13的插塞一体化。每个第二互连包括TiCu种子层16和铜层18。
因为第一互连13的小厚度(1μm)和由铜镀层形成的上互连的厚度需要被保持平衡以弛豫应力，开口15a是大尺寸的。第一互连13的焊盘区域13b被设置为上述尺寸以使开口15a大。
铜等的导电柱20连接到第二互连。
由聚酰胺酰亚胺树脂(polyamideimide resin)、聚酰亚胺树脂(polyimideresin)、环氧树脂、酚醛树脂或聚对亚苯基苯并双噁唑(polyparaphenylenebenzobisoxazole)制成的绝缘缓冲层21布置在导电柱20之间的第一绝缘层15上。
凸点(突出电极)22被分别布置在缓冲层21上并连接至导电柱20。
在按照第一实施例的半导体装置中，包括第一互连13和第二互连(层16、18)的互连层被嵌入在包括第一绝缘层15和缓冲层21的绝缘层内。
虽然第一互连13和第二互连(层16、18)被堆叠在硅衬底10上，但是第一互连13为具有等于或小于1μm的很小厚度的薄膜互连的形式，第一互连13直接形成于硅衬底10上而不需要在第一互连13下面的树脂绝缘层。
从而，在有重布线互连布置在半导体衬底上的封装的半导体装置中，重布线互连嵌入其中的绝缘层被制成薄的。
下面将参考图2A至图2S描述制造按照第一实施例的半导体装置的方法。按照本实施例，制造方法的所有步骤能以晶片级被进行。
如图2A所示，包括有源元件的电子电路(没有示出)形成于具有725μm的厚度的硅衬底10上，衬垫11形成于硅衬底10上，并且在电路平面内被连接至电子电路。没有衬垫11的硅衬底10的区域被氧化硅等的保护层12覆盖。
然后，如图2B所示，例如，TiCu层13S通过溅射沉积到保护层12和衬垫11上的至此形成的整个表面上。例如，TiCu层13S包括具有160nm的厚度的Ti膜和具有600nm的厚度的Cu膜。
然后，如图2C所示，例如，具有第一互连的图案的抗蚀膜14通过光刻沉积到TiCu膜13S上。
然后，如图2D所示，TiCu层13S使用抗蚀膜14作为掩模由RIE蚀刻，因此形成TiCu的第一互连13。
然后，如图2E所示，例如，抗蚀膜14由灰化除去。此后，如图2F所示，至此形成的整个表面通过旋涂或印刷被供给比如聚酰亚胺树脂、酚醛树脂、环氧树脂等的光敏绝缘材料，因此形成第一绝缘层15。第一绝缘层15在它被硬化之后具有从约4到10μm范围的厚度。
如果第一绝缘层15通过旋涂由光敏聚酰亚胺树脂形成，则它在下面的条件下生长：
旋涂：1000rpm(30秒)+1950rpm(40秒)+1000rpm(10秒)+1500rpm(10秒)+1500rpm(10秒)；
预先烘焙：90℃(120秒)+100℃(120秒)。
然后，如图2G所示，例如，延伸到第一互连13的焊盘13b的开口15a，通过按照图形将第一绝缘层15曝光至125mJ/cm2的曝光水平并将其显影，形成于第一绝缘层15内。在此时，第一绝缘层15沿划线SL的区域也被除去。
在显影之后，第一绝缘层15由后硬化工艺在300℃硬化60分钟。
然后，如图2H所示，在整个表面被清除浮渣(descum)并蚀刻以溅射预处理之后，TiCu层通过溅射被沉积到整个表面上，覆盖第一绝缘层15内的开口15a，因此形成种子层16。例如，该TiCu层包括具有160nm的厚度的Ti膜和具有600nm的厚度的Cu膜。
然后，如图2I所示，涂布并显影抗蚀膜以防止第一绝缘层15内除了开口15a外的其它区域和第二互连形成区域被镀覆。具体地，抗蚀膜17沉积为暴露第一绝缘层15内的开口15a和第二互连形成区域的图案。
然后，如图2J所示，按照使用抗蚀膜17为掩模和以种子层16为一个电极的电解电镀工艺，在第一绝缘层15和第二互连形成区域内通过使用铜镀覆它们而形成了铜层18。
然后，如图2K所示，例如，抗蚀膜17由灰化被除去。此后，如图2L所示，例如，抗蚀膜19通过旋涂形成，并通过光刻曝光和显影以在导电柱形成区域形成延伸到铜层18的表面的开口。
然后，如图2M所示，按照使用种子层16为一个电极的电解电镀工艺，导电柱20在抗蚀膜19内的开口内的铜层18上形成。每个导电柱20具有从180到300μm的范围的直径和从80到180μm范围的高度。
然后，如图2N所示，例如，抗蚀膜19由灰化被除去。此后，如图2P所示，例如，使用导电柱20和铜层18作为掩模，蚀刻种子层16。
以这种方式，由种子层16和铜层18组成的第二互连与连接至第一互连13的插塞成一体地形成于第一绝缘层15上，导电柱20形成在其上。
然后，如图2P所示，通过旋涂、印刷或模制成型沉积环氧基树脂、聚酰亚胺基树脂、聚硅酮基树脂、聚酰胺酰亚胺树脂、聚酰亚胺树脂、酚醛树脂或聚对亚苯基苯并双噁唑树脂，绝缘缓冲层21被沉积至足以完全覆盖导电柱20厚度。
然后，如图2Q所示，例如，在缓冲层21的树脂被硬化后，导电柱20的上端通过研磨被暴露。在此时，例如，使用#600的砂轮，使其以3500rpm旋转，以0.5mm/sec的速率研磨缓冲层21。
然后，如图2R所示，通过放置焊球或印刷焊膏，形成凸点(突出电极)22以连接至各自的导电柱。
此后，如图2S所示，例如，硅衬底10从其背面通过BGR减薄至期望的厚度，和通过刀片B被切割成独立的半导体装置。
现在完成了图1A中所示的半导体装置。
按照第一实施例的制造半导体装置的方法提供了下面的优点：当第一互连13和第二互连(16、18)形成于硅衬底10上时，第一互连13直接形成为具有等于或小于1μm的厚度的很薄的膜，而不需要第一互连13下面的树脂绝缘层。
所以，当具有布置在半导体衬底上的重布线互连的封装的半导体装置通过上述方法被制造时，重布线互连嵌入其中的绝缘层被制成薄的。
此外，在具有重布线互连设置于两个或更多层内的晶片级封装中，减小了由多层互连引起的任何晶片翘曲，允许以增加的自由度使互连被安排在两层或更多层。所以，外部电极的位置不依赖于有源元件的电极的位置，因此能被容易地设置在周边区域。然而，因为它的高频特征，第一互连应优选地被安排在尽可能小的距离上，而不是大的距离上。
按照本实施例的制造半导体装置的方法的步骤的数目小于电镀Cu和形成绝缘层的步骤被重复的情况下的数目。
第二实施例
图3以截面图示出了按照本发明第二实施例的半导体装置，该半导体装置以形成于半导体衬底上的重布线互连被封装。
按照第二实施例的半导体装置区别于按照第一实施例的半导体装置的是它没有缓冲层21和导电柱20，聚酰亚胺的第二绝缘层30以覆盖第二互连(16、18)的关系沉积到第一绝缘层15上，第二绝缘层30具有延伸到第二互连的铜层18的开口30a，凸点31被沉积到开口30a内并连接至第二互连。按照第二实施例的半导体装置的其它细节与按照第一实施例的半导体装置的细节相同。
硅衬底10具有等于或小于4.5mm2的尺寸。因此，半导体装置不需要用于应力弛豫的缓冲层和导电柱。
在按照第二实施例的半导体装置中，第一互连13和第二互连(16、18)形成于硅衬底10上，第一互连13直接形成为具有小于1μm的厚度的很薄的膜，而不需要第一互连13下面的树脂绝缘层。
从而，在具有布置于半导体衬底上的重布线互连的封装的半导体装置中，其中嵌入重布线互连的绝缘层被制成薄的。
因为按照第二实施例的半导体装置没有在按照第一实施例的半导体装置中采用的导电柱，所以不需要消耗时间的镀覆工艺，并且半导体装置的厚度被减小。
下面参考图4A到图4F描述制造按照第二实施例的半导体装置的方法。按照本实施例，制造方法的所有步骤可以在晶片级被进行，如第一实施例。
该方法直到图4A中所示的步骤以与第一实施例相同的方式进行。
例如，连接至电子电路的衬垫11和保护层12形成于硅衬底10上，和形成连接至衬垫11的第一互连13。形成第一绝缘层15，和延伸到第一互连13的开口15a形成于第一绝缘层15内。种子层16以覆盖开口15a的关系形成于整个表面上，铜层18形成于开口15a和第一互连形成区域内。
然后，如图4B所示，种子层16使用铜层18作为掩模被刻蚀。
现在，由种子层16和铜层18组成的第二互连形成于第一绝缘层15上，与连接至第一互连13的插塞一体化。
然后，如图4C所示，至此形成的整个表面通过旋涂或印刷被供给比如聚酰亚胺树脂、酚醛树脂、环氧树脂等的光敏绝缘材料，因此形成第二绝缘层30。第二绝缘层30在它被硬化之后具有从约4到10μm的范围的厚度。
如果第二绝缘层30通过旋涂由光敏的聚酰亚胺树脂形成，那么它以下面的条件被生长：
旋涂：1000rpm(30秒)+1950rpm(40秒)+1000rpm(10秒)+1500rpm(10秒)；
预先烘焙：90℃(120秒)+100℃(120秒)。
然后，如图4D所示，例如，延伸到第二互连的铜层18的开口30a通过按照图形将第二绝缘层30曝光至125mJ/cm2的曝光水平并将其显影而形成，在此时，第二绝缘层30沿划线SL的区域也被除去。
显影之后，第二绝缘层30通过后硬化工艺在300℃被硬化60分钟。
然后，如图4E所示，凸点(突出电极)31通过放置焊球或印刷焊膏形成于第二绝缘层30中的开口30a内。
此后，如图4F所示，例如，硅衬底10从它的背面通过BGR减薄至期望的厚度，并通过刀片B切割成独立的半导体装置。
现在完成如图3所示的半导体装置。
制造按照第二实施例的半导体装置的方法提供下面的优点：当第一互连13和第二互连(16、18)形成于硅衬底10上时，第一互连13直接形成为具有等于或小于1μm的厚度的很薄的膜，而不需要第一互连13下面的树脂绝缘层。
因此，当由上述方法制造具有布置在半导体衬底上的重布线互连的封装的半导体装置时，重布线互连嵌入其中的绝缘层被制成薄的。
本发明不限制于上述的细节，但示出的实施例可以被修改。
例如，比如电感器和电容器的无源元件可以形成于第一和第二互连内。
半导体芯片可以被嵌入到绝缘层内。
在所示的实施例中，在两层的互连，也就是，第一互连和第二互连，被设置于绝缘层内。然而，互连可以被提供于更多或更少的层内。类似地，半导体装置可以比上述的半导体装置具有更多或更少的绝缘层。
虽然详细地示出和描述了本发明的某个优选的实施例，但应该了解的是各种变化和修改可以在其中做出而不偏离权利要求的范围。
本领域的技术人员应了解，各种修改、组合、子组合和变化可以根据设计需要和其它因素而进行，只要它们在权利要求或其等同特征的范围内。
本发明包含与在日本特许厅于2006年8月17日提交的日本专利申请JP2006-222468的主题，将其全文引用结合于此。

Claims (10)

1.一种包括半导体的封装形式的半导体装置，包括：
半导体衬底，具有有源元件和布置在表面上并连接至所述有源元件的衬垫；
第一互连，布置在所述半导体衬底上并连接至所述衬垫；
第一绝缘层，以覆盖所述第一互连的关系布置在所述半导体衬底上并具有延伸到所述第一互连的部分的开口；以及
第二互连，布置在所述开口内和所述第一绝缘层上并连接至所述第一互连。
2.如权利要求1所述的半导体装置，其中所述第一互连具有等于或小于1μm的膜厚。
3.如权利要求1所述的半导体装置，其中所述第一互连具有互连区域和宽于所述互连区域的焊盘区域，所述开口延伸到所述焊盘区域。
4.如权利要求1所述的半导体装置，还包括：
缓冲层，布置在包括所述第一绝缘层的绝缘层上；
导电柱，延伸穿过所述缓冲层并连接至包括所述第一互连和第二互连的互连层；以及
突出电极，布置在所述导电柱的上表面并从所述缓冲层的表面突出。
5.一种制造包括半导体的封装形式的半导体装置的方法，包括步骤：
(a)在具有有源元件和布置在表面上并连接至所述有源元件的衬垫的半导体衬底上形成第一互连，所述第一互连连接至所述衬垫；
(b)在所述半导体衬底上以覆盖所述第一互连的关系形成第一绝缘层，所述第一绝缘层具有延伸到所述第一互连的部分的开口；以及
(c)在所述开口内和所述第一绝缘层上形成第二互连，所述第二互连连接至所述第一互连。
6.如权利要求5所述的方法，其中所述步骤(a)包括形成所述第一互连至等于或小于1μm的膜厚的步骤。
7.如权利要求5所述的方法，其中所述步骤(a)包括通过溅射形成所述第一互连的步骤。
8.如权利要求5所述的方法，其中所述步骤(b)包括步骤：
(d)在所述半导体衬底上以覆盖所述第一互连的关系形成所述第一绝缘层；以及
(e)在所述第一绝缘层内形成延伸到所述第一互连的部分的所述开口。
9.如权利要求8所述的方法，其中，
所述步骤(a)包括形成所述第一互连以具有互连区域和宽于所述互连区域的焊盘区域的步骤，以及
所述步骤(e)包括形成所述开口以延伸到所述焊盘区域的步骤。
10.如权利要求5所述的方法，进一步包括步骤：
形成连接至包括所述第一互连和第二互连的互连层的导电柱；
在包括所述第一绝缘层的绝缘层上形成缓冲层，使所述导电柱的上表面暴露；以及
在所述导电柱上形成突出电极以从所述缓冲层的表面突出。
CN200710141086XA 2006-08-17 2007-08-16 半导体装置及其制造方法 Expired - Fee Related CN101127345B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006222468A JP2008047732A (ja) 2006-08-17 2006-08-17 半導体装置及びその製造方法
JP222468/06 2006-08-17

Publications (2)

Publication Number Publication Date
CN101127345A true CN101127345A (zh) 2008-02-20
CN101127345B CN101127345B (zh) 2010-08-11

Family

ID=39095322

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200710141086XA Expired - Fee Related CN101127345B (zh) 2006-08-17 2007-08-16 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US7902672B2 (zh)
JP (1) JP2008047732A (zh)
CN (1) CN101127345B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066043A (zh) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 半导体封装件
CN103794513A (zh) * 2012-10-26 2014-05-14 中国科学院上海微系统与信息技术研究所 增强介质层PI和金属Cu层之间粘附性的方法
CN110517966A (zh) * 2019-08-07 2019-11-29 电子科技大学 一种高密度集成电路芯片扇出封装的制作方法
CN110676179A (zh) * 2018-07-02 2020-01-10 台湾积体电路制造股份有限公司 重建晶圆中的跨晶圆rdl和半导体器件的形成方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100159644A1 (en) * 2008-12-19 2010-06-24 Rajiv Carl Dunne Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system
KR102655804B1 (ko) * 2022-05-02 2024-04-09 주식회사 네패스 반도체 패키지

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW556329B (en) * 1999-02-26 2003-10-01 Hitachi Ltd Wiring board, its production method, semiconductor device and its production method
JP2002313696A (ja) 2001-04-13 2002-10-25 Hitachi Ltd パターン形成方法及び半導体集積回路装置の製造方法
JP2003017520A (ja) * 2001-06-28 2003-01-17 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2003124236A (ja) 2001-10-09 2003-04-25 Mitsui Chemicals Inc 接着材料およびそれらを用いたスタックパッケージ
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
JP3611561B2 (ja) * 2002-11-18 2005-01-19 沖電気工業株式会社 半導体装置
JP4547956B2 (ja) 2004-03-24 2010-09-22 ヤマハ株式会社 半導体装置、及び、チップサイズパッケージ
US7262121B2 (en) * 2004-07-29 2007-08-28 Micron Technology, Inc. Integrated circuit and methods of redistributing bondpad locations
JP5129438B2 (ja) 2004-09-28 2013-01-30 ローム株式会社 半導体装置
JP5017872B2 (ja) * 2006-02-06 2012-09-05 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066043A (zh) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 半导体封装件
CN103066043B (zh) * 2011-10-20 2016-05-04 台湾积体电路制造股份有限公司 半导体封装件
CN103794513A (zh) * 2012-10-26 2014-05-14 中国科学院上海微系统与信息技术研究所 增强介质层PI和金属Cu层之间粘附性的方法
CN103794513B (zh) * 2012-10-26 2016-12-21 中国科学院上海微系统与信息技术研究所 增强介质层PI和金属Cu层之间粘附性的方法
CN110676179A (zh) * 2018-07-02 2020-01-10 台湾积体电路制造股份有限公司 重建晶圆中的跨晶圆rdl和半导体器件的形成方法
CN110676179B (zh) * 2018-07-02 2022-03-22 台湾积体电路制造股份有限公司 重建晶圆中的跨晶圆rdl和半导体器件的形成方法
CN110517966A (zh) * 2019-08-07 2019-11-29 电子科技大学 一种高密度集成电路芯片扇出封装的制作方法

Also Published As

Publication number Publication date
US7902672B2 (en) 2011-03-08
US20080284040A1 (en) 2008-11-20
CN101127345B (zh) 2010-08-11
JP2008047732A (ja) 2008-02-28

Similar Documents

Publication Publication Date Title
US6852616B2 (en) Semiconductor device and method for producing the same
US6780673B2 (en) Method of forming a semiconductor device package using a plate layer surrounding contact pads
TWI360204B (en) Semiconductor device
JP2005327984A (ja) 電子部品及び電子部品実装構造の製造方法
CN111433906B (zh) 一种内部电源焊盘间距更小的半导体封装
US7327018B2 (en) Chip package structure, package substrate and manufacturing method thereof
US20080203565A1 (en) Semiconductor device and method of manufacturing the same
JP5567489B2 (ja) アンダーバンプ配線層の方法および装置
KR100368029B1 (ko) 반도체장치
US6596560B1 (en) Method of making wafer level packaging and chip structure
US8330050B2 (en) Wiring board having heat intercepting member
CN101127345B (zh) 半导体装置及其制造方法
WO2010050091A1 (ja) 半導体装置
US9589886B2 (en) Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
US7141885B2 (en) Wafer level package with air pads and manufacturing method thereof
US8723319B2 (en) BGA package structure and method for fabricating the same
US7692287B2 (en) Semiconductor device and wiring board
JP2007173749A (ja) 半導体装置及びその製造方法
JP2006032462A (ja) 配線形成方法
JP4728079B2 (ja) 半導体装置用基板および半導体装置
US9974166B2 (en) Circuit board and manufacturing method thereof
US7910478B2 (en) Method of manufacturing semiconductor devices
JP2010092974A (ja) 半導体装置及びその製造方法、並びに電子装置
JP2004172163A (ja) 半導体装置及びその製造方法
KR101920434B1 (ko) 인쇄회로기판 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100811

Termination date: 20210816

CF01 Termination of patent right due to non-payment of annual fee