TWI404183B - 封裝組合與應用此封裝組合之積體電路裝置 - Google Patents

封裝組合與應用此封裝組合之積體電路裝置 Download PDF

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Publication number
TWI404183B
TWI404183B TW099110782A TW99110782A TWI404183B TW I404183 B TWI404183 B TW I404183B TW 099110782 A TW099110782 A TW 099110782A TW 99110782 A TW99110782 A TW 99110782A TW I404183 B TWI404183 B TW I404183B
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TW
Taiwan
Prior art keywords
height
substrate
gap
solder
connection
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TW099110782A
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English (en)
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TW201112369A (en
Inventor
Wenwei Shen
Chenshien Chen
Chencheng Kuo
Chihhua Chen
Chingwen Hsiao
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Taiwan Semiconductor Mfg
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Publication of TW201112369A publication Critical patent/TW201112369A/zh
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Publication of TWI404183B publication Critical patent/TWI404183B/zh

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Description

封裝組合與應用此封裝組合之積體電路裝置
本發明是有關於一種封裝組合與應用此封裝組合之積體電路裝置。
半導體積體電路(IC)工業經歷了快速的成長。在積體電路技術產生變革的期間，當幾何尺寸(例如：運用一製程可製造獲得的最小元件(或線))變小時，功能密度(例如：每一晶片區域之內連接裝置的數量)一般都會增加。此小型化製程一般係藉由增加生產效率和降低相關的成本來提供益處。此縮小化也增加了IC製造與加工的複雜度，而且為了這些欲實現的發展，在IC加工和製造中需要有類似的發展。
例如，內連接和封裝問題所引起的需求不僅包含對快速且高效率之IC的需求，也包含對同樣高速且可靠之封裝的需求。例示性的晶片封裝系統被稱為”覆晶”技術，一種將IC設置在封裝體上之系統。此系統牽涉到將焊接凸塊置放在晶粒或IC上；翻轉IC；將IC與基材上的接觸墊對準；以及回焊焊球來建立IC和基材間的連接。焊球係做為IC和基板間的內連接體。在習知的內連接幾何中，可觀察到習知內連接幾何展現出凸塊疲勞以及不受歡迎的連接可靠度。因此，出現一種解決這些內連接幾何問題的需求。
本揭露準備了多個實施例。例示性的覆晶封裝組合包含第一基材、第二基材和設置於第一基材與第二基材間的複數個連接結構。每一連接結構包含位於第一基材與第二基材間之內連接柱體以及位於內連接柱體和第二基材間之焊料，其中內連接柱體具有寬度和第一高度。每兩相鄰連接結構之間的距離係以間隙來定義。第一高度係小於間隙的一半。
例示性的積體電路裝置包含包含有接合墊之半導體基材以及形成於半導體基材上方且電性連接至接合墊之凸塊結構，其中每兩相鄰連接結構之間的距離係以間隙來定義。每一凸塊結構包含銅柱，此銅柱具有寬度和高度，其中高度係小於間隙的一半。
本揭露一般係有關於積體電路封裝製程，特別是有關於應用於覆晶封裝製程之內連接結構。
可以理解的是，在本說明中提供了許多不同的實施例或範例，以完成本發明之不同特徵。以下所討論之元件和配置的特定實施例係僅用以簡化本揭露。當然，此些僅為實施例，而並非用以限定本發明之範圍。例如，在說明中提到第一特徵形成在第二特徵之上方或之上時，此說明包含第一特徵與第二特徵直接接觸之實施例，也包含額外特徵形成於第一特徵與第二特徵間之實施例，所以第一特徵與第二特徵係非直接接觸。另外，為了簡化及清楚說明起見，重複使用參考數字及/或符號於本揭露的各實施例中， 然而此重複本身並非規定所討論之各實施例及/或配置之間必須有任何的關聯。
參照第1、2和3A-3B圖，方法100、積體電路裝置200(亦可選擇性地稱為半導體裝置)、凸塊結構300以及封裝基材400係整體敘述如下。可了解到，在方法100之前、之間和之後，可提供額外的步驟，而且以下所描述的一些步驟可因為額外的實施例而被置換或移除。可以理解的是，在積體電路裝置200、凸塊結構300和封裝結構400中，可加入額外的特徵，而且以下所描述的一些特徵可因為積體電路裝置200、凸塊結構300和封裝結構400的額外實施例而被置換或移除。
參照第1圖和第2圖，在方法100的方塊102中，積體電路裝置200，其可被稱為第一基材200，包含基材202。 基材202為包含矽之半導體基材。基材202可選擇性地包含基本半導體，包含結晶矽和/或結晶鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；合金半導體，包含矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化銦鋁(AlInAs)、砷化鋁鎵(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)和/或磷砷化銦鎵(GaInAsP)；或是其組合物。合金半導體基材可具有梯度性的矽鍺特徵，在此梯度性矽鍺特徵中，矽鍺合成物的成分比值係從梯度性矽鍺特徵中的一個位置的值變化至梯度性矽鍺特徵中的另一個位置的值。此合金矽鍺可形成於矽基材上。矽鍺基材可受到應變作用。再者，半導體基材可為絕緣層上覆矽(semiconductor on insulator；SOI)。在一些範例中，半導體基材可包含被摻雜的磊晶層。在其他的範例中，矽基材 可包含多層化合物半導體結構。
基材202可根據本領域公知的設計要求(例如：P形井或N型井)來包含各種不同的摻雜區域。這些摻雜區域係摻雜有P型摻雜物，例如硼或二氟化硼(BF2 )；N型摻雜物，例如：磷或砷；或是其組合物。摻雜區域可以P型井結構、N型井結構；雙井結構或使用成長結構，來直接形成於基材202上。基材202可更包含各種不同的主動區域，例如為N型金屬氧化半導體(NMOS)電晶體裝置所設計的區域以及為P型金屬氧化半導體(PMOS)電晶體裝置設計的區域。
基材202可更包含多個隔離特徵(未繪示)，例如：淺溝渠隔離(shallow trench isolation；STI)特徵或區域性矽氧化(local oxidation of silicon；LOCOS)特徵。隔離特徵可定義及隔離各種不同的微電子元件(未繪示)。可形成於基材202上之各種微電子元件的例子包含電晶體(例如：金屬氧化半導體場效電晶體(metal oxide semiconductor field effect transistors；MOSFET)，互補金屬氧化半導體(complementary metal oxide semiconductor；CMOS)電晶體，雙載子接面電晶體(bipolar junction transistors；BJT)、高電壓電晶體、高頻率電晶體、P通道和/或n通道場效電晶體；電阻；二極體；電容；電感；保險絲以及其他合適的元件。執行各種不同的製程來形成各種不同的微電子元件，這些製程包含沉積、蝕刻、植入、微影、退火以及其他合適的製程。微電子元件彼此互相內連接來形成積體電路裝置，例如：邏輯裝置、記憶體裝置(例如：SRAM)、RF裝置、輸入/輸出裝置(I/O)、系統單晶片(system-on-chip；SOC)、上述裝置 之組合物以及其他合適類型的裝置。
積體電路裝置200可更包含形成於基材202上之內連接結構。例如，此內連接結構可包含內層界電(inter-layer dielectric；ILD)層、內金屬界電(inter-metal dielectric；IMD)層和金屬化層。內連接結構中的內層界電層和內層金屬界電層包含低介電常數(low-k)材料、未摻雜矽玻璃(un-doped silicate glass；USG)、氮化矽、氮氧化矽或其他合適的材料。低介電常數材料的介電常數(k值)可實質小於3.9或實質小於2.8。金屬化層可形成金屬線於內連接結構中，此內連接結構可用銅或銅合金來形成。本領域習知技藝者可了解內連接結構的詳細資訊。
積體電路裝置200更包含接合墊204。接合墊204為形成於上層內層介電層中的上部金屬化層，此上部金屬化層為導線的一部份且具有露出之表面，此露出表面如果有必要，可以平坦化製程，例如：化學機械研磨(chemical mechanical polishing；CMP)，來處理。用於接合墊204的合適材料包含如銅、鋁、銅合金、移動導電材料，但不受限於此，然而接合墊204也可包含其他材料，例如：銅、銀、金、鎳、鎢、上述材料之合金和/或上述材料的多層結構，或利用這些材料來形成。接合墊204的外形可具有任何合適的步進高度，以實現適合的接合特性。提供鈍化層206於基材202上，並圖案化來露出接合墊204的一部份。鈍化層206可用無機材料來形成，這些無機材料係選自未摻雜矽玻璃、氮化矽、氮氧化矽、氧化矽及其組合物。鈍化層206可選擇性地以聚合物層來形成，此聚合物層可例如為環氧化物、聚亞醯胺、苯環丁烯(BCB)、聚苯噁唑(PBO) 或諸如此類的材料。其他相對較軟的介電材料(通常是有機的)也可以被使用。
在方塊104中，凸塊結構300係形成於積體電路裝置200上。如第2圖所繪示，凸塊結構300係形成於接合墊204的露出部份上。凸塊結構300為覆晶組合結構，其可將面朝下之積體電路裝置(例如：積體電路裝置200)的直接電性連接提供至另一基材上，此另一基材係例如板或電路板(PCB)。在本實施例中，凸塊結構300包含可利用任何合適製程來形成的底層凸塊金屬化(under bump metallization；UBM)層302、內連接柱體304以及焊料層306a。
底層凸塊金屬化層302係形成於鈍化層206和接合墊204的露出部份上。在一實施例中，底層凸塊金屬化層302包含擴散阻障層和/或種子層。擴散阻障層也可稱為黏著層。雖然擴散阻障層可利用鈦來形成，但擴散阻障層亦可利用其他材料，例如氮化鈦、鉭、氮化鉭或諸如此類的材料。形成的方法包含物理氣相沉積(physical vapor deposition；PVD)或濺鍍。種子層可為利用物理氣相沉積或濺鍍來形成於擴散阻障層上之銅種子層。種子層可利用包含銀、鉻、鎳、錫、金或其組合物之銅合金來形成。在一實施例中，底層凸塊金屬化層302為銅/鈦層。
類似地，內連接柱體304和焊料306可包含任何適合的材料。在本例中，內連接柱體304為金屬柱體，此金屬柱體可利用具有焊接濕潤性(solder wettability)的習知材料來形成。例如，內連接柱體304係由銅形成，此內連接柱體304被稱為銅柱(或銅凸塊)。焊料層306a係形成於內連 接柱體304上。焊料層306a可包含錫(Sn)、錫銀(SnAg)、錫鉛(Sn-Pb)、錫銀鋅(SnAgZn)、錫鋅(SnZn)、錫鉍銦(SnBi-In)、錫銦(Sn-In)、錫金(Sn-Au)、錫銅(SnCu)，錫鋅銦(SnZnIn)或錫銀銻(SnAgSb)等。
參照第1圖和第3A-3B圖，在方塊106中，凸塊結構係耦接至第二基材，並形成連接結構於第一基材和第二基材之間。更明確地來說，凸塊結構300係耦接至第二基材400，並形成連接結構308於積體電路裝置200(也被稱為第一基材)和第二基材400。如圖所示，上方形成有凸塊結構300之積體電路裝置(第一基材)200被由上往下翻覆，並使第一基材200與第二基材400接觸。第二基材400可為封裝基材、板材(例如：印刷電路板)或其他合適的基材。
凸塊結構300係利用形成連接結構308於第一基材200和第二基材400間之各種不同導電接點，來與第二基材400接觸，例如，位於接觸墊和/或導電路徑上之另一焊料層306b。當凸塊結構300耦接至第二基材400時，連接在一起的焊料層306a和306b可被稱為連接焊料306。例示性的耦接製程包含焊劑施加、晶片配置、晶片接點回焊以及殘餘焊劑清除。積體電路裝置(第一基材)200、連接結構308和第二基材400可被稱為封裝組合結構，在本實施例中，或可稱為覆晶封裝組合結構。
第3圖標示了多種尺寸/特徵來定義封裝組合結構之幾何，特別是凸塊結構300和連接結構308之幾何。連接結構308包含內連接柱體304以及焊料層306a和306b(被稱為焊料層306)。前述之尺寸/特徵包含連接結構308之高度HJ 、內連接柱體304之高度HPost 、內連接柱體304之寬度 WPost 和連接焊料306之高度HS 。這些尺寸/特徵更包含用以定義第一連接結構308和第二連接結構308間距離之間隙(或凸塊間隙)。在本實施例中，間隙寬度係由連接結構之中心開始量測，然而，其他的設定也可以考慮，例如，由連接結構之末端開始量測。連接結構308可具有任何合適的連接結構高度HJ 、內連接柱體高度HPost 、內連接柱體寬度WPost 以及連接焊料高度HS 。
在習知的連接結構中，可觀察到習知連接結構展現了凸塊疲勞，特別是當連接結構之高度太高時。因此，本實施例展示出可提供較佳連接可靠度以及可減輕凸塊疲勞之尺寸/特徵。例如，內連接柱體高度HPost 與間隙之間的關係可用下式來表示：內連接柱體高度<0.5×間隙
確定內連接柱體高度小於間隙的一半，可提供較佳的連接可靠度以及減輕凸塊疲勞。內連接柱體高度HPost 可以下式來進一步定義：0.21×間隙<內連接柱體高度HPost <0.24×間隙因此，內連接柱體高度與間隙之比值可介於0.24和0.21之間。
再者，幾何規格包含內連接柱體寬度WPost 和間隙，而內連接柱體寬度WPost 和間隙彼此之間的關係可用下列關係式來表示：內連接柱體寬度>0.6×間隙
連接結構308之連接焊料高度HS 和連接結構高度HJ 也可調整，其中連接結構高度和連接焊料高度之比值如下：連接結構高度/連接焊料高度>0.44
例示性的連接結構幾何包含範圍實質介於120μm至180μm之間的間隙；範圍實質介於30μm至90μm之間的連接結構高度HJ ；範圍實質介於30μm至50μm之間的內連接柱體高度HPost ；範圍實質介於40μm至60μm之間的連接焊料高度HS ；以及範圍實質介於60μm至100μm之間的內連接柱體寬度WPost 。內連接柱體高度HPost 、連接結構高度HJ 和連接焊料高度HS 可選擇性地被稱為第一高度、第二高度和第三高度。例示性的連接結構幾何有益地增加連接可靠度和減輕凸塊疲勞問題。可以理解的是，不同的實施例可以有不同的優點，而且沒有一個特定的優點是所有實施例都必須具備的。
雖然本發明已以數個實施例揭露如上，然其並非用以限定本發明，在本發明所屬技術領域中任何具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧方法
102‧‧‧方塊
104‧‧‧方塊
106‧‧‧方塊
200‧‧‧積體電路裝置
202‧‧‧基材
204‧‧‧接合墊
206‧‧‧鈍化層
300‧‧‧凸塊結構
302‧‧‧底層凸塊金屬化層
304‧‧‧內連接柱體
306‧‧‧焊料
306a‧‧‧焊料層
306b‧‧‧焊料層
308‧‧‧連接結構
400‧‧‧第二基材
HJ ‧‧‧連接結構高度
HPost ‧‧‧內連接柱體高度
HS ‧‧‧連接焊料高度
WPost ‧‧‧內連接柱體寬度
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，上文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：第1圖係繪示根據本揭露之一方面之用以封裝積體電路裝置之方法的流程示意圖。
第2圖係繪示根據本揭露之一方面之上方設置有凸塊結構之積體電路裝置之實施例的剖面示意圖。
第3A-3B圖係繪示根據第1圖之方法之積體電路裝置封裝製程之實施例的各種不同剖面示意圖。
200‧‧‧積體電路裝置
302‧‧‧底層凸塊金屬化層
304‧‧‧內連接柱體
306‧‧‧焊料
308‧‧‧連接結構
400‧‧‧第二基材
HPost ‧‧‧內連接柱體高度
HJ ‧‧‧連接結構高度
WPost ‧‧‧內連接柱體寬度
HS ‧‧‧連接焊料高度

Claims (10)

  1. 一種覆晶封裝組合，包含：一第一基材；一第二基材；以及複數個連接結構，設置於該第一基材和該第二基材之間，其中每兩相鄰之該些連接結構之間的距離係以一間隙(pitch)來定義；其中每一該些連接結構包含位於該第一基材與該第二基材間之一內連接柱體以及位於該內連接柱體與該第二基材間之一連接焊料；其中該內連接柱體具有一寬度和一第一高度，該連接結構具有一第二高度，而該連接焊料具有一第三高度，該第一高度大於該第三高度；其中該第一高度與該間隙彼此之間的關係以下列關係式來表示：該第一高度<0.5×該間隙。
  2. 如申請專利範圍第1項所述之覆晶封裝組合，其中該寬度與該間隙彼此之間的關係係以下列關係式來表示：該寬度>0.6×該間隙。
  3. 如申請專利範圍第2項所述之覆晶封裝組合，其中該第一高度與該間隙彼此之間的關係式係以下列關係式來表示： 0.21×該間隙<該第一高度<0.24×該間隙。
  4. 如申請專利範圍第1項所述之覆晶封裝組合，其中該第二高度和該第三高度之一比值係以下式來表示：該第三高度/該第二高度>0.44。
  5. 一種積體電路，包含：一第一半導體基材，包含複數個接合墊；一第二半導體基材；以及複數個凸塊結構，形成於該半導體基材上方並電性連接至該些接合墊，其中每兩相鄰之該些凸塊結構之間的距離係以一間隙來定義；其中，每一該些凸塊結構包含一銅柱以及一連接焊料，該銅柱具有一寬度和一第一高度，且該第一高度小於該間隙的一半，其中，每一該些凸塊結構具有自該第一半導體基材延伸至該第二半導體基材之一第二高度，其中，該連接焊料具有一第三高度，且該第一高度大於該第三高度。
  6. 如申請專利範圍第5項所述之積體電路，其中該寬度與該間隙之比值係大於0.6。
  7. 如申請專利範圍第5項所述之積體電路，其中該第一高度與該間隙之比值係介於0.24和0.21之間。
  8. 一種封裝組合，包含：一第一基材和一第二基材；以及複數個連接結構，耦接於該第一基材和該第二基材之間，該些連接結構包含一內連接柱體和一連接焊料，其中每兩相鄰之該些連接結構之間的距離係以一間隙來定義；其中，該連接結構具有一第一高度，該內連接柱體具有一第二高度，而該焊料具有一第三高度，該第二高度係小於該間隙的一半，該第二高度大於該第三高度。
  9. 如申請專利範圍第8項所述之封裝組合，其中該第三高度和該第一高度之比值係大於0.44。
  10. 如申請專利範圍第8項所述之封裝組合，其中該第二高度和該間隙之比值的範圍係實質介於0.21至0.24之間。
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