TW202101616A - 晶片封裝結構形成方法 - Google Patents

晶片封裝結構形成方法 Download PDF

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TW202101616A
TW202101616A TW109107598A TW109107598A TW202101616A TW 202101616 A TW202101616 A TW 202101616A TW 109107598 A TW109107598 A TW 109107598A TW 109107598 A TW109107598 A TW 109107598A TW 202101616 A TW202101616 A TW 202101616A
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Taiwan
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layer
conductive
insulating layer
opening
substrate
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TW109107598A
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English (en)
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李苓瑋
張容華
黃震麟
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台灣積體電路製造股份有限公司
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Publication of TW202101616A publication Critical patent/TW202101616A/zh

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Abstract

本揭露實施例提供一種晶片封裝結構形成方法。此方法包括在第一基板中形成導孔結構。此方法包括將晶片接合到第一基板的第一表面。此方法包括在第一基板的第二表面上方形成阻障層。此方法包括在阻障層上方形成第一絕緣層。此方法包括在第一絕緣層上方以及在第一開口、第二開口、第三開口中形成導電墊。導電墊從導孔結構連續地延伸到第三開口中。此方法包括在第三開口中的導電墊上方形成導電凸塊。

Description

晶片封裝結構形成方法
本揭露實施例關於一種晶片封裝結構形成方法。
在各種電子應用，例如個人電腦、手機、數位相機和其他電子裝置中使用了半導體裝置。通常係藉由在半導體基板上依序沉積絕緣層或介電層、導電層和半導體層，並使用微影製程來圖案化各種材料層，以在材料層上形成電路部件和元件來製造半導體裝置。
通常會在單個半導體晶圓上製造出數十個或數百個積體電路。藉由沿著切割道鋸切積體電路以單粒化晶粒。然後將各個晶粒分開封裝以形成封裝體。每個封裝體被接合到基板上。在接合製程中，封裝體和基板之間的接合應力會降低接合製程的良率。因此，提高接合製程的良率是一種挑戰。
根據一些實施例，本揭露提供一種晶片封裝結構形成方法。此方法包括在第一基板中形成導孔結構。此方法包括將晶片接合到第一基板的第一表面。此方法包括在第一基板的第二表面上方形成阻障層。阻障層直接接觸第一基板，且阻障層具有露出導孔結構的第一開口。此方法包括在阻障層上方形成第一絕緣層。第一絕緣層具有第二開口以及第三開口，第二開口位在第一開口上方並且露出導孔結構，第三開口部分地露出阻障層，且阻障層比第一絕緣層薄。此方法包括在第一絕緣層上方以及在第一開口、第二開口、第三開口中形成導電墊。導電墊從導孔結構連續地延伸到第三開口中。此方法包括在第三開口中的導電墊上方形成導電凸塊。
根據一些實施例，本揭露提供一種晶片封裝結構形成方法。此方法包括在基板中形成導孔結構。此方法包括將晶片接合基板的第一表面。此方法包括在基板的第二表面上方形成阻障層，阻障層直接接觸基板。此方法包括形成部分地位在阻障層上方的第一絕緣層。此方法包括在第一絕緣層上方形成導電墊，導電墊具有第一部份以及第二部分，第一部分穿過阻障層以及第一絕緣層以連接到導孔結構，且第二部分穿過第一絕緣層並直接接觸阻障層。此方法包括在第一絕緣層以及導電墊上方形成第二絕緣層。此方法包括在第二絕緣層上方形成導電凸塊，導電凸塊的第一底部穿過第二絕緣層，以連接導電墊的第二部分。
根據一些實施例，本揭露提供一種晶片封裝結構。此晶片封裝結構包括第一基板。此晶片封裝結構包括導孔結構，穿過第一基板。此晶片封裝結構包括晶片，位在第一基板的第一表面上方。此晶片封裝結構包括阻障層，位在第一基板的第二表面上方，阻障層直接接觸第一基板。此晶片封裝結構包括第一絕緣層，位在阻障層上方。此晶片封裝結構包括導電墊，位在第一絕緣層上方，導電墊具有第一部分以及第二部分，第一部分穿過阻障層以及第一絕緣層以連接導孔結構，且第二部分穿過第一絕緣層並直接接觸阻障層。此晶片封裝結構包括導電凸塊，位在導電墊的第二部分上方。
以下公開許多不同的實施方法或是範例來實行所提供之標的之不同特徵，以下描述具體的元件及其排列的實施例以闡述本揭露。當然這些實施例僅用以例示，且不該以此限定本揭露的範圍。舉例來說，在說明書中提到第一特徵部件形成於第二特徵部件之上，其包括第一特徵部件與第二特徵部件是直接接觸的實施例，另外也包括於第一特徵部件與第二特徵部件之間另外有其他特徵的實施例，亦即，第一特徵部件與第二特徵部件並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關用詞，例如“在下方”、“下方”、＂下＂、＂上方＂、＂上＂及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞旨在涵蓋包括特徵的裝置的不同方向。當設備被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。應理解的是，可以在上述方法前、中、後提供額外的操作，並且對於上述方法的其他實施例來說，可以取代或去除所描述的一些操作。
以下對本揭露的一些實施例進行描述。可以在所述實施例中描述的階段之前、之中及/或之後提供額外的操作。對於不同的實施例，可以更換或去除所述的某些階段。可以在半導體裝置結構中增加額外的特徵。對於不同的實施例，可以更換或去除以下描述的某些功能。儘管藉由使用特定順序來執行的操作以討論一些實施例，但是可以藉由其他的邏輯順序來執行所述操作。
根據一些實施例，第1A圖至第1H圖是用於形成晶片封裝結構的製程的各個階段的剖面圖。根據一些實施例，如第1A圖所示，提供了基板110。在一些實施例中，基板110是中置(interposer)晶圓。根據一些實施例，基板110包括半導體基板111、導孔結構112、阻障層113和重分佈結構114。
根據一些實施例，半導體基板111具有表面111a和111b。在一些實施例中，半導體基板111由包括單晶、多晶或非晶結構的矽或鍺的元素半導體材料製成。
在一些其他實施例中，半導體基板111由化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦或砷化銦)、合金半導體(例如SiGe或GaAsP)、或其組合所形成。半導體基板111還可包括多層半導體(multi-layer semiconductors)、絕緣體上半導體(semiconductor on insulator ，SOI)(例如絕緣體上矽或絕緣體上鍺)、或其組合。
根據一些實施例，導孔結構112形成在半導體基板111中。導孔結構112可以從表面111a延伸到半導體基板111中。根據一些實施例，阻障層113形成在半導體基板111上方。根據一些實施例，阻障層113位在導孔結構112和半導體基板111之間。
根據一些實施例，阻障層113配置成防止導孔結構112的材料擴散到半導體基板111中。根據一些實施例，阻障層113進一步配置成使導孔結構112與半導體基板111電性絕緣。
根據一些實施例，阻障層113係由如氮化矽、氧化矽、氮氧化矽、碳化矽等的含矽材料或其組合所製成。在一些其他實施例中，阻障層113係由磷矽酸鹽玻璃(phosphosilicate glass ，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、四乙氧基矽烷(tetraethyl orthosilicate，TEOS)等所製成。
阻障層113係使用氧化製程、沉積製程、旋轉塗佈製程或其他合適的製程來形成。根據一些實施例，所述沉積製程包括化學氣相沉積(chemical vapor deposition，CVD)製程，例如可流動化學氣相沉積(flowable chemical vapor deposition，FCVD)製程、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)製程、低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)製程等。
在一些實施例中，基板110是包括各種裝置元件的裝置晶圓。在一些實施例中，各種裝置元件形成在半導體基板111內及/或上方。為了簡單和清楚起見，未在圖中示出裝置元件。各種裝置元件的範例包括主動裝置、被動裝置、其他合適的元件或其組合。主動裝置可以包括形成在表面111a處的電晶體或二極體(未示出)。被動裝置包括電阻、電容或其他合適的被動裝置。
舉例來說，電晶體可為金氧半場效電晶體(metal oxide semiconductor field effect transistors，MOSFET)、互補金氧半(complementary metal oxide semiconductor，CMOS)電晶體、雙極性接面型電晶體(bipolar junction transistors，BJT)、高壓電晶體(high-voltage transistors)、高頻電晶體(high-frequency transistors)、p通道及/或n通道場效電晶體(p-channel and/or n-channel field effect transistor，PFETs/NFETs)等。執行各種製程以形成各種裝置元件，例如前端生產線(front-end-of-line，FEOL)半導體製程。前端生產線半導體製造製程可包括沉積、蝕刻、佈植、微影、退火、平坦化、一或多種其他合適的製程、或其組合。
在一些實施例中，在半導體基板111中形成隔離特徵(未示出)。隔離特徵用於定義主動區域，並且電性隔離形成在主動區域中的各種裝置元件。在一些實施例中，隔離特徵包括淺溝槽隔離(shallow trench isolation，STI)特徵、局部氧化矽(local oxidation of silicon，LOCOS)特徵、其他合適的隔離特徵、或其組合。
根據一些實施例，重分佈結構114形成在半導體基板111上方。根據一些實施例，重分佈結構114包括絕緣層114a、線路層114b、導孔114c、和導電墊114d。根據一些實施例，絕緣層114a形成在表面111a上方。根據一些實施例，線路層114b形成在絕緣層114a中。
根據一些實施例，如第1A圖所示，導孔114c在不同的線路層114b之間、以及在線路層114b和導電墊114d之間提供電性連接。為了簡單起見，根據一些實施例，第1A圖僅示出一層線路層114b。
根據一些實施例，導孔結構112藉由線路層114b和導孔114c與導電墊114d電性連接。根據一些實施例，導電墊114d形成在絕緣層114a上方。根據一些實施例，係由如銅(Cu)、鋁(Al)、鎢(W)、鈷(Co)、鎳(Ni)或其他合適的材料形成導孔結構112、線路層114b、導孔114c、和導電墊114d。
根據一些實施例，如第1A圖所示，分別在各個導電墊114d上方形成導電凸塊115。根據一些實施例，由導電材料形成導電凸塊115，例如銅(Cu)、鋁(Al)、鎢(W)、鈷(Co)、鎳(Ni)或其他合適的材料。根據一些實施例，如第1A圖所示，分別在各個導電凸塊115上方形成焊接層116。根據一些實施例，由導電材料形成焊接層116，例如錫(Sn)或其他合適的材料。
根據一些實施例，如第1A圖所示，提供了晶片120。根據一些實施例，晶片120包括晶片上系統(system on chip，SoC)。根據一些實施例，晶片120包括各種裝置元件。在一些實施例中，各種裝置元件形成在晶片120中。
為了簡單和清楚起見，並未在圖中繪示出裝置元件。各種裝置元件的範例包括主動裝置、被動裝置、其他合適的元件、或其組合。主動裝置可以包括形成在表面111a的電晶體或二極體(未示出)。被動裝置包括電阻、電容、或其他合適的被動裝置。
舉例來說，電晶體可為金氧半場效電晶體(metal oxide semiconductor field effect transistors，MOSFET)、互補金氧半(complementary metal oxide semiconductor，CMOS)電晶體、雙極性接面型電晶體(bipolar junction transistors，BJT)、高壓電晶體(high-voltage transistors)、高頻電晶體(high-frequency transistors)、p通道及/或n通道場效電晶體(p-channel and/or n-channel field effect transistor，PFETs/NFETs)等。執行各種製程以形成各種裝置元件，例如前端生產線(front-end-of-line，FEOL)半導體製程。前端生產線半導體製造製程可包括沉積、蝕刻、佈植、微影、退火、平坦化、一或多種其他合適的製程、或其組合。
在一些實施例中，隔離特徵(未示出)形成在晶片120中。隔離特徵用於定義主動區域，並且電性隔離形成在主動區域中的各種裝置元件。在一些實施例中，隔離特徵包括淺溝槽隔離(shallow trench isolation，STI)特徵、局部氧化矽(local oxidation of silicon，LOCOS)特徵、其他合適的隔離特徵、或其組合。
根據一些實施例，如第1A圖所示，導電凸塊132形成在晶圓120上方。根據一些實施例，如第1A圖所示，分別在各個導電凸塊132上方形成焊接層134。根據一些實施例，由導電材料形成焊接層134，例如錫(Sn)或其他合適的材料。
根據一些實施例，如第1A圖和第1B圖所示，晶片120設置在基板110上。此後，根據一些實施例，在焊接層134和116上執行回流(reflow)製程。根據一些實施例，在回流製程之後，每層焊接層134和在焊接層134下方的焊接層116熔化並混合在一起，以形成焊球136。因此，根據一些實施例，晶片120藉由導電凸塊132和115以及焊球136結合到基板110。
根據一些實施例，如第1B圖所示，在基板110和晶片120之間的間隙G1中形成底部填充層140。根據一些實施例，底部填充層140圍繞導電凸塊132和115、焊球136、和晶片120。根據一些實施例，底部填充層140包括聚合物材料(例如模封化合物材料(molding compound material)、環氧樹脂(epoxy)、或樹脂(resin))。
根據一些實施例，如第1B圖所示，在基板110上形成模封層150。根據一些實施例，模封層150圍繞晶片120、底部填充層140、導電凸塊132和115、以及焊球136。根據一些實施例，模封層150包括聚合物材料(例如模封化合物材料、環氧樹脂、或樹脂)。根據一些實施例，形成模封層150的步驟包括在基板110、底部填充層140、和晶片120上形成模封材料層，以及在模封材料層上執行平坦化製程，以去除模封材料層的上部直到露出晶片120的頂表面122。根據一些實施例，晶片120的頂表面122和模封層150的頂表面152實質上共平面。
根據一些實施例，如第1C圖所示，去除了半導體基板111的下部。根據一些實施例，去除製程包括化學機械研磨(chemical mechanical polishing，CMP)製程。根據一些實施例，在去除製程之後露出導孔結構112和阻障層113。
根據一些實施例，導孔結構112和阻障層113穿過半導體基板111。根據一些實施例，當半導體基板111是矽基板時，導孔結構112也被稱為基板穿孔(through-substrate vias)或矽穿孔(through-silicon vias，TSV)。
根據一些實施例，如第1D圖所示，上下翻轉半導體基板111。根據一些實施例，如第1D圖所示，在表面111b上方形成阻障層117。根據一些實施例，阻障層117配置成防止隨後形成在阻障層117上方的線路層的材料擴散到半導體基板111中。根據一些實施例，阻障層117進一步配置成電性絕緣隨後形成在阻障層117上方的線路層與半導體基板111。
根據一些實施例，阻障層117直接接觸半導體基板111。根據一些實施例，阻障層117具有開口117a。根據一些實施例，各個開口117a分別露出下方的導孔結構112。
根據一些實施例，阻障層117係由如氮化矽、氧化矽、氮氧化矽、碳化矽等的含矽材料或其組合所製成。在一些其他實施例中，阻障層113係由磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、氟摻雜矽酸鹽玻璃(FSG)、四乙氧基矽烷(TEOS)等所製成。
阻障層117係使用氧化製程、沉積製程、旋轉塗佈製程或其他合適的製程來形成。根據一些實施例，所述沉積製程包括化學氣相沉積(CVD)製程，例如可流動化學氣相沉積(FCVD)製程、電漿增強化學氣相沉積(PECVD)製程、低壓化學氣相沉積(LPCVD)製程等。根據一些實施例，使用微影製程和蝕刻製程形成開口117a。
根據一些實施例，第1E-1圖是第1E圖的晶片封裝結構的俯視圖。根據一些實施例，第1E圖是沿著第1E-1圖中的剖面線I-I’繪示的晶片封裝結構的剖面圖。
根據一些實施例，如第1E圖和第1E-1圖所示，在阻障層117上方形成絕緣層118。根據一些實施例，絕緣層118具有開口118a和118b。根據一些實施例，各個開口118a分別位在開口117a上方。
根據一些實施例，各個開口118a分別與下方的開口117a連接。根據一些實施例，開口118a分別露出下方的導孔結構112。根據一些實施例，開口118a進一步露出圍繞導孔結構112的阻障層117。
根據一些實施例，開口118b部分地露出接近導孔結構112的阻障層117。根據一些實施例，絕緣層118部分地位在開口118a和118b之間。根據一些實施例，阻障層117比絕緣層118更薄。根據一些實施例，阻障層117的硬度大於絕緣層118的硬度。
根據一些實施例，絕緣層118由如環氧樹脂、聚醯亞胺、聚苯並噁唑(polybenzoxazole，PBO)、阻焊劑(solder resist，SR)、ABF膜等的聚合物材料製成。在一些實施例中，由光敏感材料形成絕緣層118，並且當曝光時可發生化學反應。
在一些實施例中，由不同的材料形成阻障層117和絕緣層118。根據一些實施例，使用塗佈製程、層壓製程、化學氣相沉積製程等、或其組合來形成絕緣層118。根據一些實施例，使用微影製程和蝕刻製程來形成開口118a和118b。
此後，根據一些實施例，如第1E圖所示，在阻障層117、絕緣層118和導孔結構112上方形成晶種層162。根據一些實施例，晶種層162共形地(conformally)覆蓋阻障層117、絕緣層118、以及導孔結構112。
根據一些實施例，晶種層162直接接觸阻障層117、絕緣層118、以及導孔結構112。根據一些實施例，晶種層162的材料包括鈦、銅等。根據一些實施例，使用物理氣相沉積(PVD)製程形成晶種層162，例如濺鍍製程。
此後，根據一些實施例，如第1E圖和第1E-1圖所示，在晶種層162上方形成遮罩層164。根據一些實施例，遮罩層164具有開口164a。根據一些實施例，每個開口164a露出一部分在開口117a、118a、和118b中的晶種層162。根據一些實施例，由如光阻材料的聚合物材料形成遮罩層164。
此後，根據一些實施例，如第1E圖和第1E-1圖所示，在開口164a中形成導電層166。根據一些實施例，導電層166共形地覆蓋由開口164a露出的晶種層162。根據一些實施例，導電層166比晶種層162厚。根據一些實施例，各個導電層166部分地位在下方的開口117a、118a、和118b中。
根據一些實施例，由如銅、鋁、鎳、鎢、鈦等的金屬材料或其組合形成導電層166。根據一些實施例，使用電鍍(electroplating)製程、無電鍍層(electroless plating)製程等形成導電層166。
此後，根據一些實施例，如第1E圖和第1F圖所示，去除遮罩層164。根據一些實施例，去除製程包括灰化製程及/或清洗製程。此後，根據一些實施例，如第1F圖所示，去除原先位在遮罩層164下方的晶種層162。根據一些實施例，去除製程包括蝕刻製程，如濕蝕刻製程或乾蝕刻製程。
根據一些實施例，如第1F圖所示，在去除最初在遮罩層164下方的晶種層162之後，每個導電層166以及保留在導電層166下方的晶種層162一起形成導電墊167。根據一些實施例，每個導電墊167從下方的導孔結構112(或開口117a)連續地延伸至下方的開口118b。根據一些實施例，如第1F圖所示，導電墊167具有類似W字形的形狀。
根據一些實施例，每個導電墊167具有第一部分167a和第二部分167b。根據一些實施例，第一部分167a穿過阻障層117和絕緣層118以與下方的導孔結構112連接。根據一些實施例，第二部分167b穿過絕緣層118。
根據一些實施例，第二部分167b直接接觸阻障層117。根據一些實施例，絕緣層118部分地位在第一部分167a和第二部分167b之間。根據一些實施例，絕緣層118分隔第一部分167a與第二部分167b。
此後，根據一些實施例，如第1F圖所示，在導電墊167和絕緣層118上方形成遮罩層170。根據一些實施例，遮罩層170直接接觸導電墊167和絕緣層118。
根據一些實施例，遮罩層170具有使用適當的微影和蝕刻製程所形成的開口172。根據一些實施例，每個開口172部分地露出開口118b中的導電墊167(或導電層166)。根據一些實施例，由聚合物材料形成遮罩層170，例如光阻材料。
此後，根據一些實施例，如第1F圖所示，在各個開口172中分別形成導電凸塊180。根據一些實施例，導電凸塊180直接位在開口118b上方。根據一些實施例，導電凸塊180直接位在導電墊167的第二部分167b上方。根據一些實施例，即在導電凸塊180與導電墊167(或導電層166)之間不存在晶種層。根據一些實施例，導電凸塊180藉由下方的導電墊167電性連接到導孔結構112。
根據一些實施例，導電凸塊180比導電墊167厚。根據一些實施例，導電凸塊180與導電墊167(或導電層166)直接接觸。在一些實施例中，導電凸塊180的底部182位在開口118b中。
根據一些實施例，在垂直於表面111b的垂直方向V1上，導電凸塊180和導孔結構112錯位。因此，根據一些實施例，在隨後的接合製程期間，集中在導電凸塊180上的接合應力不傳遞至導孔結構112。根據一些實施例，因此避免了導孔結構112被接合應力損壞。
根據一些實施例，由如銅(Cu)、鋁(Al)、鎢(W)、鈷(Co)、或鎳(Ni)的導電材料製成導電凸塊180。根據一些實施例，導電凸塊包括受控塌陷晶片連接(controlled collapse chip connector，C4)銅柱凸塊。根據一些實施例，使用如電鍍製程的鍍層製程來形成導電凸塊180。
此後，根據一些實施例，如第1F圖所示，分別在各個導電凸塊180上方形成焊接層190。根據一些實施例，由錫(Sn)、無鉛焊料、或熔點低於導電凸塊180的熔點的其他合適的導電材料來形成焊接層190。根據一些實施例，使用如電鍍製程的鍍層製程來形成焊接層190。
根據一些實施例，第1G-1圖是第1G圖的晶片封裝結構的俯視圖。根據一些實施例，第1G圖是沿著第1G-1圖中的剖面線I-I’繪示的晶片封裝結構100的剖面圖。根據一些實施例，如第1G圖和第1G-1圖所示，去除遮罩層170。根據一些實施例，去除製程包括灰化製程及/或清洗製程。
此後，根據一些實施例，如第1F圖和第1G圖所示，在焊接層190上執行回流製程，以將焊接層190轉換成焊球190a。如第1G圖所示，根據一些實施例，進行切割製程以沿著預定的切割道SC切割基板110和模封層150，進而形成晶片封裝結構100。為了簡單起見，第1G-1圖僅顯示了晶片封裝結構100之一者。
根據一些實施例，如第1G圖所示，導電凸塊180與導電墊167之間的接觸面積大於導電凸塊180的頂表面180a的面積。根據一些實施例，如第1G-1圖所示，導電墊167的寬度W1大於導電凸塊180的寬度W2、導孔結構112的寬度W3、以及導電凸塊180和導孔結構112之間的距離D之總和。
根據一些實施例，如第1H圖所示，將晶片封裝結構100上下顛倒。如第1H圖所示，根據一些實施例，晶片封裝結構100藉由焊球190a接合到基板210。
根據一些實施例，在接合製程期間，晶片封裝結構100和基板210之間的接合應力傾向於集中在導電凸塊180上。如果導電層118將導電凸塊180下方的導電墊167與阻障層117完全分開，則集中在導電凸塊180上的接合應力可能會傳遞至絕緣層118，並且可能會損壞絕緣層118，這可能會降低接合製程的良率。
根據一些實施例，由於在導電凸塊180下方的導電墊167直接接觸阻障層117，因此集中在導電凸塊180上的接合應力被直接傳遞至阻障層117和半導體基板111。根據一些實施例，因此防止了集中在導電凸塊180上的接合應力損壞絕緣層118。根據一些實施例，由於阻障層117比絕緣層118更硬且更薄，所以阻障層117能夠承受集中在導電凸塊180上的接合應力。根據一些實施例，因此提高了接合製程的良率。
此外，根據一些實施例，由於導電凸塊180形成在穿過絕緣層118的導電墊167上方，所以導電凸塊180的共面性(coplanarity)不被絕緣層118的共面性影響。因此，根據一些實施例，改善了導電凸塊180的共面性。因此，根據一些實施例，提高了接合製程的良率。
在一些實施例中，開口118a的寬度Wl與導電凸塊180的寬度W2之比值介於大約0.3至大約1的範圍內。在一些實施例中，開口118a的寬度Wl與導電凸塊180的寬度W2之比值介於大約0.3至大約0.8的範圍內。如果開口118a的寬度W1與導電凸塊180的寬度W2之比值小於0.3，則接合製程的良率稍微提升或未提升。
根據一些實施例，基板210包括絕緣層212、線路層214、導孔216、和導電墊218。根據一些實施例，線路層214形成在絕緣層212中。根據一些實施例，導電墊218形成在絕緣層212上方。根據一些實施例，導孔216在不同的線路層214之間以及在線路層214和導電墊218之間提供電性連接。
根據一些實施例，如第1H圖所示，在基板110和210之間形成底部填充層220。在一些實施例中，底部填充層220的一部分形成在基板210上方並圍繞晶片封裝結構100。根據一些實施例，由如聚合物材料的絕緣材料形成底部填充層220。根據一些實施例，在此步驟中實質上形成了晶片封裝結構200。
根據一些實施例，第2圖是晶片封裝結構的剖面圖。根據一些實施例，如第2圖所示，在第1F圖的步驟之後，去除遮罩層170，然後在絕緣層118和導電墊167上方形成絕緣層230。
根據一些實施例，絕緣層230覆蓋導電墊167未被導電凸塊180覆蓋的部分。根據一些實施例，即絕緣層230不與導電凸塊180垂直地重疊。根據一些實施例，絕緣層230圍繞導電凸塊180。
根據一些實施例，絕緣層230由如環氧樹脂、聚醯亞胺、聚苯並噁唑(PBO)、阻焊劑(SR)、ABF膜等的聚合物材料製成。在一些實施例中，由光敏感材料形成絕緣層230，並且當曝光時可發生化學反應。
在一些實施例中，阻障層117和絕緣層230由不同的材料製成。根據一些實施例，使用分配製程、塗佈製程等、或其組合來形成絕緣層230。根據一些實施例，如第2圖所示，執行第1G圖至第1H圖的步驟以形成晶片封裝結構300。
根據一些實施例，第3A圖至第3C圖是用於形成晶片封裝結構的製程的各個階段的剖面圖。根據一些實施例，如第3A圖所示，在第1E圖的步驟之後去除遮罩層164，然後在絕緣層118和導電墊167上方形成絕緣層310。根據一些實施例，絕緣層310具有開口312。根據一些實施例，開口312露出在絕緣層118的開口118b中的導電墊167。
根據一些實施例，絕緣層310由如環氧樹脂、聚醯亞胺、聚苯並噁唑(PBO)、阻焊劑(SR)、ABF膜等的聚合物材料製成。在一些實施例中，由光敏感材料形成絕緣層310，並且當曝光時可發生化學反應。在一些實施例中，阻障層117和絕緣層310由不同的材料所製成。
根據一些實施例，使用塗佈製程、層壓製程、化學氣相沉積製程等或其組合來形成絕緣層310。根據一些實施例，使用微影製程和蝕刻製程來形成開口312。
根據一些實施例，如第3A圖所示，在絕緣層310和導電墊167上方形成晶種層320。在一些實施例中，晶種層320的底部322穿過絕緣層310，以共形地覆蓋導電墊167的第二部分167b。
根據一些實施例，晶種層320的底部322部分地位在絕緣層118中。根據一些實施例，由鈦、銅等形成晶種層320。晶種層320的材料可以包括其他金屬，例如銀、金、鋁及其組合。
此後，根據一些實施例，如第3A圖所示，在晶種層320上方形成遮罩層170。根據一些實施例，遮罩層170與晶種層320直接接觸。根據一些實施例，遮罩層170具有開口172。根據一些實施例，開口172部分地露出晶種層320。根據一些實施例，由如光阻材料的聚合物材料形成遮罩層170。
此後，根據一些實施例，如第3A圖所示，在開口172中分別形成導電凸塊180。根據一些實施例，導電凸塊180與晶種層320直接接觸。根據一些實施例，導電凸塊180直接位在開口118b上方。根據一些實施例，導電凸塊180直接位在導電墊167的第二部分167b上方。
根據一些實施例，導電凸塊180和導孔結構112在垂直於表面111b的垂直方向Vl上錯位。在一些實施例中，根據一些實施例，導電凸塊180的底部184穿過絕緣層310。絕緣層310部分地位在導電凸塊180和導電墊167之間。
根據一些實施例，由如銅(Cu)、鋁(Al) 、鎢(W) 、鈷(Co) 、或鎳(Ni)的導電材料形成導電凸塊180。根據一些實施例，使用如電鍍製程的鍍層製程來形成導電凸塊180。
此後，根據一些實施例，如第3A圖所示，分別在導電凸塊180上方形成焊接層190。根據一些實施例，由錫(Sn)、無鉛焊料或熔點低於導電凸塊180的熔點的其他合適的導電材料形成焊接層190。根據一些實施例，使用如電鍍製程的鍍層製程來形成焊接層190。
根據一些實施例，如第3B圖所示，去除遮罩層170。根據一些實施例，去除製程包括灰化製程及/或清洗製程。此後，根據一些實施例，如第3B圖所示，去除了一開始位在遮罩層170下方的晶種層320。根據一些實施例，去除製程包括如濕蝕刻製程或乾蝕刻製程的蝕刻製程。
此後，根據一些實施例，如第3B圖所示，在焊接層190上執行回流製程，以將焊接層190轉換成焊球190a。根據一些實施例，如第3B圖所示，執行切割製程以沿著預定的切割道SC切穿絕緣層310、基板110、和模封層150，而形成晶片封裝結構400。
根據一些實施例，導電凸塊180藉由晶種層320和下方的導電墊167電性連接到導孔結構112。根據一些實施例，如第3C圖所示，執行第1H圖的步驟以形成晶片封裝結構500。
根據一些實施例，第4A圖是晶片封裝結構600的剖面圖。根據一些實施例，第4B圖是第4A圖的晶片封裝結構600的俯視圖。根據一些實施例，第4A圖是沿著第4B圖中的剖面線I-I’繪示的晶片封裝結構600的剖面圖。
根據一些實施例，如第4A圖和第4B圖所示，除了導電凸塊180在垂直方向上與導孔結構112重疊以外，晶片封裝結構600類似於第3C圖的晶片封裝結構500。
用於形成晶片封裝結構300、500和600的製程和材料可以與用於形成上述晶片封裝結構200的製程和材料相似或相同。
根據一些實施例，本揭露提供了一種晶片封裝結構及其形成方法。(用於形成晶片封裝結構的)此方法包括：在基板上依序形成阻障層和絕緣層、在絕緣層上形成導電墊，其中導電墊具有第一部分和第二部分，第一部分穿過阻障層和第二絕緣層，以與基板中的導孔結構連接，並且第二部分穿過絕緣層、在第二部分上形成導電凸塊。當藉由導電凸塊將基板接合到另一個基板時，接合應力傾向於集中在導電凸塊上。由於第二部分穿過絕緣層，因此集中在導電凸塊上的接合應力會直接傳遞到阻障層和基板，而不傳遞到絕緣層。因此，保護了絕緣層免於被接合應力損壞。因此提高了接合製程的良率。
根據一些實施例，本揭露提供一種晶片封裝結構形成方法。此方法包括在第一基板中形成導孔結構。此方法包括將晶片接合到第一基板的第一表面。此方法包括在第一基板的第二表面上方形成阻障層。阻障層直接接觸第一基板，且阻障層具有露出導孔結構的第一開口。此方法包括在阻障層上方形成第一絕緣層。第一絕緣層具有第二開口以及第三開口，第二開口位在第一開口上方並且露出導孔結構，第三開口部分地露出阻障層，且阻障層比第一絕緣層薄。此方法包括在第一絕緣層上方以及在第一開口、第二開口、第三開口中形成導電墊。導電墊從導孔結構連續地延伸到第三開口中。此方法包括在第三開口中的導電墊上方形成導電凸塊。
在一些實施例中，封裝結構形成方法更包括藉由導電凸塊，將第一基板接合到第二基板。在一些實施例中，導電凸塊比導電墊厚，且導電凸塊直接接觸導電墊。在一些實施例中，導電凸塊的底部位在第三開口中。在一些實施例中，第二開口進一步露出阻障層的一部份。在一些實施例中，導電凸塊以及導孔結構在垂直第二表面的一垂直方向上錯位。在一些實施例中，晶片封裝結構形成方法更包括在第三開口中的導電墊上方形成導電凸塊之後，在第一絕緣層以及導電墊上方形成第二絕緣層，第二絕緣層圍繞導電凸塊。在一些實施例中，導電墊的第一寬度大於導電凸塊的第二寬度、導孔結構的第三寬度、以及導電凸塊和導孔結構間的距離之總和。在一些實施例中，形成導電凸塊的操作包括在導電墊以及第一絕緣層上方形成遮罩層，遮罩層直接接觸導電墊以及第一絕緣層，且遮罩層具有第四開口，第四開口露出位在第三開口中的導電墊、在第四開口中形成導電凸塊、以及去除遮罩層。在一些實施例中，阻障層以及第一絕緣層係由不同的材料所形成。
根據一些實施例，本揭露提供一種晶片封裝結構形成方法。此方法包括在基板中形成導孔結構。此方法包括將晶片接合基板的第一表面。此方法包括在基板的第二表面上方形成阻障層，阻障層直接接觸基板。此方法包括形成部分地位在阻障層上方的第一絕緣層。此方法包括在第一絕緣層上方形成導電墊，導電墊具有第一部份以及第二部分，第一部分穿過阻障層以及第一絕緣層以連接到導孔結構，且第二部分穿過第一絕緣層並直接接觸阻障層。此方法包括在第一絕緣層以及導電墊上方形成第二絕緣層。此方法包括在第二絕緣層上方形成導電凸塊，導電凸塊的第一底部穿過第二絕緣層，以連接導電墊的第二部分。
在一些實施例中，晶片封裝結構形成方法更包括在第二絕緣層上方形成導電凸塊之前，在第二絕緣層上方形成晶種層，晶種層的第二底部穿過第二絕緣層，以共形地覆蓋導電墊的第二部分，且導電凸塊形成在晶種層上方。在一些實施例中，晶種層的第二底部係部分地位在第一絕緣層中。在一些實施例中，導電墊在剖面視角中具有類似W字形的形狀。在一些實施例中，阻障層比第一絕緣層硬。
根據一些實施例，本揭露提供一種晶片封裝結構。此晶片封裝結構包括第一基板。此晶片封裝結構包括導孔結構，穿過第一基板。此晶片封裝結構包括晶片，位在第一基板的第一表面上方。此晶片封裝結構包括阻障層，位在第一基板的第二表面上方，阻障層直接接觸第一基板。此晶片封裝結構包括第一絕緣層，位在阻障層上方。此晶片封裝結構包括導電墊，位在第一絕緣層上方，導電墊具有第一部分以及第二部分，第一部分穿過阻障層以及第一絕緣層以連接導孔結構，且第二部分穿過第一絕緣層並直接接觸阻障層。此晶片封裝結構包括導電凸塊，位在導電墊的第二部分上方。
在一些實施例中，導電凸塊比導電墊厚，且導電凸塊直接接觸導電墊。在一些實施例中，導電凸塊以及導電墊之間的接觸面積大於導電凸塊的頂表面的面積。在一些實施例中，晶片封裝結構更包括第二絕緣層，位在第一絕緣層以及導電墊的第一部分上方。在一些實施例中，晶片封裝結構更包括第二絕緣層，位在第一絕緣層以及導電墊上方，導電凸塊穿過第二絕緣層以連接導電墊，且第二絕緣層部分地位在導電凸塊以及導電墊之間。
上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本揭露之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本揭露為基礎，設計或修改其他製程及結構，以達到與本揭露實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本揭露之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本揭露的精神及範圍。
100,200,300,400,500,600:晶片封裝結構 110,210:基板 111:半導體基板 111a,111b:表面 112:導孔結構 113,117:阻障層 114:重分佈結構 114a,118,212,230,310:絕緣層 114b,214:線路層 114c,216:導孔 114d,167,218:導電墊 115,132,180:導電凸塊 116,134:焊接層 117a,118a,118b,164a,172,312:開口 120:晶片 122,152,180a:頂表面 136,190a:焊球 140,220:底部填充層 150:模封層 162,320:晶種層 164:遮罩層 166:導電層 167a:第一部分 167b:第二部分 170:遮罩層 182,322:底部 190:焊接層 D:距離 G1:間隙 SC:切割道 V1:垂直方向 W1,W2,W3:寬度
以下將配合所附圖式詳述本揭露之實施例。應注意的是，依據在業界的標準做法，多種特徵並未按照比例繪示且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。 根據一些實施例，第1A圖至第1H圖是用於形成晶片封裝結構的製程的各個階段的剖面圖。 根據一些實施例，第1E-1圖是第1E圖的晶片封裝結構的俯視圖。 根據一些實施例，第1G-1圖是第1G圖的晶片封裝結構的俯視圖。 根據一些實施例，第2圖是晶片封裝結構的剖面圖。 根據一些實施例，第3A圖至第3C圖是用於形成晶片封裝結構的製程的各個階段的剖面圖。 根據一些實施例，第4A圖是晶片封裝結構的剖面圖。 根據一些實施例，第4B圖是第4A圖的晶片封裝結構的俯視圖。
100,200:晶片封裝結構
110,210:基板
111:半導體基板
117:阻障層
118,212:絕緣層
118a:開口
120:晶片
150:模封層
162:晶種層
166:導電層
167,218:導電墊
180:導電凸塊
190a:焊球
214:線路層
216:導孔
220:底部填充層
W1,W2:寬度

Claims (1)

  1. 一種晶片封裝結構形成方法，包括： 在一第一基板中形成一導孔結構； 將一晶片接合到該第一基板的一第一表面； 在該第一基板的一第二表面上方形成一阻障層，其中該阻障層直接接觸該第一基板，且該阻障層具有露出該導孔結構的一第一開口； 在該阻障層上方形成一第一絕緣層，其中該第一絕緣層具有一第二開口以及一第三開口，該第二開口位在該第一開口上方並且露出該導孔結構，該第三開口部分地露出該阻障層，且該阻障層比該第一絕緣層薄； 在該第一絕緣層上方以及在該第一開口、該第二開口、該第三開口中形成一導電墊，其中該導電墊從該導孔結構連續地延伸到該第三開口中；以及 在該第三開口中的該導電墊上方形成一導電凸塊。
TW109107598A 2019-06-27 2020-03-09 晶片封裝結構形成方法 TW202101616A (zh)

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TWI824634B (zh) * 2021-11-04 2023-12-01 群創光電股份有限公司 電性連接結構

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US10770427B1 (en) * 2019-06-27 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same

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JP3756041B2 (ja) * 1999-05-27 2006-03-15 Ｈｏｙａ株式会社 多層プリント配線板の製造方法
US20020151164A1 (en) * 2001-04-12 2002-10-17 Jiang Hunt Hang Structure and method for depositing solder bumps on a wafer
JP4068838B2 (ja) * 2001-12-07 2008-03-26 株式会社日立製作所 半導体装置の製造方法
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US10770427B1 (en) * 2019-06-27 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same

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* Cited by examiner, † Cited by third party
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TWI824634B (zh) * 2021-11-04 2023-12-01 群創光電股份有限公司 電性連接結構

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