CN102456651B - 具有含钴的侧壁保护层的铜柱 - Google Patents

具有含钴的侧壁保护层的铜柱 Download PDF

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Publication number
CN102456651B
CN102456651B CN201110194230.2A CN201110194230A CN102456651B CN 102456651 B CN102456651 B CN 102456651B CN 201110194230 A CN201110194230 A CN 201110194230A CN 102456651 B CN102456651 B CN 102456651B
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layer
metal
substrate
integrated circuit
projection
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CN102456651A (zh
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黄见翎
林正怡
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供一种集成电路器件，包括铜柱和叠加在铜柱上的焊料层。形成含钴金属化层以覆盖铜柱和焊料层，然后执行热回流工艺以形成焊接凸块并且驱使钴元素进入焊接凸块中。接下来，执行氧化工艺以在铜柱的侧壁表面上形成钴氧化层。

Description

具有含钴的侧壁保护层的铜柱
交叉引用
本申请要求2010年10月18日提交的，申请号为61/394,038的美国临时专利申请的优先权，并将其结合于此作为参考。
本申请是涉及2010年7月26日提交的，申请号为12/843,760的美国专利申请的共同申请，将其结合于此作为参考。
技术领域
本公开涉及集成电路制造以及，更具体地，涉及集成电路器件中的铜柱凸块结构。
背景技术
倒装芯片封装利用凸块建立芯片的输入/输出(I/O)焊盘和衬底或封装的引线框架之间的电接触。在结构上，凸块结构包括凸块和位于该凸块和I/O焊盘之间的所谓的凸块下金属层(UBM)。UBM通常包括接合层、势垒层以及浸润层，它们按此顺序布置在I/O焊盘上。基于凸块本身使用的材料，将其归类为焊料凸块、金制凸块、铜(Cu)柱凸块和使用混合金属的凸块。近来，提出了铜互连柱技术。取代使用焊接凸块，用过使用铜柱使电子元件与衬底连接。与焊接凸块技术相比，铜柱凸块技术实现了微小间距具有最小概率的凸块桥接，减小电路的电容负载，并且使得电子元件能够以高频率运行。对于保护凸块结构和连接电子元件，焊接合金仍然是必要的。
铜柱凸块倒装芯片组件具有以下优势：(1)更好的热/电性能，(2)更高的载流量，(3)更好的阻抗电迁移，从而使凸块寿命更长，(4)最小化成形缩孔-在铜柱凸块之间具有更多的连续沟槽。而且，通过使用有可控可焊性、消除了无铅泪滴设计的铜柱能够降低衬底成本。当前工艺采用具有开口的光阻层，并且在该光阻层的开口中形成具有金属层罩保护的铜柱。不过，在光刻剥离工艺之前和/或之后，金属层罩的形成经常会导致缺陷。此外，在制造工艺期间，铜有被氧化的趋势。被氧化的铜柱会导致电子元件与衬底间的粘附性较低。由于高泄漏电流，低粘附性会引起严重的可靠性问题。被氧化的铜柱还会导致沿底层材料和铜柱的接触面的底层开裂。该开裂会扩散至下层的低介电常数(低k)绝缘层或扩散至用于将铜柱和衬底相接合的焊料。
因此，需要一种侧壁保护层以防止铜氧化，传统的处理铜柱侧壁的方法具有高成本和界面分层问题。当前，采用浸锡(Sn)工艺提供在铜柱侧壁上的锡层，不过仍然存在工艺成本、浸锡层的厚度局限性、Sn和底层填料之间的粘附性、以及侧壁上的焊料润湿性问题和焊料过冷的影响等问题，这对于新一代芯片的微小间距封装技术仍是一个挑战。
发明内容
针对现有技术的缺陷，本发明提供了一种集成电路器件，包括：半导体衬底；凸块下金属层(UBM)层，叠加在所述半导体衬底上；在所述UBM层上的导电柱；以及钴氧化层，在所述导电柱的侧壁表面上。
根据本发明所述的集成电路器件，进一步包括叠加在所述导电柱上的焊料层，其中所述焊料层包括钴(Co)元素。
根据本发明所述的集成电路器件，其中所述焊料层包括无铅焊料层。
根据本发明所述的集成电路器件，进一步包括在所述导电柱和所述焊料层之间的金属保护层。
根据本发明所述的集成电路器件，其中所述金属氧化层延伸以覆盖所述金属保护层的侧壁表面。
根据本发明所述的集成电路器件，其中所述金属保护层包括镍。
根据本发明所述的集成电路器件，其中所述导电柱是铜柱。
根据本发明所述的一种封装组件，包括：第一衬底，所述第一衬底包括凸块结构；第二衬底，与所述第一衬底连接；以及接合焊料层，在所述第二衬底和所述第一衬底的凸块结构之间；其中所述凸块结构包括金属柱和在所述金属柱的侧壁表面上的钴氧化层。
根据本发明所述的封装组件，其中所述接合焊料层包括钴(Co)元素。
根据本发明所述的封装组件，其中所述凸块结构包括在所述导电柱和所述接合焊料层之间的金属保护层。
根据本发明所述的封装组件，其中所述钴氧化层延伸以覆盖所述金属保护层的侧壁表面。
根据本发明所述的封装组件，其中所述金属保护层包括镍。
根据本发明所述的封装组件，其中所述金属柱是铜柱。
根据本发明所述的封装组件，其中所述第二衬底包括导电迹线，所述导电迹线与所述凸块结构重叠以形成迹线上凸块互连。
根据本发明所述的一种形成集成电路器件的方法，所述方法包括：形成金属柱，所述金属柱叠加在半导体衬底上；形成焊料层，所述焊料层叠加在所述金属柱上；形成金属化层，所述金属化层覆盖所述金属柱和所述焊料层，其中所述金属化层包括钴(Co)元素；将所述焊料层热回流以形成焊接凸块，其中所述金属化层的Co元素转入所述焊接凸块中；以及将所述金属化层氧化，以在所述金属柱的侧壁表面上形成金属氧化层。
根据本发明所述的方法，其中所述金属柱是铜柱，并且所述金属化层是Co层。
根据本发明所述的方法，其中通过化学沉积形成所述金属化层。
根据本发明所述的方法，其中进一步包括在形成所述金属化层之前，在所述金属柱和所述焊料层之间形成金属保护层。
根据本发明所述的方法，其中所述金属保护层包括镍。
根据本发明所述的方法，其中所述金属氧化层是钴氧化层。
附图说明
图1A-1G是描绘形成铜柱凸块结构的示例实施例的截面图；
图2是根据一个示例实施例的封装组件的截面图；以及
图3描绘了根据本公开多个方面的铜柱凸块结构的制造方法的流程图。
具体实施方式
本公开提供了用于铜柱凸块技术的侧壁保护层的形成工艺实施例。如整个公开中使用的，术语“铜柱凸块”是指包括导电铜柱(柱or支座)凸块结构，该铜柱包括铜或铜合金。铜柱凸块可以直接施加在电焊盘、用于倒装芯片组件的半导体芯片上的再分配层、或其他类似应用。在以下描述中，阐释了多个特定细节以帮助更透彻的理解本公开。不过，本领域普通技术人员应该认识到，没有这些特定细节也可以实现本公开。在一些情况下，没有详细描述公知结构和工艺以避免不必要的模糊本公开。在整个说明书的引用中，“一个实施例”或“一实施例”表示相关实施例中描述的特定部件、结构、特性包括在至少一个实施例中。因此，在整个说明书中不同地方出现的短语“在一个实施例中”或“在一实施例中”并不需要参见同一个实施例。而且，也可以以任意适当的方式将特定部件、结构、或特性结合在一个或更多实施例中。应当理解，以下图形并未按比例绘制；相反地，这些图形仅仅用于说明目的。
图1A-1D是根据示例实施例，部分半导体器件在铜柱凸块制造工艺中的不同阶段的截面图。
参见图1A，用于凸块制造的示例衬底10包括与半导体集成电路制造中采用的衬底一样的半导体衬底，并且可以在该衬底中和/或衬底上形成集成电路。将半导体衬底限定为指包括半导体材料的任意结构，该材料包括，但不仅限于体硅、半导体晶片、绝缘体上硅(SOI)衬底、或硅锗衬底。其他半导体材料包括可以使用的族Ⅲ、族Ⅳ、和/或族Ⅴ元素。衬底10可以进一步包括多个隔离部件(未示出)，例如浅沟隔离(STI)部件或硅的局部氧化(LOCOS)部件。隔离部件可以限定且隔离各种微电子元件(未示出)。可以形成在衬底10中的各种微电子元件的示例包括晶体管(例如金属氧化物半导体场效应晶体管(MOSFET)、互补型金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p-沟道和/或n-沟道场效应晶体管(PFET/NFET)、等等)；电阻器、二极管、电容器、感应器、保险丝、和/或其他适合的元件。被执行以形成各种微电子元件的各种工艺包括沉积、蚀刻、注入、光刻、热处理、和/或其他适合的工艺。微电子元件相互连接以形成集成电路器件，例如逻辑器件、存储器件(例如SRAM)、RF器件、输入/输出(I/O)器件、片上系统(SoC)器件、及其组合、和/或其他适合的器件种类。
衬底10进一步包括叠加在集成电路上的层间绝缘层和金属化结构。金属化结构中的层间绝缘层包括低-k绝缘材料、未掺杂硅酸盐玻璃(USG)、氮化硅、氮氧化硅、或其他通常使用的材料。低-k绝缘材料的介电常数(k值)可以大约小于3.9，或大约小于2.8。金属化结构中的金属线可以由铜或铜合金形成。本领域普通技术人员能够利用适当工艺形成金属化层，因此省略了形成金属化层的细节。如图1所示，导电区12是形成在顶层层间绝缘层中的金属化层，该层是导电通路的一部分，并且具有经过平面化工艺(例如化学机械抛光(CMP))处理的暴露面(如果必要的话)。用于导电区的适合材料包括，但不仅限于，例如铜(Cu)、铝(Al)、AlCu、铜合金、或其他导电材料。导电区12可以是金属焊盘区或再分布线路区，其用于接合工艺中以连接相应芯片中的集成电路和外部部件。
图1还描绘了在衬底10上形成钝化层14，并且图案化该层以形成露出部分导电区12的开口以允许后续的凸块结构。在至少一个实施例中，钝化层14由非有机材料，例如未掺杂硅盐酸玻璃(USG)、氮化硅、氮氧化硅、氧化硅、及其组合形成。在另一个实施例中，钝化层14由聚合物层形成，例如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并噁唑(PBO)、以及类似物，但是还可以使用其他相对较软、通常为有机的、绝缘材料。
图1进一步描绘了凸块下金属(UBM)层16的结构。在部分实施例中，UBM层16包括在衬底10上方形成的第一UBM层16a和第二UBM层16b。例如，UBM层16形成在导电区12的露出部分上，并且延伸至部分钝化层14上方。第一UBM层16a(也称为扩散势垒层或粘合层)由钛、钽、氮化钛、氮化钽、或类似物通过物理气相沉积(PVD)或溅射形成。沉积第一UBM层16a使其厚度范围为约500至2000埃，并且在部分实施例中例如，厚度约为1000埃。第二UBM层16b是通过物理气相沉积(PVD)或溅射在第一UBM层16a上形成的铜晶种层。第二UBM层16b由铜合金形成，该合金包括银、铬、镍、锡、金、或其组合。沉积第二UBM层16b，使其厚度达到约500至10000埃，并且在部分实施例中，例如厚度达到约5000埃。在至少一个实施例中，UBM层16包括由Ti形成的第一UBM层16a和由Cu形成的第二UBM层16b。
接下来，在图1B中，在第一UBM层16a上形成掩膜层20，并且将该层图案化形成开口18以露出部分第一UBM层16a用于形成凸块。掩膜层20是通过涂敷、硬化、电浆预处理和/或类似步骤，随后通过光刻技术和蚀刻工艺(例如干蚀刻和/或湿蚀刻工艺)而得到的干膜或光刻胶膜。
然后，用具有焊料润湿性的导电材料部分地填充开口18。参见图1C，在开口18中形成铜(Cu)层22以接通下面的第二UBM层16b。铜层22通常基本由含有纯元素铜、含有不可避免的杂质的铜、和/或含有微量元素的铜合金的层组成，这些微量元素包括钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆。形成方法包括溅射、印刷、电镀、化学镀、和/或通常使用的化学气相沉积(CVD)法。例如，执行电化学镀(ECP)以形成Cu层22。在一个示例实施例中，Cu层22的的厚度大于30um。在另一示例实施例中，Cu层22的厚度大于40um。例如，Cu层22的厚度约为40-50um，或约为40-70um，但是该厚度可以更大或更小。以下将Cu22层称为铜柱22。
接下来，在铜柱22的顶面形成金属保护层24。金属保护层24可以作为势垒层防止铜柱22中的铜扩散至接合材料中，例如用于接合衬底10和外部部件的焊接合金。防止铜扩散能够增加封装的可靠性和接合强度。金属保护层24是金属化层，该层包括镍、锡、锡铅(SnPb)、金(Au)、银、钯(Pd)、铟、镍-钯-金(NiPdAu)、镍-金(NiAu)、其他类似材料、或合金。金属保护层24是多层结构或单层结构。在至少一个实施例中，金属保护层24的厚度约为1-5um。然后，在掩膜层20的开口18中的金属保护层24上形成焊料层26。焊料层26由Sn、SnAg、Sn-Pb、SnAgCu(其中铜的重量百分比小于0.3％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn、或SnAgSb、等等形成。在至少一个实施例中，焊料层26由无铅焊材料层形成。
参见图1D，去除掩膜层20以露出部分UBM层16。由此得到的结构包括铜柱22、金属保护层24和焊料层26，并且露出了铜柱22的侧壁22a。本实施例中掩膜层20是干膜，可以利用碱性溶液去除该掩膜层。之后，利用由此得到的结构(包括层22、24和26)作为掩膜层，根据UBM材料的冶金性，通过湿和/或干蚀刻工艺回蚀第二UBM层16b和第一UBM层16a。
为了保护铜柱22的露出的侧壁22a，该工艺接着在铜柱22上形成了侧壁保护层。如图1E所示，在一个实施例中，在铜柱22的露出的侧壁表面22a上形成金属化层28。在部分实施例中，金属化层28延伸以覆盖在金属保护层24和焊料层26的露出表面上。金属化层28包括钴(Co)或钴合金(例如CoWBP或CoWP)。采用基于钴的保护层以抑制Cu扩散和迁移。通过化学镀工艺或浸镀工艺，在UBM层16、铜柱22、金属保护层24以及焊料层26的露出表面上选择性地形成金属化层28，但不在钝化层24上形成。通过利用化学镀，能够准确地控制金属化层28的厚度。在部分实施例中，金属化层28的厚度约为0.1-10um。金属化层28可以是单层结构、双层结构或三层结构。
参见图1F，例如通过晶片加热或快速热处理工艺(RTP)，执行热回流工艺融化焊料层26以形成半球形焊接凸块26a。金属化层28中的钴元素混合在由此得到的焊接凸块26a中。在部分实施例中，在回流之后，在低于焊接凸块26a的熔化温度的温度下，可选地执行另外的热处理，以进一步使钴元素扩散至焊接凸块26a中。在由此得到的焊接凸块26a中，钴元素的原子百分比小于约0.7％、或小于约0.1％、或甚至小于约0.01％。由于添加了钴元素，在焊接凸块26a中出现了SnAgCoX金属间化合物(IMC)以抑制SnAg IMC。因此，至少可以减少焊接凸块26a的过冷影响，并且焊接凸块26a可以更均匀地结晶。可以观察到，掺钴焊接凸块的过冷温度可以下降约7℃-30℃。
接下来，为了解决铜柱侧壁变湿问题，执行氧化工艺使金属化层28变成金属氧化层3。在至少一个实施例中，金属氧化层30是氧化钴(CoOX)层。这样就完成了凸块结构32，其包括铜柱22、金属保护层24、焊接凸块26a以及金属氧化层30。本公开提供了一种方法，即在去除掩膜层20之后，执行化学镀钴沉积工艺，然后在使焊料层26热回流之后，氧化金属层28，从而保护铜柱22的侧壁表面。除了作为侧壁保护层，还可以将按剂量添加钴元素并使其分布在焊接凸块26a中以改变焊接材料的特性，并且金属氧化工艺能够防止铜柱侧壁的焊料润湿。这种无润湿性效果有益于迹线上凸块(BOT)封装技术。与传统的浸Sn工艺相比，化学镀钴沉积方法使得能够更好的控制侧壁保护层的厚度以得到更薄的侧壁保护层，并且还能够因此减少工艺成本。
然后，锯下衬底10并且将其封装在封装衬底、或另一小片上，并且焊接球或铜凸块放置在封装衬底的焊盘或另一小片上。图2是描绘倒装芯片组件的示例实施例的截面示意图。在图2中，翻转图1中示出的结构并且使其底部与另一衬底100连接。衬底100可以是封装衬底、板(例如，印刷电路板(PCB))、或其他合适的衬底。凸块结构32通过各种导电连接点与衬底100连接(例如在接触焊盘上的接合焊料层102和/或导电迹线104)以形成接合结构，该结构连接了两个衬底10和100。接合焊料层102可以是共晶焊接材料，其包括锡、铅、银、铜、镍、铋或其组合的合金。在部分实施例中，通过连接焊接凸块26a和衬底100的预焊料层而形成接合焊料层102。接合焊料层102包括钴元素。示例连接工艺包括施加助焊剂、设置芯片、使融化的焊接点回流、和/或清除残留助焊剂。可以将集成电路衬底10、接合焊料层102、以及另一衬底100称为封装组件200，或在本实施例中，称为倒装芯片封装组件。在至少一个实施例中，凸块结构32和导电区104重叠并且形成迹线上凸块(BOT)互连。
现在参见图3，该图描绘了根据本公开实施例的用于形成凸块结构的方法300的流程。方法300可以用于制造以上图形阐述的结构，例如凸块结构32。应该理解，可以在方法300之前、期间和/或之后执行其他工艺，并且在该方法的不同实施例中，可以替换或去除以下描述的部分步骤。
方法300从步骤310开始，该步骤形成重叠在半导体衬底上的UBM层。在至少一个实施例中，半导体衬底包括导电区和钝化层，其中钝化层具有露出部分导电区的开口。UBM层通过钝化层的开口与导电区电连接。在步骤320中，在UBM层上形成掩膜层，其中图案化掩膜层使其具有流出部分UBM层的开口。在下一步314中，在掩膜层的开口中形成铜柱以与下面的UBM层电连接。然后在步骤316中，在铜柱上形成金属保护层，随后在步骤318中，在金属保护层上形成焊料层。接下来，在步骤320中去除掩膜层，然后在步骤322，利用铜柱作为掩膜，执行UBM工艺去除UBM层的露出部分，方法300继续步骤324，其中在UBM层、铜柱、金属保护层、以及焊料层的露出表面上形成金属化层。在一个实施例中，金属化层至少包括通过化学沉积形成的一个Co层或Co合金层的其中之一。然后方法300继续步骤326，其中在焊料层上执行热回流工艺。焊料层回流以变成半球形焊接凸块，其中按剂量添加钴元素并使其分散。在下一步骤328中，在金属化层上执行氧化工艺，以在铜柱和/或金属保护层的侧壁表面上形成金属氧化层。
在以上的详细描述中，参照本公开的具体示例实施例描述了本公开。不过，显然的是，可以在不背离本公开的更广泛的精神和范围的情况下，做各种不同的修改、结构、工艺、以及改变。相应地，本说明书和附图只应被视为是说明性的而并非是限制性的。应该理解，本公开可以使用各种其他组合和环境，并且可以在此处所论述的思想范围之内做出改变或修改。

Claims (7)

1.一种集成电路器件，包括：
半导体衬底；
凸块下金属层，叠加在所述半导体衬底上；
在所述凸块下金属层上的导电柱；
钴氧化层，在所述导电柱的侧壁表面上；以及
焊料层，叠加在所述导电柱上，其中所述焊料层包括钴元素，
其中，所述导电柱是铜柱。
2.根据权利要求1所述的集成电路器件，其中所述焊料层包括无铅焊料层。
3.根据权利要求1所述的集成电路器件，进一步包括在所述导电柱和所述焊料层之间的金属保护层。
4.根据权利要求3所述的集成电路器件，其中所述钴氧化层延伸成覆盖所述金属保护层的侧壁表面。
5.根据权利要求3所述的集成电路器件，其中所述金属保护层包括镍。
6.一种封装组件，包括：
第一衬底，所述第一衬底包括凸块结构；
第二衬底，附接所述第一衬底；以及
接合焊料层，在所述第二衬底和所述第一衬底的凸块结构之间；
其中所述凸块结构包括金属柱和在所述金属柱的侧壁表面上的钴氧化层，
其中，所述金属柱是铜柱，所述接合焊料层包括钴元素。
7.一种形成集成电路器件的方法，所述方法包括：
形成金属柱，所述金属柱叠加在半导体衬底上；
形成焊料层，所述焊料层叠加在所述金属柱上；
形成金属化层，所述金属化层覆盖所述金属柱和所述焊料层，其中所述金属化层包括钴元素；
将所述焊料层热回流以形成焊接凸块，其中所述金属化层的钴元素转入所述焊接凸块中，所述焊料层包括钴元素；以及
将所述金属化层氧化，以在所述金属柱的侧壁表面上形成金属氧化层，
其中，所述金属柱是铜柱。
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