JP6544354B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6544354B2 JP6544354B2 JP2016529243A JP2016529243A JP6544354B2 JP 6544354 B2 JP6544354 B2 JP 6544354B2 JP 2016529243 A JP2016529243 A JP 2016529243A JP 2016529243 A JP2016529243 A JP 2016529243A JP 6544354 B2 JP6544354 B2 JP 6544354B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- layer
- opening
- package substrate
- wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 358
- 238000004519 manufacturing process Methods 0.000 title claims description 61
- 229910000679 solder Inorganic materials 0.000 claims description 494
- 239000000758 substrate Substances 0.000 claims description 258
- 229910052751 metal Inorganic materials 0.000 claims description 131
- 239000002184 metal Substances 0.000 claims description 131
- 239000011347 resin Substances 0.000 claims description 78
- 229920005989 resin Polymers 0.000 claims description 78
- 239000010949 copper Substances 0.000 claims description 52
- 238000002844 melting Methods 0.000 claims description 32
- 230000008018 melting Effects 0.000 claims description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 238000010438 heat treatment Methods 0.000 claims description 28
- 229910052802 copper Inorganic materials 0.000 claims description 27
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910020836 Sn-Ag Inorganic materials 0.000 claims description 8
- 229910020988 Sn—Ag Inorganic materials 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 359
- 238000000034 method Methods 0.000 description 60
- 239000010408 film Substances 0.000 description 46
- 230000004048 modification Effects 0.000 description 46
- 238000012986 modification Methods 0.000 description 46
- 230000008569 process Effects 0.000 description 31
- 230000000694 effects Effects 0.000 description 29
- 239000000463 material Substances 0.000 description 29
- 230000001965 increasing effect Effects 0.000 description 23
- 229910045601 alloy Inorganic materials 0.000 description 17
- 239000000956 alloy Substances 0.000 description 17
- 230000002093 peripheral effect Effects 0.000 description 17
- 230000006870 function Effects 0.000 description 15
- 230000008646 thermal stress Effects 0.000 description 15
- 238000007747 plating Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 12
- 230000035882 stress Effects 0.000 description 11
- 230000004907 flux Effects 0.000 description 10
- 238000001816 cooling Methods 0.000 description 7
- 238000011161 development Methods 0.000 description 7
- 230000018109 developmental process Effects 0.000 description 7
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 239000012298 atmosphere Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 235000019253 formic acid Nutrition 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- DEXFNLNNUZKHNO-UHFFFAOYSA-N 6-[3-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperidin-1-yl]-3-oxopropyl]-3H-1,3-benzoxazol-2-one Chemical class C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C1CCN(CC1)C(CCC1=CC2=C(NC(O2)=O)C=C1)=O DEXFNLNNUZKHNO-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000001151 other effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000011417 postcuring Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- YLZOPXRUQYQQID-UHFFFAOYSA-N 3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-1-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]propan-1-one Chemical class N1N=NC=2CN(CCC=21)CCC(=O)N1CCN(CC1)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F YLZOPXRUQYQQID-UHFFFAOYSA-N 0.000 description 1
- CONKBQPVFMXDOV-QHCPKHFHSA-N 6-[(5S)-5-[[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperazin-1-yl]methyl]-2-oxo-1,3-oxazolidin-3-yl]-3H-1,3-benzoxazol-2-one Chemical class C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)N1CCN(CC1)C[C@H]1CN(C(O1)=O)C1=CC2=C(NC(O2)=O)C=C1 CONKBQPVFMXDOV-QHCPKHFHSA-N 0.000 description 1
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- -1 Ammonia peroxide Chemical class 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1601—Structure
- H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
- H01L2224/16052—Shape in top view
- H01L2224/16055—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
- H01L2224/16057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16113—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
- H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81464—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
1.第1の実施の形態(半導体装置;ソルダレジスト層の開口の平面形状を円形とし、柱状金属層の径を開口の幅(径)よりも大きくする例)
2.変形例1−1(柱状金属層の中心と開口の中心とをずらして配置する例)
3.第2の実施の形態(半導体装置;ソルダレジスト層の開口の平面形状を略長方形とし、開口の長さを、パッケージ基板の熱膨張係数に応じて調整する例)
4.変形例2−1(開口の平面形状を楕円形とする例)
5.変形例2−2(開口内において、配線に拡幅部を設ける例)
6.変形例2−3(開口内において、配線に途切れ部を設ける例)
7.変形例2−4(二つの開口の角部に斜め切欠き部を設け、その二つの開口を、斜め切欠き部どうしを向かい合わせて隣接配置する例)
8.変形例2−5(二つの開口の辺に斜め切欠き部を設け、その二つの開口を、斜め切欠き部どうしを向かい合わせて隣接配置する例)
9.第3の実施の形態(半導体装置;開口内におけるソルダレジスト層の厚みを、基板本体の表面のうち開口以外の領域におけるソルダレジスト層の厚みよりも小さくする例)
10.第4の実施の形態(半導体装置;MCM(Multi Chip Module )の例)
11.第5の実施の形態(半導体装置;モールド樹脂で封止する例)
12.第6の実施の形態(半導体装置の製造方法;フラックスを用いて仮付けしたのち一括リフローを行う例)
13.第7の実施の形態(半導体装置の製造方法;ローカルリフローの例)
14.第8の実施の形態(半導体装置の製造方法;熱圧着により仮付けを行う例)
15.第9の実施の形態(半導体装置の製造方法;ツール側の温度を固定して熱圧着を行う例)
16.第10の実施の形態(半導体装置の製造方法;予めパッケージ基板の上にアンダーフィル樹脂を供給する例)
図1は、本開示の第1の実施の形態に係る半導体装置の全体構成を概略的に表したものであり、図2は、この半導体装置のII−II線における断面構成を概略的に表したものである。半導体装置1は、例えば、半導体チップ10とパッケージ基板20とを、はんだを含む複数の電極30により接続したフリップチップ型半導体装置である。半導体チップ10とパッケージ基板20との間には、アンダーフィル樹脂40が設けられている。
また、上記第1の実施の形態では、柱状金属層31の径dを、開口60の幅(径)Wよりも大きくすることにより、柱状金属層31とソルダレジスト層24とのオーバーラップ領域OLを設ける場合について説明した。しかしながら、例えば図5に示したように、柱状金属層31の中心C31と開口60の中心C60とをずらして配置するようにしてもよい。このようにした場合にも、柱状金属層31とソルダレジスト層24とのオーバーラップ領域OLを設けることができ、上記第1の実施の形態と同様の効果を得ることが可能となる。なお、本変形例は、上記第1の実施の形態に限らず、以下の第2ないし第10の実施の形態または変形例との組み合わせも可能である。
図6は、本開示の第2の実施の形態に係る半導体装置2の一部を拡大して表したものであり、具体的には、隣接する二本の配線50(50A,50B)の、チップ配設領域20Aの外周部近傍における平面構成を表している。なお、図6の上面図では、わかりやすくするために半導体チップ10およびアンダーフィル樹脂40を省略しているが、半導体チップ10は、点線で表した半導体チップ10のチップ外形線10Aよりも左側の領域に配置されている。
(式1において、Lは、開口60の長さ(mm)、aは、パッケージ基板20の等価熱膨張係数(ppm/℃)、Dは、開口60の中心のパッケージ基板20の中心からの距離(mm)、Tは、はんだの融点(℃)、dは、はんだを含む電極30の径をそれぞれ表す。)
(開口の平面形状を楕円形とする例)
図10は、変形例2−1に係る半導体装置の一部を拡大して表したものであり、具体的には、隣接する二本の配線50(50A,50B)のチップ配設領域20Aの外周部近傍における平面構成を表している。なお、図10の上面図では、わかりやすくするために半導体チップ10およびアンダーフィル樹脂40を省略しているが、半導体チップ10は、点線で表した半導体チップ10のチップ外形線10Aよりも左側の領域に配置されている。
(開口内において、配線に拡幅部を設ける例)
図12は、変形例2−2に係る半導体装置の一部を拡大して表したものであり、具体的には、隣接する二本の配線50(50A,50B)のチップ配設領域20Aの外周部近傍における平面構成を表している。なお、図12の上面図では、わかりやすくするために半導体チップ10、はんだを含む複数の電極30およびアンダーフィル樹脂40を省略しているが、半導体チップ10は、点線で表した半導体チップ10のチップ外形線10Aよりも左側の領域に配置されている。また、図12では、はんだを含む複数の電極30の実装位置を点線で表している。
(開口内において、配線に途切れ部を設ける例)
図13は、変形例2−3に係る半導体装置の一部を拡大して表したものであり、具体的には、隣接する二本の配線50(50A,50B)のチップ配設領域20Aの外周部近傍における平面構成を表している。なお、図13の上面図では、わかりやすくするために半導体チップ10、はんだを含む複数の電極30およびアンダーフィル樹脂40を省略しているが、半導体チップ10は、点線で表した半導体チップ10のチップ外形線10Aよりも左側の領域に配置されている。また、図13では、はんだを含む複数の電極30の実装位置を点線で表している。
(二つの開口の角部に斜め切欠き部を設け、その二つの開口を、斜め切欠き部どうしを向かい合わせて隣接配置する例)
図15は、変形例2−4に係る半導体装置の一部を拡大して表す上面図であり、具体的には、隣接する二本の配線50(50A,50B)のチップ配設領域20Aの外周部近傍における平面構成を表している。なお、図15の上面図では、わかりやすくするために半導体チップ10およびアンダーフィル樹脂40を省略しているが、半導体チップ10は、点線で表した半導体チップ10のチップ外形線10Aよりも左側の領域に配置されている。
(二つの開口の辺に斜め切欠き部を設け、その二つの開口を、斜め切欠き部どうしを向かい合わせて隣接配置する例)
図16は、変形例2−5に係る半導体装置の一部を拡大して表す上面図であり、具体的には、隣接する二本の配線50(50A,50B)のチップ配設領域20Aの外周部近傍における平面構成を表している。なお、図16の上面図では、わかりやすくするために半導体チップ10、はんだを含む複数の電極30およびアンダーフィル樹脂40を省略しているが、半導体チップ10は、点線で表した半導体チップ10のチップ外形線10Aよりも左側の領域に配置されている。
(半導体装置;開口内におけるソルダレジスト層の厚みを、基板本体の表面のうち開口以外の領域におけるソルダレジスト層の厚みよりも小さくする例)
図17は、本開示の第3の実施の形態に係る半導体装置の一部を拡大して表したものであり、具体的には、隣接する二本の配線50(50A,50B)のチップ配設領域20Aの外周部近傍における断面構成を表している。
(半導体装置;MCM(Multi Chip Module )の例)
図18は、本開示の第4の実施の形態に係る半導体装置の全体構成を概略的に表したものである。図19は、この半導体装置のXIX−XIX線における断面構成を概略的に表したものである。上記第2の実施の形態では半導体装置2が半導体チップ10単体のLSIパッケージである場合について説明したのに対し、本実施の形態の半導体装置4は、例えば、MCM(Multi Chip Module )への適用例である。このことを除いては、本実施の形態の半導体装置4は、上記第2の実施の形態の半導体装置2と同様の構成、作用および効果を有している。よって、対応する構成要素には同一の符号を付して説明する。
(半導体装置;モールド樹脂で封止する例)
図20は、本開示の第5の実施の形態に係る半導体装置の全体構成を概略的に表したものである。この半導体装置5は、上記第2の実施の形態で説明した半導体装置2を、モールド樹脂80で封止した構成を有している。半導体装置2をモールド樹脂80で封止することによって、半導体チップ10の裏面およびパッケージ基板20の基板本体21の表面21Aが保護される。従って、ハンドリングが容易になり、外部からの衝撃に強いフリップチップ型半導体装置5を実現することが可能となる。
また、図21に示したように、モールド樹脂80の内部に、半導体チップ10とは異なる半導体チップ90が積層されている半導体装置5Aにおいても、上記の効果を発揮することが可能である。半導体チップ90は、例えばチップ本体91を有している。チップ本体91は、ワイヤ92によりパッケージ基板20に接続されている。
更に、図22に示したように、第2の実施の形態で説明した半導体装置2の半導体チップ10の上に、更に他の半導体パッケージ100が積層されているPoP(Package on Package)型の半導体装置5Bでも、上記と同様の効果を得ることが可能である。
(半導体装置の製造方法;一括リフローの例)
図23ないし図30、および図31ないし図34は、本開示の第6の実施の形態に係る半導体装置の製造方法を工程順に表したものである。
(半導体装置の製造方法;ローカルリフローの例)
次に、同じく図31、図33および図34を参照して、パッケージ基板20と半導体チップ10との、サーマルコンプレッション(Thermal Compression )と呼ばれるローカルリフロー工法を用いた接続方法について説明する。
なお、上記第6の実施の形態では、フラックスによる仮付け後にリフロ炉で加熱する方法を説明したが、第7の実施の形態で説明したような熱圧着工法によって仮付けを行った後に、リフロ炉で加熱を行い、より合金層の成長を進めて確実に接合する手法を用いてもよい。
また、上記第7の実施の形態では、接合プロセス中に半導体チップ10を保持するツール側の温度を昇温/冷却させるプロセスを説明した。しかしながら、ツール側の温度をはんだ融点以上に固定した状態で熱圧着する工法を用いてもよい。この場合には、はんだ層32と配線50との接触によって荷重を検出することが難しいので、柱状金属層31がソルダレジスト層24と接触する際の荷重を検出する、または柱状金属層31が配線50と接触するときの荷重を検出し、その後所望のギャップGを形成するように、半導体チップ10を保持するツールを引き上げる。ただし、はんだ層32が溶融した状態のままで保持されるため、表面の酸化膜が成長する。よって窒素雰囲気下で接合を行う等の対策を行うことによって、より良い接合状態を得ることが可能となる。
(半導体装置の製造方法;予めパッケージ基板の上にアンダーフィル樹脂を供給する例)
図35ないし図37は、本開示の第10の実施の形態に係る半導体装置の製造方法を工程順に表したものである。本実施の形態の製造方法は、先にアンダーフィル樹脂40をパッケージ基板20上に供給するようにしたことにおいて上記第6の実施の形態に係る半導体装置の製造方法と異なるものである。
以上、各実施の形態およびその効果について説明した。以上の効果は、第1ないし第3の実施の形態のように単体の半導体チップ10を実装したフリップチップ型半導体装置に限られない。例えば、第4の実施の形態のように複数のメモリパッケージと半導体チップ10とが一枚のパッケージ基板20に実装された、MCM(Multi Chip Module )構造でも同じ効果を発揮することが可能である。
(1)
半導体チップと、前記半導体チップが配設されるパッケージ基板とを備え、
前記半導体チップは、チップ本体と、前記チップ本体の素子形成面に設けられたはんだを含む複数の電極とを有し、
前記パッケージ基板は、基板本体と、前記基板本体の表面に設けられた複数の配線およびソルダレジスト層とを有し、
前記ソルダレジスト層は、前記基板本体の表面および前記複数の配線の上に連続層として設けられると共に、前記複数の配線の各々の上に開口を有し、
前記はんだを含む複数の電極は、少なくとも一つの間隔制御電極を含み、
前記少なくとも一つの間隔制御電極は、前記チップ本体の側から、柱状金属層と、はんだ層とを順に有すると共に、前記開口の開口端の一部または全部に、前記柱状金属層と前記ソルダレジスト層とが重なるオーバーラップ領域を有する
半導体装置。
(2)
前記少なくとも一つの間隔制御電極は、複数の間隔制御電極を含み、
前記複数の間隔制御電極は、前記半導体チップの各辺に少なくとも一つ配置されている
前記(1)記載の半導体装置。
(3)
前記少なくとも一つの間隔制御電極において、前記柱状金属層の径は、前記開口の開口端の一部または全部において前記開口の幅よりも大きい
前記(1)または(2)記載の半導体装置。
(4)
前記少なくとも一つの間隔制御電極は、前記柱状金属層の中心と前記開口の中心とをずらして配置されている
前記(1)または(2)記載の半導体装置。
(5)
前記開口は、前記開口内の前記配線の長手方向に長い平面形状を有し、前記開口の長さは、前記パッケージ基板の熱膨張係数に応じて調整されている
前記(1)ないし(4)のいずれかに記載の半導体装置。
(6)
前記柱状金属層は、前記はんだ層を構成するはんだよりも高い融点をもつ金属により構成されている
前記(1)ないし(5)のいずれかに記載の半導体装置。
(7)
前記柱状金属層の高さは、前記はんだ層の高さよりも大きい
前記(6)記載の半導体装置。
(8)
前記はんだ層の体積は、前記開口の容積よりも大きい
前記(6)または(7)記載の半導体装置。
(9)
前記開口の長さは、以下の式1を満たす
L>(a−3.5)*D*(T−25)*10-6+d ・・・式1
(式1において、Lは、前記開口の長さ(mm)、aは、前記パッケージ基板の等価熱膨張係数(ppm/℃)、Dは、前記開口の中心の前記パッケージ基板の中心からの距離(mm)、Tは、前記はんだの融点(℃)、dは、前記はんだを含む複数の電極の各々の径をそれぞれ表す。)
前記(5)ないし(8)のいずれかに記載の半導体装置。
(10)
前記複数の配線の各々は、
主として銅(Cu)により構成された金属配線層と、
前記金属配線層の表面のうち前記開口内に露出した領域を覆う表面被膜と
を有する前記(1)ないし(9)のいずれかに記載の半導体装置。
(11)
前記表面被膜は、Ni−Auめっき層またはNi−Pd−Auめっき層により構成されている
前記(10)記載の半導体装置。
(12)
前記柱状金属層は、銅(Cu)または銅(Cu)とニッケル(Ni)との積層膜により構成され、
前記はんだ層は、スズ(Sn)またはSn−Agにより構成されている
前記(1)ないし(11)のいずれかに記載の半導体装置。
(13)
前記柱状金属層は、銅(Cu)または銅(Cu)とニッケル(Ni)との積層膜により構成され、
前記はんだ層は、インジウム(In)またはIn−Agにより構成されている
前記(1)ないし(11)のいずれかに記載の半導体装置。
(14)
チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板に対して位置決めすることと、
前記半導体チップを前記パッケージ基板に対して仮付けすることと、
リフロ加熱により前記はんだを含む複数の電極と前記複数の配線とを接続することと、
前記半導体チップと前記パッケージ基板との間にアンダーフィル樹脂を注入したのち前記アンダーフィル樹脂を硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記半導体チップを前記パッケージ基板に対して仮付けすることにおいて、前記半導体チップを前記パッケージ基板に対して加熱圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出する
半導体装置の製造方法。
(15)
チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、前記はんだの融点以上に加熱したのち、基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板に対して位置決めすることと、
前記はんだを含む複数の電極と前記複数の配線とを接続することと、
前記半導体チップと前記パッケージ基板との間にアンダーフィル樹脂を注入したのち前記アンダーフィル樹脂を硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記はんだを含む複数の電極と前記複数の配線とを接続することにおいて、前記半導体チップを前記パッケージ基板に対して圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出したのち、前記半導体チップと前記パッケージ基板との間の間隔を調整する
半導体装置の製造方法。
(16)
チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板に対して位置決めすることと、
前記はんだを含む複数の電極と前記複数の配線とを接続することと、
前記半導体チップと前記パッケージ基板との間にアンダーフィル樹脂を注入したのち前記アンダーフィル樹脂を硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記はんだを含む複数の電極と前記複数の配線とを接続することにおいて、前記半導体チップを前記パッケージ基板に対して圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出し、前記はんだの融点以上に加熱および圧着することにより前記はんだを含む複数の電極と前記複数の配線とを接続する
半導体装置の製造方法。
(17)
基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板の上に、アンダーフィル樹脂を供給することと、
チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、前記パッケージ基板に対して位置決めすることと、
前記はんだを含む複数の電極と前記複数の配線とを接続すると共に、前記アンダーフィル樹脂を仮硬化させることと、
前記アンダーフィル樹脂を本硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記はんだを含む複数の電極と前記複数の配線とを接続することにおいて、前記半導体チップを前記パッケージ基板に対して圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出し、前記はんだの融点以上に加熱および圧着することにより前記はんだを含む複数の電極と前記複数の配線とを接続する
半導体装置の製造方法。
Claims (16)
- チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板に対して位置決めすることと、
前記半導体チップを前記パッケージ基板に対して仮付けすることと、
リフロ加熱により前記はんだを含む複数の電極と前記複数の配線とを接続することと、
前記半導体チップと前記パッケージ基板との間にアンダーフィル樹脂を注入したのち前記アンダーフィル樹脂を硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記半導体チップを前記パッケージ基板に対して仮付けすることにおいて、前記半導体チップを前記パッケージ基板に対して加熱圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出する
半導体装置の製造方法。 - チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、前記はんだの融点以上に加熱したのち、基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板に対して位置決めすることと、
前記はんだを含む複数の電極と前記複数の配線とを接続することと、
前記半導体チップと前記パッケージ基板との間にアンダーフィル樹脂を注入したのち前記アンダーフィル樹脂を硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記はんだを含む複数の電極と前記複数の配線とを接続することにおいて、前記半導体チップを前記パッケージ基板に対して圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出したのち、前記半導体チップと前記パッケージ基板との間の間隔を調整する
半導体装置の製造方法。 - チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板に対して位置決めすることと、
前記はんだを含む複数の電極と前記複数の配線とを接続することと、
前記半導体チップと前記パッケージ基板との間にアンダーフィル樹脂を注入したのち前記アンダーフィル樹脂を硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記はんだを含む複数の電極と前記複数の配線とを接続することにおいて、前記半導体チップを前記パッケージ基板に対して圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出し、前記はんだの融点以上に加熱および圧着することにより前記はんだを含む複数の電極と前記複数の配線とを接続する
半導体装置の製造方法。 - 基板本体の表面に複数の配線およびソルダレジスト層を有するパッケージ基板の上に、アンダーフィル樹脂を供給することと、
チップ本体の素子形成面にはんだを含む複数の電極を有する半導体チップを、前記パッケージ基板に対して位置決めすることと、
前記はんだを含む複数の電極と前記複数の配線とを接続すると共に、前記アンダーフィル樹脂を仮硬化させることと、
前記アンダーフィル樹脂を本硬化させることと
を含み、
前記ソルダレジスト層を、前記基板本体の表面および前記複数の配線の上に連続層として設けると共に、前記複数の配線の各々の上に開口を設け、
前記はんだを含む複数の電極を、少なくとも一つの間隔制御電極を含んで形成し、
前記少なくとも一つの間隔制御電極として、前記チップ本体の側から、柱状金属層と、はんだ層とを順に形成し、
前記はんだを含む複数の電極と前記複数の配線とを接続することにおいて、前記半導体チップを前記パッケージ基板に対して圧着し、前記少なくとも一つの間隔制御電極の前記柱状金属層と前記ソルダレジスト層とを接触させて荷重を検出し、前記はんだの融点以上に加熱および圧着することにより前記はんだを含む複数の電極と前記複数の配線とを接続する
半導体装置の製造方法。 - 前記少なくとも一つの間隔制御電極として、複数の間隔制御電極を形成し、
前記複数の間隔制御電極を、前記半導体チップの各辺に少なくとも一つ配置する
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。 - 前記少なくとも一つの間隔制御電極において、前記柱状金属層の径を、前記開口の開口端の一部または全部において前記開口の幅よりも大きくする
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。 - 前記少なくとも一つの間隔制御電極を、前記柱状金属層の中心と前記開口の中心とをずらして配置する
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。 - 前記開口を、前記開口内の前記配線の長手方向に長い平面形状とし、前記開口の長さを、前記パッケージ基板の熱膨張係数に応じて調整する
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。 - 前記柱状金属層を、前記はんだ層を構成するはんだよりも高い融点をもつ金属により構成する
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。 - 前記柱状金属層の高さを、前記はんだ層の高さよりも大きくする
請求項9記載の半導体装置の製造方法。 - 前記はんだ層の体積を、前記開口の容積よりも大きくする
請求項9記載の半導体装置の製造方法。 - 前記開口の長さを、以下の式1を満たすようにする
L>(a−3.5)*D*(T−25)*10 -6 +d ・・・式1
(式1において、Lは、前記開口の長さ(mm)、aは、前記パッケージ基板の等価熱膨張係数(ppm/℃)、Dは、前記開口の中心の前記パッケージ基板の中心からの距離(mm)、Tは、前記はんだの融点(℃)、dは、前記はんだを含む複数の電極の各々の径をそれぞれ表す。)
請求項8記載の半導体装置の製造方法。 - 前記複数の配線の各々は、
主として銅(Cu)により構成された金属配線層と、
前記金属配線層の表面のうち前記開口内に露出した領域を覆う表面被膜と
を有する請求項1記載の半導体装置の製造方法。 - 前記表面被膜を、Ni−Auめっき層またはNi−Pd−Auめっき層により構成する
請求項13記載の半導体装置の製造方法。 - 前記柱状金属層を、銅(Cu)または銅(Cu)とニッケル(Ni)との積層膜により構成し、
前記はんだ層を、スズ(Sn)またはSn−Agにより構成する
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。 - 前記柱状金属層を、銅(Cu)または銅(Cu)とニッケル(Ni)との積層膜により構成し、
前記はんだ層を、インジウム(In)またはIn−Agにより構成する
請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014132333 | 2014-06-27 | ||
JP2014132333 | 2014-06-27 | ||
PCT/JP2015/066349 WO2015198838A1 (ja) | 2014-06-27 | 2015-06-05 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2015198838A1 JPWO2015198838A1 (ja) | 2017-05-25 |
JP6544354B2 true JP6544354B2 (ja) | 2019-07-17 |
Family
ID=54937934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016529243A Active JP6544354B2 (ja) | 2014-06-27 | 2015-06-05 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10867950B2 (ja) |
JP (1) | JP6544354B2 (ja) |
CN (1) | CN106463426B (ja) |
WO (1) | WO2015198838A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10861779B2 (en) * | 2018-06-22 | 2020-12-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having an electrical contact with a high-melting-point part and method of manufacturing the same |
JP7168280B2 (ja) * | 2018-06-26 | 2022-11-09 | 住友電工デバイス・イノベーション株式会社 | 半導体装置、および、半導体チップの搭載方法 |
US20200066626A1 (en) * | 2018-08-21 | 2020-02-27 | Intel Corporation | Pocket structures, materials, and methods for integrated circuit package supports |
US11417622B2 (en) | 2019-10-18 | 2022-08-16 | Qualcomm Incorporated | Flip-chip device |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2695893B2 (ja) | 1989-01-27 | 1998-01-14 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
JP3057130B2 (ja) * | 1993-02-18 | 2000-06-26 | 三菱電機株式会社 | 樹脂封止型半導体パッケージおよびその製造方法 |
US6730541B2 (en) * | 1997-11-20 | 2004-05-04 | Texas Instruments Incorporated | Wafer-scale assembly of chip-size packages |
US6683375B2 (en) * | 2001-06-15 | 2004-01-27 | Fairchild Semiconductor Corporation | Semiconductor die including conductive columns |
KR100523330B1 (ko) * | 2003-07-29 | 2005-10-24 | 삼성전자주식회사 | Smd 및 nsmd 복합형 솔더볼 랜드 구조를 가지는bga 반도체 패키지 |
US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
TWI230994B (en) * | 2004-02-25 | 2005-04-11 | Via Tech Inc | Circuit carrier |
JP4971769B2 (ja) * | 2005-12-22 | 2012-07-11 | 新光電気工業株式会社 | フリップチップ実装構造及びフリップチップ実装構造の製造方法 |
JP5011993B2 (ja) * | 2006-12-08 | 2012-08-29 | パナソニック株式会社 | 熱圧着ヘッドの荷重測定装置及び方法 |
TWI343084B (en) * | 2006-12-28 | 2011-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor device having conductive bumps and fabrication methodthereof |
US7772104B2 (en) * | 2007-02-02 | 2010-08-10 | Freescale Semiconductor, Inc. | Dynamic pad size to reduce solder fatigue |
JP4618260B2 (ja) * | 2007-02-21 | 2011-01-26 | 日本テキサス・インスツルメンツ株式会社 | 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置 |
JP2008244180A (ja) * | 2007-03-28 | 2008-10-09 | Kyocera Corp | 実装構造体およびその製造方法 |
US8222538B1 (en) * | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
US20110169157A1 (en) * | 2010-01-13 | 2011-07-14 | Wen-Jeng Fan | Substrate and flip chip package with gradational pad pitches |
US8866267B2 (en) * | 2010-05-28 | 2014-10-21 | Alpha & Omega Semiconductor, Inc. | Semiconductor device with substrate-side exposed device-side electrode and method of fabrication |
US9048135B2 (en) * | 2010-07-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper pillar bump with cobalt-containing sidewall protection |
TWI478303B (zh) * | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構 |
JP2013074054A (ja) * | 2011-09-27 | 2013-04-22 | Renesas Electronics Corp | 電子装置、配線基板、及び、電子装置の製造方法 |
US8912668B2 (en) * | 2012-03-01 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connections for chip scale packaging |
US9490196B2 (en) * | 2011-10-31 | 2016-11-08 | Intel Corporation | Multi die package having a die and a spacer layer in a recess |
US9313881B2 (en) * | 2013-01-11 | 2016-04-12 | Qualcomm Incorporated | Through mold via relief gutter on molded laser package (MLP) packages |
US9508671B2 (en) * | 2015-04-20 | 2016-11-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
US20170162536A1 (en) * | 2015-12-03 | 2017-06-08 | International Business Machines Corporation | Nanowires for pillar interconnects |
US10181448B2 (en) * | 2016-03-22 | 2019-01-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor devices and semiconductor packages |
KR101926187B1 (ko) * | 2016-12-15 | 2018-12-06 | 스마트모듈러 테크놀러지스 엘엑스 에스에이알엘 | 반도체 패키지의 범프 형성방법 |
-
2015
- 2015-06-05 JP JP2016529243A patent/JP6544354B2/ja active Active
- 2015-06-05 US US15/316,598 patent/US10867950B2/en active Active
- 2015-06-05 CN CN201580033302.1A patent/CN106463426B/zh active Active
- 2015-06-05 WO PCT/JP2015/066349 patent/WO2015198838A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US10867950B2 (en) | 2020-12-15 |
WO2015198838A1 (ja) | 2015-12-30 |
JPWO2015198838A1 (ja) | 2017-05-25 |
US20170141064A1 (en) | 2017-05-18 |
CN106463426A (zh) | 2017-02-22 |
CN106463426B (zh) | 2020-03-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6547745B2 (ja) | 半導体装置およびその製造方法 | |
JP5259560B2 (ja) | 半導体装置 | |
JP6458801B2 (ja) | 半導体装置およびその製造方法 | |
US7476564B2 (en) | Flip-chip packaging process using copper pillar as bump structure | |
US20070111398A1 (en) | Micro-electronic package structure and method for fabricating the same | |
JP2008016514A (ja) | 半導体装置の製造方法および半導体装置 | |
JP6586952B2 (ja) | 半導体装置およびその製造方法 | |
JP6544354B2 (ja) | 半導体装置の製造方法 | |
JP2005129955A (ja) | 超薄型フリップチップパッケージの製造方法 | |
JP5404513B2 (ja) | 半導体装置の製造方法 | |
JP2006041401A (ja) | 半導体装置及びその製造方法 | |
TW201903991A (zh) | 半導體裝置 | |
TWI336516B (en) | Surface structure of package substrate and method for manufacturing the same | |
US6956293B2 (en) | Semiconductor device | |
JP2002026073A (ja) | 半導体装置およびその製造方法 | |
US20040256737A1 (en) | [flip-chip package substrate and flip-chip bonding process thereof] | |
US6953711B2 (en) | Flip chip on lead frame | |
JP4668608B2 (ja) | 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法 | |
WO2013084384A1 (ja) | 半導体装置及びその製造方法 | |
WO2013051182A1 (ja) | 半導体装置及びその製造方法 | |
JP2006066505A (ja) | 半導体装置およびこれを備えた電子機器 | |
JP2005072211A (ja) | 電子部品とその製造方法及び電子装置 | |
JP2008091954A (ja) | 半導体装置の製造方法 | |
JP2008028108A (ja) | 半導体装置 | |
JP2006186128A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180531 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180531 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190326 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190510 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190521 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190603 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6544354 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |