JP2008028108A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2008028108A JP2008028108A JP2006198396A JP2006198396A JP2008028108A JP 2008028108 A JP2008028108 A JP 2008028108A JP 2006198396 A JP2006198396 A JP 2006198396A JP 2006198396 A JP2006198396 A JP 2006198396A JP 2008028108 A JP2008028108 A JP 2008028108A
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/732—Location after the connecting process
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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Abstract
【解決手段】本発明に係る半導体装置10は、チップ実装領域の周囲に電極パッド14が形成された実装基板としての第1の半導体チップ11と、チップ実装領域にフリップチップ実装された第2の半導体チップ12と、第1,第2の半導体チップ11,12の間に注入されたアンダーフィル材15とを備え、上記電極パッド14は、アンダーフィル材15の流出防止用のダムとして形成される。この構成により、第1の半導体チップ11の小型化を図れるようになる。また、電極パッド14がダムとして機能するので、電極パッド14の表面をアンダーフィル材15の汚染から防止して、ボンディングワイヤの接合信頼性を確保することができる。
【選択図】図1
Description
図1A,Bは、本発明の第1の実施形態を示しており、Aは、半導体装置10の一製造工程であるアンダーフィル注入工程を示す概略断面図、Bは、配線基板に対する半導体装置10の一実装形態を示す概略断面図である。
次に、本発明の第2の実施形態について説明する。上述の第1の実施形態においては、ワイヤボンディング用のパッド部22上に端子部17を突出形成することで、ダムを兼ねた電極パッド14を構成したが、本実施形態では、上記パッド部を当初より厚手に形成してダムを兼ねる電極パッドを構成するようにしている。図6は、本実施形態における電極パッド44の製造方法を説明する要部の工程断面図である。
次に、本発明の第3の実施形態について説明する。本実施形態では、ワイヤボンディング用のパッド部を下地層を介して形成することにより、アンダーフィル材の流出防止用ダムを兼ねる電極パッド54を構成するようにしている。図7は、本実施形態における電極パッド54の製造方法を説明する要部の工程断面図である。
Claims (7)
- チップ実装領域の周囲に電極パッドが形成された実装基板と、
前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に注入されたアンダーフィル材とを備えた半導体装置において、
前記電極パッドは、前記アンダーフィル材の流出防止用のダムとして形成されている
ことを特徴とする半導体装置。 - 前記実装基板上において、前記電極パッドは、前記アンダーフィル材の塗布面よりも高く形成されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記電極パッドは、前記チップ実装領域に対する前記半導体チップの接合温度で溶融しない金属材料で形成されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記電極パッドの内周側縁部には、前記アンダーフィル材の流出を規制するエッジ部が形成されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記実装基板は、半導体チップである
ことを特徴とする請求項1に記載の半導体装置。 - 前記電極パッドには、ボンディングワイヤが接続されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記電極パッドには、はんだバンプが形成されている
ことを特徴とする請求項1に記載の半導体装置。
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JP2006198396A JP5050431B2 (ja) | 2006-07-20 | 2006-07-20 | 半導体装置およびその製造方法 |
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JP2006198396A JP5050431B2 (ja) | 2006-07-20 | 2006-07-20 | 半導体装置およびその製造方法 |
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JP2008028108A true JP2008028108A (ja) | 2008-02-07 |
JP5050431B2 JP5050431B2 (ja) | 2012-10-17 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11145183A (ja) * | 1997-11-07 | 1999-05-28 | Rohm Co Ltd | 半導体装置、およびその製造方法 |
WO2005076352A1 (ja) * | 2004-02-05 | 2005-08-18 | Renesas Technology Corp. | 半導体装置および半導体装置の製造方法 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11145183A (ja) * | 1997-11-07 | 1999-05-28 | Rohm Co Ltd | 半導体装置、およびその製造方法 |
WO2005076352A1 (ja) * | 2004-02-05 | 2005-08-18 | Renesas Technology Corp. | 半導体装置および半導体装置の製造方法 |
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