JP3801188B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP3801188B2 JP3801188B2 JP2004258740A JP2004258740A JP3801188B2 JP 3801188 B2 JP3801188 B2 JP 3801188B2 JP 2004258740 A JP2004258740 A JP 2004258740A JP 2004258740 A JP2004258740 A JP 2004258740A JP 3801188 B2 JP3801188 B2 JP 3801188B2
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Description
また、近年では、携帯電話などの小型化、高性能化および高機能化に対応して、チップサイズパッケージまたはボールグリッドアレイなどの半導体パッケージが携帯電話に搭載されるようになっている。このため、製品落下時の衝撃に対する耐性を向上させるため、ニッケルおよび金メッキをランドの素地上に施すことなく、半田ボールまたは鉛フリーボールを銅の素地上に直接接合させることが行われている。
一方、ニッケルおよび金メッキをランドに施すと、せん断強度、温度サイクル耐性およびボールシェア強度は確保することができるが、(Cu,Ni)6Sn5という合金の引き剥がし方向の強度が弱いため、製品落下時の衝撃に対する耐性が劣化するという問題があった。
また、本発明の一態様に係る半導体装置によれば、前記第1のランドは、前記第2のランドが配置された領域よりも引っ張り応力がかかり易い領域に配置されていることを特徴とする。
これにより、引っ張り応力がかかり易い領域では、引っ張り応力に対する耐性を向上させることが可能となるとともに、せん断応力がかかり易い領域では、せん断応力に対する耐性を向上させることが可能となる。このため、せん断強度の劣化を抑制しつつ、衝撃に対する耐性を向上させることが可能となる。
これにより、半導体パッケージの実装面積を低減することを可能としつつ、せん断強度および衝撃に対する耐性を確保することができ、携帯電話などの携帯機器の小型化、高性能化および高機能化を図ることができる。
これにより、半田ボールまたは鉛フリーボールをメッキ層に安定して接合させることが可能となり、メッキ層との間の接合部分にてせん断強度を確保することが可能となるとともに、半田ボールまたは鉛フリーボールを銅の素地上にも直接接合させることが可能となり、製品落下時の衝撃に対する耐性を向上させることが可能となる。
また、本発明の一態様に係る半導体装置によれば、半導体チップの実装面と異なる領域に配置された第1および第2のランドをキャリア基板上に形成する工程と、第1のランドをレジストで覆った状態でメッキ処理を行うことにより、前記第2のランドの接合面上にメッキ層を形成する工程と、前記キャリア基板上に半導体チップを実装する工程と、前記第1のランド上及び前記メッキ層上に突出電極を形成する工程と、を備え、前記第2のランドは、前記第1のランドを形成する領域よりもせん断応力がかかり易い領域に形成することを特徴とする。
図1は、本発明の一実施形態に係る半導体装置の概略構成を示す断面図である。
図1において、キャリア基板11の表面には導電パターン12cが形成されるとともに、キャリア基板11の裏面には複数のランド12a、12a´が形成されている。ここで、ランド12a´にはメッキ層19を形成するとともに、ランド12aにはメッキ層19が形成されないようにして素地が露出されたままの状態にすることができる。なお、メッキ層19としては、例えば、Pdの単層構造、Auの単層構造、Snの単層構造、Ni/Auの積層構造、Pd/Niの積層構造またはPd/Ni/Auの積層構造を用いることができる。
なお、キャリア基板11としては、例えば、両面基板、多層配線基板、ビルドアップ基板、テープ基板またはフィルム基板などを用いることができ、キャリア基板11の材質としては、例えば、ポリイミド樹脂、ガラスエポキシ樹脂、BTレジン、アラミドとエポキシのコンポジットまたはセラミックなどを用いることができる。また、導電パターン12cおよびランド2、12a、12a´の素材としては、例えば、Cuを用いることができる。また、突出電極18としては、例えば、半田ボールや鉛フリーボールの他、Auバンプ、半田材などで被覆されたCuバンプやNiバンプなどを用いることができ、ボンディングワイヤ16としては、例えば、AuワイヤやAlワイヤなどを用いることができる。また、接着層15としては、例えば、Agペーストなどを用いることができる。鉛フリーボールとしては、Sn−Ag−Cuの合金や、Sn−Ag−Cu−Biの合金を用いてもよい。
ここで、ランド12aの素地としてCuを用いることにより、Ni/Auなどのメッキ層19をランド12aに施した場合に比べて、引き剥がし方向の強度を確保することが可能となり、衝撃に対する耐性を向上させることができる。また、ランド12a´にメッキ層19を形成することにより、メッキ層19がない場合に比べて、せん断強度を向上させることができる。このため、ランド12aを突出電極18に接合させることで、引き剥がし方向の強度を確保することが可能となるとともに、ランド12a´を突出電極18´に接合させることで、せん断強度を確保することが可能となる。この結果、せん断強度の劣化を抑制しつつ、引き剥がし方向の強度を確保することが可能となり、温度サイクル耐性およびボールシェア強度を確保することが可能となるとともに、衝撃に対する耐性を向上させることができる。
図2(a)において、キャリア基板11の両面に銅箔12、12´をそれぞれ貼り付ける。そして、図2(b)に示すように、銅箔12、12´をそれぞれパターニングすることにより、キャリア基板11上に導電パターン12cを形成するとともに、キャリア基板11の裏面にランド12a、12a´を形成する。
次に、図2(c)に示すように、キャリア基板11を貫通させる開口部を形成し、導電性材料を開口部内に埋め込むことにより、キャリア基板11に内部配線12bを形成する。なお、開口部内に埋め込む導電性材料としては、例えば、Cuペーストなどを用いることができる。
次に、図2(e)に示すように、導電パターン12cを覆うマスキングテープMをキャリア基板11上に貼り付ける。また、フォトリソグラフィー技術を用いることにより、ランド12aの接合面を覆うとともに、ランド12a´の接合面を露出させるレジストパターンRをキャリア基板11の裏面に形成する。そして、レジストパターンRが形成されたキャリア基板11のメッキ処理を行うことにより、図2(f)に示すように、ランド12a´上にメッキ層19を選択的に形成する。なお、導電パターン12cにメッキ層を形成する場合、マスキングテープMをキャリア基板11上に貼り付けることなく、キャリア基板11のメッキ処理を行うようにしてもよい。そして、ランド12a´上にメッキ層19が選択的に形成されると、レジストパターンRおよびマスキングテープMをキャリア基板11から除去する。
図3(a)において、キャリア基板21上には、素地が露出されたランド22と接合面にメッキが施されたランド23とが交互に配置されている。これにより、せん断強度が劣るランド22をせん断強度が優れるランド23で取り囲むことが可能となるとともに、引き剥がし方向の強度が劣るランド23を引き剥がし方向の強度が優れるランド22で取り囲むことが可能となる。この結果、せん断強度が劣るランド22の接合部分を、せん断強度が優れるランド23の接合部分で支えることが可能となるとともに、引き剥がし方向の強度が劣るランド23の接合部分を、引き剥がし方向の強度が優れるランド22の接合部分で支えることが可能となり、半導体パケージの小型化を図りつつ、せん断強度の劣化を抑制することが可能となるとともに、衝撃に対する耐性を向上させることが可能となる。
また、図3(c)に示すように、メッキが施されたランド43をキャリア基板41の内側に配置するとともに、素地が露出されたランド42をキャリア基板41の外周部に配置するようにしてもよい。
Claims (8)
- 半導体チップが実装されたキャリア基板と、
前記半導体チップの実装面と異なる領域に配置されるようにして前記キャリア基板に形成され、接合面の素地が露出された第1のランドと、
前記半導体チップの実装面と異なる領域に配置されるようにして前記キャリア基板に形成され、接合面上にメッキ層が積層された第2のランドと、
を備え、
前記第1のランドは、前記第2のランドが配置された領域よりも引っ張り応力がかかり易い領域に配置されることを特徴とする半導体装置。 - 半導体チップが実装されたキャリア基板と、
前記半導体チップの実装面と異なる領域に配置されるようにして前記キャリア基板に形成され、接合面の素地が露出された第1のランドと、
前記半導体チップの実装面と異なる領域に配置されるようにして前記キャリア基板に形成され、接合面上にメッキ層が積層された第2のランドと、
を備え、
前記第2のランドは、前記第1のランドが配置された領域よりもせん断応力がかかり易い領域に配置されることを特徴とする半導体装置。 - 前記第2のランドは、前記第1のランドが配置された領域よりもせん断応力がかかり易い領域に配置されていることを特徴とする請求項1記載の半導体装置。
- 前記第1のランドは、前記第2のランドが配置された領域よりも引っ張り応力がかかり易い領域に配置されていることを特徴とする請求項2記載の半導体装置。
- 前記第1および第2のランドに接合された突出電極と、
前記第1および第2の突出電極を介して前記キャリア基板が搭載されたマザーボードとをさらに備えることを特徴とする請求項1から4のいずれか1項記載の半導体装置。 - 前記第1および第2のランドの素地はCu、前記メッキ層は、Pdの単層構造、Auの単層構造、Snの単層構造、Ni/Auの積層構造、Pd/Niの積層構造またはPd/Ni/Auの積層構造、前記突出電極は半田ボールまたは鉛フリーボールであることを特徴とする請求項5記載の半導体装置。
- 半導体チップの実装面と異なる領域に配置された第1および第2のランドをキャリア基板上に形成する工程と、
第1のランドをレジストで覆った状態でメッキ処理を行うことにより、前記第2のランドの接合面上にメッキ層を形成する工程と、
前記キャリア基板上に半導体チップを実装する工程と、
前記第1のランド上及び前記メッキ層上に突出電極を形成する工程と、
を備え、
前記第1のランドは、前記第2のランドを形成する領域よりも引っ張り応力がかかり易い領域に形成することを特徴とする半導体装置の製造方法。 - 半導体チップの実装面と異なる領域に配置された第1および第2のランドをキャリア基板上に形成する工程と、
第1のランドをレジストで覆った状態でメッキ処理を行うことにより、前記第2のランドの接合面上にメッキ層を形成する工程と、
前記キャリア基板上に半導体チップを実装する工程と、
前記第1のランド上及び前記メッキ層上に突出電極を形成する工程と、
を備え、
前記第2のランドは、前記第1のランドを形成する領域よりもせん断応力がかかり易い領域に形成することを特徴とする半導体装置の製造方法。
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JP3488888B2 (ja) * | 2000-06-19 | 2004-01-19 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ用回路基板の製造方法及びそれを用いた半導体パッケージ用回路基板 |
JP3656590B2 (ja) | 2001-10-16 | 2005-06-08 | 日立電線株式会社 | 半導体装置用テープキャリアの製造方法 |
JP3897596B2 (ja) * | 2002-01-07 | 2007-03-28 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置と配線基板との実装体 |
JP3942952B2 (ja) | 2002-05-10 | 2007-07-11 | 松下電器産業株式会社 | リフロー半田付け方法 |
US7138711B2 (en) * | 2002-06-17 | 2006-11-21 | Micron Technology, Inc. | Intrinsic thermal enhancement for FBGA package |
JP2004158737A (ja) | 2002-11-08 | 2004-06-03 | Hitachi Cable Ltd | 配線板の製造方法 |
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2004
- 2004-09-06 JP JP2004258740A patent/JP3801188B2/ja not_active Expired - Fee Related
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2005
- 2005-08-18 CN CNB200510091529XA patent/CN100390982C/zh not_active Expired - Fee Related
- 2005-08-30 US US11/213,788 patent/US7372167B2/en not_active Expired - Fee Related
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US20060049510A1 (en) | 2006-03-09 |
CN100390982C (zh) | 2008-05-28 |
JP2006073954A (ja) | 2006-03-16 |
CN1747161A (zh) | 2006-03-15 |
US7372167B2 (en) | 2008-05-13 |
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