CN100390982C - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN100390982C
CN100390982C CNB200510091529XA CN200510091529A CN100390982C CN 100390982 C CN100390982 C CN 100390982C CN B200510091529X A CNB200510091529X A CN B200510091529XA CN 200510091529 A CN200510091529 A CN 200510091529A CN 100390982 C CN100390982 C CN 100390982C
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terminal pad
mentioned
carrier substrate
semiconductor device
zone
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CN1747161A (zh
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大槻哲也
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

既能抑制半导体装置的剪切强度劣化，又能提高耐冲击性。在载体基板11的背面上形成多个连接盘(12a、12a’)，在连接盘(12a’)上形成镀层(19)，在连接盘(12a)上不形成镀层(19)，而形成基体露出的状态，通过将突出电极(18、18’)分别与连接盘(12a、12a’)接合，使突出电极(18)直接与连接盘(12a)的基体接合，使突出电极(18’)与形成镀层(19)的连接盘(12a’)接合。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明是关于半导体装置及半导体装置的制造方法，尤其是适宜适用于芯片尺寸封装(CSP)或球状格栅阵列(BGA)等的方法。
背景技术
在以往的半导体装置中，为了获得半导体封装的小型化，有使用芯片尺寸封装或球状格栅阵列的方法。在这些芯片尺寸封装或球状格栅阵列中，通过使用安装了半导体芯片的载体基板，可构成半导体封装。因此，在将安装了半导体芯片的载体基板搭载在母板上时，通过使用焊锡球或无铅球，将载体基板与母板接合在一起。为了使焊锡球或无铅球与载体基板或母板接合，而在载体基板或母板上形成连接盘(land)。
在此，作为连接盘的材料，一般使用铜。为了确保温度循环性和球的剪切强度，而在连接盘的底面上实施有镀镍或镀金。
进年来，与移动电话机等的小型化、高性能化和高功能化相适应，移动电话机中都已搭载了芯片尺寸封装或球状格栅阵列等半导体封装。由此，为了提高制品降落时的耐冲击性，不再对连接盘的底面实施镀镍或镀金，而是将焊锡球或无铅球直接与铜的底面进行接合。
另外，例如，专利文献1中公开了一种在温度循环时，为防止焊锡球发生破裂，而将焊料抗蚀剂层开口部的端部形状形成为锥状的方法。
[专利文献1]特开平10-340972号公报
然而，将焊锡球或无铅球与铜的底面直接接合时，虽然提高了制品落下时的耐冲击性，但出现所谓剪切强度(横向强度)、耐温度循环性和球均摊(ball share)强度劣化的问题。
另一方面，对连接盘实施镀镍和镀金时，虽然能确保剪切强度、耐温度循环性和球均摊强度，但由于所谓(Cu，Ni)6Sn5合金的剥离方向的强度弱，所以出现所谓制品落下时耐冲击性低劣的问题。
发明内容
因此，本发明的目的是提供一种既能抑制剪切强度劣化，又能提高耐冲击性的半导体装置和半导体装置的制造方法。
为了解决上述课题，根据本发明的一种形态的半导体装置，其特征在于，具备：安装了半导体芯片的载体基板；配置在与上述半导体芯片安装面不同的区域内，以在上述载体基板上形成、并露出了接合底面的第1连接盘；和配置在与上述半导体芯片安装面不同的区域内，以在上述载体基板上形成、并在接合面上层叠了镀层的第2连接盘，所述第1连接盘被配置在所述载体基板的四角。
据此，通过将第1连接盘与第1突出电极接合，可确保剥离方向的强度，同时，通过将第2连接盘与第2突出电极接合，可确保剪切强度。由此，既能抑制剪切强度劣化，又能确保剥离方向的强度，还能确保耐温度循环性和球均摊强度，同时也提高了耐冲击性。
另外，根据本发明的一种形态的半导体装置，其特征是上述第1连接盘配置在上述载体基板中更容易产生拉伸应力的区域内，而上述第2连接盘配置在上述载体基板中更容易产生剪切应力的区域内。
据此，在容易产生拉伸应力的区域内，可提高对拉伸应力的耐性，同时，在容易产生剪切应力的区域内，可提高对剪切应力的耐性。由此，既能抑制剪切强度的劣化，又能提高对冲击的耐性。
另外，根据本发明的一种形态的半导体装置，其特征是还具有与上述第1和第2连接盘接合的突出电极；和隔着上述第1和第2突出电极，搭载了上述载体基板的母板。
据此，既能减小半导体封装的安装面积，又能确保剪切强度和对冲击的耐性，并能使移动电话机等携带设备获得小型化、高性能化和高功能化。
根据本发明的一种形态的半导体装置，其特征是上述第1和第2连接盘的底面是Cu，上述镀层是Pd的单层结构、Au的单层结构、Sn的单层结构、Ni/Au的层叠结构、Pd/Ni的层叠结构、或者Pd/Ni/Au的层叠结构、上述突出电极是焊锡球或无铅球。
据此，可使焊锡球或无铅球能稳定地与镀层接合，在与镀层间的接合部分，可确保剪切强度，同时也能使焊锡球或无铅球与铜底面直接接合，还能提高制品落下时的耐冲击性。
另外，根据本发明的一种形态的半导体制造方法，其特征是具备以下工序：即，将配置在与半导体芯片安装面不同区域内的第1和第2连接盘，在载体基板上形成的工序；在由抗蚀剂层覆盖住第1连接盘的状态下，进行电镀处理，在上述第2连接盘的接合面上形成镀层的工序；和在上述载体基板上安装半导体芯片的工序。
据此，在第2连接盘的接合面上，可有选择地形成镀层，通过将第1突出电极与第1连接盘的底面接合之后，可将第2突出电极接合在设有镀层的第2连接盘上。由此，既能获得半导体封装小型化，又能抑制剪切强度劣化，还能提高耐冲击性。
根据本发明的一种形态的半导体装置的制造方法，其特征是还具备隔着分别与上述第1和第2连接盘接合的突出电极，将上述安装了半导体芯片的载体基板搭载在母板上的工序。
据此，既能减小半导体封装的安装面积，又能确保剪切强度和耐冲击性，还能使移动电话机等携带设备获得小型化、高性能化、和高功能化。
附图说明
图1是表示涉及本发明的一种实施方式的半导体装置的简要构成的剖面图。
图2是表示涉及本发明的一种实施方式的半导体装置的制造方法的剖面图。
图3是表示形成了镀层的连接盘的配置方法的平面图。图中：
1-母板，2、12a、12a’、22、32、42、52、23、33、43、53-连接盘，11、21、32、41、51-载体基板，12b-内部配线，12c-导电图案，12、12’-铜箔，13-焊料抗蚀剂层，14-半导体芯片，14a-焊盘电极，15-连接层，16-连接线，17-密封树脂，18、18’-突出电极，19-镀层
具体实施方式
以下参照附图说明涉及本发明实施方式的半导体装置及其制造方法。
图1是表示涉及本发明一种实施方式的半导体装置的简要构成的剖面图。
图1中，在载体基板11的表面上形成导电图案12c，同时在载体基板11的背面上形成多个连接盘12a、12a’。在连接盘12a’上形成镀层19，同时，在连接盘12a上，不形成镀层19，而是直接露出基体(镀前表面)的状态。而且，作为镀层19，例如可采用Pd的单层结构、Au的单层结构、Su的单层结构、Ni/Au的层叠结构、Pd/Ni的层叠结构、或者Pd/Ni/Au的层叠结构。
另外，在载体基板11内形成内部配线12b，导电图案12c和连接盘12a、12a’通过内部配线连接。在载体基板11上形成覆盖连接盘12a、12a’周围的焊料抗蚀剂层13。在载体基板11上，通过接合层15面朝上安装半导体芯片。在半导体芯片14上设置焊盘电极(pad electrode)14a，焊盘电极14a通过焊接线16与导电图案12c连接。安装在载体基板11上的半导体芯片14，用密封树脂17密封住。而且，在用密封树脂17密封半导体芯片14时，例如，使用环氧树脂等热固化树脂进行模具成形等。
另外，设在载体基板11之背面的连接盘12a、12a’上，分别设置有用于在母板1上安装载体基板11的突出电极18、18’。分别将突出电极18、18’与设在母板1上的连接盘2进行接合，而将载体基板11安装在母板1上。
另外，作为载体基板11，例如可使用两面基板、多层配线基板、组合基板、带式基板或薄膜基板等，作为载体基板11的材质，例如可使用聚酰亚胺树脂、玻璃环氧树脂、BT树脂、芳族聚酰胺和环氧的混合物或陶瓷等。另外，作为导电图案12c和连接盘2、12a、12a’的材质，例如可使用Cu。作为突出电极18，例如，除了焊锡球和无铅球外，还可使用Au凸起、用焊锡等被覆的Cu凸起和Ni凸起等，作为焊接线16，例如可使用Au和Al线等。作为接合层15，例如可使用Ag糊等。作为无铅球，最好使用Sn-Ag-Cu的合金、Sn-Ag-Cu-Bi的合金。
另外，除了在载体基板11上朝上安装半导体芯片14的方法外，还可以在载体基板11上倒装片安装半导体芯片14。例如，在载体基板11上倒装片安装半导体芯片14时，可使用ACF(Anisotropic ConductiveFilm)、NCF(Nonconductive Film)接合、ACP(Anisotropic ConductivePaste)接合、NCP(Nonconductive Conductive Paste)接合等压接接合，也可用焊锡接合和合金接合等金属接合。
然后，通过将突出电极18、18’分别与连接盘12a、12a’接合，可将突出电极18直接接合在连接盘12a的底面上，将突出电极18’接合在形成镀层19的连接盘12a’上。
作为连接盘12a的基体使用Cu，与对连接盘12a实施Ni/Au等镀层19的情况比较，可确保剥离方向的强度，并能提高耐冲击性。通过在连接盘12a’上形成镀层19，与没有镀层19的情况比较，可提高剪切强度。由此，通过将连接盘12a与突出电极18接合，可确保剥离方向的强度，同时，通过将连接盘12a’与突出电极18’接合，可确保剪切强度。结果，既能抑制剪切强度劣化，又能确保剥离方向的强度，既能确保耐温度循环性和球均摊强度，又能提高耐冲击性。
在将焊锡球和无铅球与Cu底面的连接盘12a接合时，也可在连接盘12a上形成CuOSP等有机皮膜。在将突出电极与设在母板1上的连接盘2接合时，可将突出电极18直接与连接盘2的基体接合。或者，对于设在母板1上的连接盘2，也可设置实施镀的连接盘和未实施镀的连接盘。
另外，连接盘12a配置在载体基板11上易于产生拉伸应力的区域内，连接盘12a’最好配置在载体基板11上易于产生剪切应力的区域内。最好是将连接盘12a配置在比设置连接盘12a’的区域更容易产生拉伸应力的区域内，将连接盘12a’配置在比设置连接盘12a的区域更容易产生剪切应力的区域内。
图2是表示涉及本发明一种实施方式的半导体装置制造方法的剖面图。
图 2(a)中，在载体基板11的两个面上分别贴合铜箔12、12’。如图2(b)所示，通过将铜箔12、12’分别形成图案，在载体基板11上形成导电图案12c，同时在载体基板11的背面上形成连接盘12a、12a’。
另外，在载体基板11上形成导电图案12c时，可使用光刻技术，在铜箔12上形成与导电图案12c形状相对应的第1光致抗蚀剂膜。将第1光致抗蚀剂膜作为掩模，对铜箔12进行蚀刻，可在载体基板11上形成导电图案12c。而且，在载体基板11的背面上形成连接盘12a、12a’时，也可使用光刻技术，在铜箔12’上形成与连接盘12a、12a’形状相对应的第2光致抗蚀剂膜。同样将第2光致抗蚀剂膜作掩模，对铜箔12’进行蚀刻，可在载体基板11的背面上形成连接盘12a、12a’。
在导电图案12c上，例如也可形成Ni/Au层叠结构的镀层。连接盘12a的厚度，例如为10～30μm，连接盘12a的直径，例如为300～400μm。
接着，如图2(c)所示，形成贯通载体基板11的开口部，通过将导电性材料埋入开口部内，在载体基板11上形成内部配线12b。作为埋入开口部内的导电性材料，例如可用Cu糊等。
接着，如图2(d)所示，在载体基板11上形成被覆连接盘12a之周围的焊料抗蚀剂层13。在载体基板11上形成焊料抗蚀剂层13时，在载体基板11上涂布绝缘性树脂，介于构成的掩模，覆盖在连接盘12a、12a’上。
接着，如图2(e)所示，在载体基板11上贴合标识带M，覆盖住导电图案12c。而且，利用光刻技术，在载体基板11的背面上，形成覆盖连接盘12a的接合面，同时使连接盘12a’的接合面露出的抗蚀剂膜图案R。通过对形成抗蚀剂膜图案R的载体基板11进行电镀处理，如图2(f)所示，在连接盘12a’上有选择地形成镀层19。而且，在导电图案12c上形成镀层时，不必在载体基板11上贴合标识带M，就可对载体基板11进行电镀处理。在连接盘12a’上有选择地形成镀层19时从载体基板11上除去抗蚀剂膜图案R和标识带M。
接着，如图2(g)所示，通过接合层15，将半导体芯片14安装在载体基板11上。这样，通过焊接线16将焊接电极14a与导电图案12c连接后，用密封树脂17将半导体芯片14封住。然后，如图1所示，通过使突出电极18与连接盘2、12a接合，同时使突出电极18’与连接盘2、12a’接合，将载体基板11安装在母板上。
图3是表示涉及本发明实施方式的形成了镀层的连接盘配置方法的平面图。
图3(a)中，在载体基板21上交替配置露出底面的的连接盘22，和对接合面实施电镀的连接盘23，据此，能用剪切强度优良的连接盘23围绕着剪切强度较差的连接盘22，同时还能用剥离方向强度优良的连接盘22围绕着剥离方向强度较差的连接盘23。结果，剪切强度较差的连接盘22的接合部分，可由剪切强度优良的连接盘23的连接盘23的接合部分支撑着，同时，剥离方向强度较差的连接盘23的接合部分，可由剥离方向强度优良的连接盘22的接合部分支撑着，所以既能获得半导体封装小型化，又能抑制剪切强度劣化，还能提高耐冲击性。
如图3(b)所示，将实施电镀的连接盘33配置在载体基板31上，同时将露出基体的连接盘32配置在载体基板31的四个角处。
如图3(c)所示，将实施电镀的连接盘43配置在载体基板41的内侧，同时将露出基体的连接盘42配置在载体基板41的外周部分。
另外，如图3(d)所示，将实施电镀的连接盘53配置在载体基板51上，同时将露出基体的连接盘52配置在载体基板51的对角线上。

Claims (10)

1.一种半导体装置，其特征在于，具备：
安装了半导体芯片的载体基板；
以配置在与上述半导体芯片的安装面不同的区域内的方式，在上述载体基板上形成、并露出接合面基体的第1连接盘；和
以配置在与上述半导体芯片的安装面不同的区域内的方式，在上述载体基板上形成、并在接合面上层叠了镀层的第2连接盘，
所述第1连接盘被配置在所述载体基板的四角。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第1连接盘和所述第2连接盘交互配置。
3.根据权利要求1所述的半导体装置，其特征在于，
所述第1连接盘被配置在所述载体基板的外周部，所述第2连接盘被配置在所述载体基板的内侧。
4.根据权利要求1所述的半导体装置，其特征在于，
所述第1连接盘被配置在所述载体基板的对角线上。
5.根据权利要求1到4任何一项所述的半导体装置，其特征在于，
上述第1连接盘配置在上述载体基板中更易于产生拉伸应力的区域内，上述第2连接盘配置在上述载体基板中更易于产生剪切应力的区域内。
6.根据权利要求1到4任何一项所述的半导体装置，其特征在于，
上述第1连接盘配置在比上述配置了第2连接盘区域更易于产生拉伸应力的区域内，
上述第2连接盘配置在比上述配置了第1连接盘的区域更易于产生剪切应力的区域内。
7.根据权利要求1～4的任一项中所述的半导体装置，其特征在于，还具备：
接合于上述第1和第2连接盘的突出电极；和
隔着上述第1和第2突出电极，搭载了上述载体基板的母板。
8.根据权利要求7所述的半导体装置，其特征在于，
上述第1和第2连接盘的底面是Cu，上述镀层是Pd的单层结构、Au的单层结构、Sn的单层结构、Ni/Au的层叠结构、Pd/Ni的层叠结构、或Pd/Ni/Au的层叠结构，上述突出电极是焊锡球或无铅球。
9.一种半导体装置的制造方法，其特征在于，具备：
在载体基板上形成配置在与半导体芯片安装面不同区域内的第1和第2连接盘的工序；
通过在用保护膜覆盖第1连接盘的状态下进行电镀处理，在上述第2连接盘的接合面上形成镀层的工序；和
在上述载体基板上安装半导体芯片的工序。
10.根据权利要求9所述的半导体装置制造方法，其特征在于，
还具备隔着分别与上述第1和第2连接盘接合的突出电极，将安装了上述半导体芯片的载体基板搭载在母板上的工序。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013030712A (ja) * 2011-07-29 2013-02-07 Toshiba Corp 半導体モジュールおよび半導体モジュールの製造方法
US8945990B2 (en) * 2012-04-24 2015-02-03 Infineon Technologies Ag Chip package and method of forming the same
KR102009727B1 (ko) 2012-11-26 2019-10-22 삼성디스플레이 주식회사 표시 장치, 표시 장치의 제조 방법 및 표시 장치를 제조하기 위한 캐리어 기판
CN103227160B (zh) * 2013-03-18 2016-03-16 三星半导体(中国)研究开发有限公司 一种混合的表面镀层及其制造方法
JP6300579B2 (ja) * 2014-03-05 2018-03-28 キヤノン株式会社 実装部材、電子部品およびモジュールの製造方法
US10916914B2 (en) * 2017-05-17 2021-02-09 Mitsubishi Electric Corporation Light module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796163A (en) * 1997-05-23 1998-08-18 Amkor Technology, Inc. Solder ball joint
JP2000082762A (ja) * 1999-06-28 2000-03-21 Nec Corp 半導体装置
CN1289147A (zh) * 1999-09-16 2001-03-28 日本电气株式会社 树脂封装的半导体器件
US6476331B1 (en) * 2000-06-19 2002-11-05 Amkor Technology, Inc. Printed circuit board for semiconductor package and method for manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10335533A (ja) 1997-05-26 1998-12-18 Ritsuei Kagi Kofun Yugenkoshi 増強型ソルダーボール排列構造装置
JP3210881B2 (ja) 1997-06-05 2001-09-25 ソニーケミカル株式会社 Ｂｇａパッケージ基板
JP3656590B2 (ja) 2001-10-16 2005-06-08 日立電線株式会社 半導体装置用テープキャリアの製造方法
JP3897596B2 (ja) * 2002-01-07 2007-03-28 日本テキサス・インスツルメンツ株式会社 半導体装置と配線基板との実装体
JP3942952B2 (ja) 2002-05-10 2007-07-11 松下電器産業株式会社 リフロー半田付け方法
US7138711B2 (en) * 2002-06-17 2006-11-21 Micron Technology, Inc. Intrinsic thermal enhancement for FBGA package
JP2004158737A (ja) 2002-11-08 2004-06-03 Hitachi Cable Ltd 配線板の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796163A (en) * 1997-05-23 1998-08-18 Amkor Technology, Inc. Solder ball joint
JP2000082762A (ja) * 1999-06-28 2000-03-21 Nec Corp 半導体装置
CN1289147A (zh) * 1999-09-16 2001-03-28 日本电气株式会社 树脂封装的半导体器件
US6476331B1 (en) * 2000-06-19 2002-11-05 Amkor Technology, Inc. Printed circuit board for semiconductor package and method for manufacturing the same

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