JP5259560B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5259560B2 JP5259560B2 JP2009272150A JP2009272150A JP5259560B2 JP 5259560 B2 JP5259560 B2 JP 5259560B2 JP 2009272150 A JP2009272150 A JP 2009272150A JP 2009272150 A JP2009272150 A JP 2009272150A JP 5259560 B2 JP5259560 B2 JP 5259560B2
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- Prior art keywords
- chip
- wiring
- wiring board
- chips
- resin
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Description
表面、前記表面に形成された表面側電極パッド、前記表面側電極パッドに形成されたメッキ膜、前記表面とは反対側の裏面、および前記裏面に形成された裏面側電極パッドを有する配線基板と、
主面、および前記主面に形成されたボンディングパッドを有し、前記配線基板の前記表面上に搭載された半導体チップと、
前記半導体チップの前記ボンディングパッドと前記配線基板の前記表面側電極パッドを電気的に接続する導電性部材と、
前記半導体チップを封止する樹脂と、
前記裏面側電極パッドに接続された半田材と、
を含み、
前記配線基板は、前記表面と前記裏面との間に位置し、かつ最も周縁部側に位置し、かつ前記樹脂で覆われない第1側面と、前記第1側面よりも内側に位置し、かつ前記樹脂で覆われた第2側面と、前記表面側電極パッドと電気的に接続され、かつ前記第2側面に向かって延在する電解メッキ用の配線とを有し、
前記配線基板の前記第2側面から露出する前記電解メッキ用の配線の端面は、前記樹脂で覆われており、
前記裏面側電極パッドは、前記配線基板の前記第1側面よりも内側に位置しており、
前記配線基板のうち、前記第1側面を有する第1部分の厚さは、前記第1部分よりも内側に位置し、かつ前記第2側面を有する第2部分の厚さよりも薄い。
図1は、本実施形態の半導体装置の上面を示す平面図、図2は、この半導体装置の断面図、図3は、この半導体装置の下面を示す平面図である。
本実施形態の半導体装置の製造方法を図27〜図34を用いて工程順に説明する。
本実施形態の半導体装置の製造方法を図35〜図37を用いて工程順に説明する。
図38は、本実施形態の半導体装置を示す断面図、図39は、図38の一部を拡大して示す断面図である。
2A、2B、2C、2D 半導体チップ
3 モールド樹脂
4 Auバンプ
5 配線
6 アンダーフィル樹脂
6a 樹脂テープ
7 接着剤
8 Auワイヤ
9 ボンディングパッド
10 電極パッド
11 半田バンプ
11t テストピン
12 ソルダレジスト
13 ボンディングパッド
14 ウエハ
15 ダイシングテープ
16 ダム領域
20 半田バンプ
21 Cu配線
100 マルチ配線基板
101 溝
102 ヒートツール
Claims (6)
- 表面、前記表面に形成された表面側電極パッド、前記表面側電極パッドに形成されたメッキ膜、前記表面とは反対側の裏面、および前記裏面に形成された裏面側電極パッドを有する配線基板と、
主面、および前記主面に形成されたボンディングパッドを有し、前記配線基板の前記表面上に搭載された半導体チップと、
前記半導体チップの前記ボンディングパッドと前記配線基板の前記表面側電極パッドを電気的に接続する導電性部材と、
前記半導体チップを封止する樹脂と、
前記裏面側電極パッドに接続された半田材と、
を含み、
前記配線基板は、前記表面と前記裏面との間に位置し、かつ最も周縁部側に位置し、かつ前記樹脂で覆われない第1側面と、前記第1側面よりも内側に位置し、かつ前記樹脂で覆われた第2側面と、前記表面側電極パッドと電気的に接続され、かつ前記第2側面に向かって延在する電解メッキ用の配線とを有し、
前記配線基板の前記第2側面から露出する前記電解メッキ用の配線の端面は、前記樹脂で覆われており、
前記裏面側電極パッドは、前記配線基板の前記第1側面よりも内側に位置しており、
前記配線基板のうち、前記第1側面を有する第1部分の厚さは、前記第1部分よりも内側に位置し、かつ前記第2側面を有する第2部分の厚さよりも薄いことを特徴とする半導体装置。 - 前記電解メッキ用の配線は、前記表面側電極パッドと一体に形成されていることを特徴とする請求項1記載の半導体装置。
- 前記配線基板は、複数の配線層を有し、
前記電解メッキ用の配線および前記表面側電極パッドは、前記配線基板の前記表面に貼り付けたCu箔をエッチングすることによって形成されたものであり、
前記電解メッキ用の配線および前記表面側電極パッドは、前記複数の配線層のうちの最上層の配線層の一部であることを特徴とする請求項2記載の半導体装置。 - 前記メッキ膜は、Auメッキ膜を含むことを特徴とする請求項3記載の半導体装置。
- 前記第1側面は、前記配線基板を切断することによって形成された切断面であることを特徴とする請求項1記載の半導体装置。
- 前記配線基板の前記表面には、表面側絶縁膜が形成されており、
前記配線基板の前記裏面には、裏面側絶縁膜が形成されており、
前記表面側電極パッドの表面は、前記表面側絶縁膜から露出しており、
前記電解メッキ用の配線の表面は、前記表面側絶縁膜で覆われており、
前記電解メッキ用の配線の前記端面は、前記表面側絶縁膜から露出しており、
前記裏面側電極パッドの表面は、前記裏面側絶縁膜から露出しており、
前記導電性部材は、前記表面側電極パッドの前記表面に接続されており、
前記半田材は、前記裏面側電極パッドの前記表面に接続されていることを特徴とする請求項1記載の半導体装置。
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US7042073B2 (en) | 2001-06-07 | 2006-05-09 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
WO2003010825A1 (en) * | 2001-07-24 | 2003-02-06 | Seiko Epson Corporation | Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipmen |
US6979904B2 (en) * | 2002-04-19 | 2005-12-27 | Micron Technology, Inc. | Integrated circuit package having reduced interconnects |
US7061088B2 (en) * | 2002-10-08 | 2006-06-13 | Chippac, Inc. | Semiconductor stacked multi-package module having inverted second package |
JP3844467B2 (ja) * | 2003-01-08 | 2006-11-15 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP4068974B2 (ja) * | 2003-01-22 | 2008-03-26 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4149289B2 (ja) | 2003-03-12 | 2008-09-10 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4484444B2 (ja) * | 2003-04-11 | 2010-06-16 | 三洋電機株式会社 | 回路装置の製造方法 |
US7371607B2 (en) * | 2003-05-02 | 2008-05-13 | Seiko Epson Corporation | Method of manufacturing semiconductor device and method of manufacturing electronic device |
US7920723B2 (en) * | 2005-11-18 | 2011-04-05 | Tessera Technologies Ireland Limited | Two stage detection for photographic eye artifacts |
JP4398225B2 (ja) * | 2003-11-06 | 2010-01-13 | 株式会社ルネサステクノロジ | 半導体装置 |
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Publication number | Publication date |
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US20120264240A1 (en) | 2012-10-18 |
US8278147B2 (en) | 2012-10-02 |
US7531441B2 (en) | 2009-05-12 |
EP1401020A4 (en) | 2007-12-19 |
US20110171780A1 (en) | 2011-07-14 |
US20060189031A1 (en) | 2006-08-24 |
US8524534B2 (en) | 2013-09-03 |
US20100015760A1 (en) | 2010-01-21 |
KR100868419B1 (ko) | 2008-11-11 |
CN100407422C (zh) | 2008-07-30 |
KR20040023608A (ko) | 2004-03-18 |
CN1516898A (zh) | 2004-07-28 |
JPWO2002103793A1 (ja) | 2004-10-07 |
JP2011018935A (ja) | 2011-01-27 |
US20090189268A1 (en) | 2009-07-30 |
CN101303984B (zh) | 2012-02-15 |
TW586201B (en) | 2004-05-01 |
WO2002103793A1 (fr) | 2002-12-27 |
US8952527B2 (en) | 2015-02-10 |
US20040164385A1 (en) | 2004-08-26 |
US7042073B2 (en) | 2006-05-09 |
EP1401020A1 (en) | 2004-03-24 |
US9613922B2 (en) | 2017-04-04 |
US8653655B2 (en) | 2014-02-18 |
US7859095B2 (en) | 2010-12-28 |
JP2010050489A (ja) | 2010-03-04 |
US20150108639A1 (en) | 2015-04-23 |
JP5420505B2 (ja) | 2014-02-19 |
JP4149377B2 (ja) | 2008-09-10 |
US20130320571A1 (en) | 2013-12-05 |
US20140117541A1 (en) | 2014-05-01 |
CN101303984A (zh) | 2008-11-12 |
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