JPS6423562A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6423562A
JPS6423562A JP17888887A JP17888887A JPS6423562A JP S6423562 A JPS6423562 A JP S6423562A JP 17888887 A JP17888887 A JP 17888887A JP 17888887 A JP17888887 A JP 17888887A JP S6423562 A JPS6423562 A JP S6423562A
Authority
JP
Japan
Prior art keywords
cut
electrolysis plating
moisture
printed wiring
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17888887A
Other languages
Japanese (ja)
Inventor
Hideo Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17888887A priority Critical patent/JPS6423562A/en
Publication of JPS6423562A publication Critical patent/JPS6423562A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce an invasion speed of moisture from outside so as to improve damp-proof performance, by forming a synthetic resin protective layer on a cut-out part which is formed by mechanically cutting one part of a wiring pattern and one part of a resin board. CONSTITUTION:A part, except a region where electrolysis plating is performed on a printed wiring board 1, is coated with a solder resist 9, and next it is provided with the electrolysis plating of nickel and gold. One part of a wiring pattern for electrolysis plating 10 and one part of the printed wiring board 1 are mechanically cut out, and next a protection layer 11 made of a solder resist, epoxy resin, or the like is formed on these cut-out part. This cutting position is in the middle of the land of the lead pin and the peripheral part of the printed wiring substrate. This cutting operation is preferably performed as widely as possible. When the cut-out part is formed on the wiring pattern for electrolysis plating and next the protective layer is formed on the cut-out part in this way, an invasion speed of moisture from outside is reduced and so an occurrence time of troubles caused by the invasion of moisture can be delayed.
JP17888887A 1987-07-20 1987-07-20 Semiconductor device Pending JPS6423562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17888887A JPS6423562A (en) 1987-07-20 1987-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17888887A JPS6423562A (en) 1987-07-20 1987-07-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6423562A true JPS6423562A (en) 1989-01-26

Family

ID=16056453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17888887A Pending JPS6423562A (en) 1987-07-20 1987-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6423562A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050489A (en) * 2001-06-07 2010-03-04 Renesas Technology Corp Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050489A (en) * 2001-06-07 2010-03-04 Renesas Technology Corp Semiconductor device
JP2011018935A (en) * 2001-06-07 2011-01-27 Renesas Electronics Corp Method of manufacturing semiconductor device
US8524534B2 (en) 2001-06-07 2013-09-03 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US8653655B2 (en) 2001-06-07 2014-02-18 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US8952527B2 (en) 2001-06-07 2015-02-10 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US9613922B2 (en) 2001-06-07 2017-04-04 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof

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