JP2008091954A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2008091954A JP2008091954A JP2007333205A JP2007333205A JP2008091954A JP 2008091954 A JP2008091954 A JP 2008091954A JP 2007333205 A JP2007333205 A JP 2007333205A JP 2007333205 A JP2007333205 A JP 2007333205A JP 2008091954 A JP2008091954 A JP 2008091954A
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Abstract
【解決手段】マルチチップモジュールの製造方法は、複数のパッケージ基板形成領域と、それらの間に配置されたダイシング領域と、前記複数のパッケージ基板形成領域および前記ダイシング領域に連続して形成された複数の配線と、前記複数の配線とそれぞれ電気的に接続された複数のボンディングパッドとを有する配線基板を準備する工程、前記ダイシング領域に形成された前記複数の配線を除去する工程、複数の電極が形成された主面を有する複数個の半導体チップを前記複数のパッケージ基板形成領域上に搭載する工程、前記複数の電極と前記複数のボンディングパッドをそれぞれ電気的に接続する工程、前記複数の半導体チップを樹脂で封止する工程、前記ダイシング領域をダイシングブレードにより切断する工程を含む。
【選択図】図26
Description
(a)複数のパッケージ基板形成領域と、前記複数のパッケージ基板形成領域の間に配置されたダイシング領域と、前記複数のパッケージ基板形成領域および前記ダイシング領域に連続して形成された複数の配線と、前記複数の配線とそれぞれ電気的に接続された複数のボンディングパッドとを有する配線基板を準備する工程、
(b)前記(a)工程の後、前記ダイシング領域に形成された前記複数の配線を除去する工程、
(c)前記(b)工程の後、複数の電極が形成された主面を有する半導体チップを複数個準備し、前記複数のパッケージ基板形成領域上に前記複数の半導体チップをそれぞれ搭載する工程、
(d)前記(c)工程の後、前記複数の電極と前記複数のボンディングパッドをそれぞれ電気的に接続する工程、
(e)前記(d)工程の後、前記複数の半導体チップを樹脂で封止する工程、
(f)前記(e)工程の後、前記ダイシング領域をダイシングブレードにより切断する工程。
図1は、本実施形態の半導体装置の上面を示す平面図、図2は、この半導体装置の断面図、図3は、この半導体装置の下面を示す平面図である。
本実施形態の半導体装置の製造方法を図27〜図34を用いて工程順に説明する。
本実施形態の半導体装置の製造方法を図35〜図37を用いて工程順に説明する。
図38は、本実施形態の半導体装置を示す断面図、図39は、図38の一部を拡大して示す断面図である。
2A、2B、2C、2D 半導体チップ
3 モールド樹脂
4 Auバンプ
5 配線
6 アンダーフィル樹脂
6a 樹脂テープ
7 接着剤
8 Auワイヤ
9 ボンディングパッド
10 電極パッド
11 半田バンプ
11t テストピン
12 ソルダレジスト
13 ボンディングパッド
14 ウエハ
15 ダイシングテープ
16 ダム領域
20 半田バンプ
21 Cu配線
100 マルチ配線基板
101 溝
102 ヒートツール
Claims (5)
- (a)複数のパッケージ基板形成領域と、前記複数のパッケージ基板形成領域の間に配置されたダイシング領域と、前記複数のパッケージ基板形成領域および前記ダイシング領域に連続して形成された複数の配線と、前記複数の配線とそれぞれ電気的に接続された複数のボンディングパッドとを有する配線基板を準備する工程、
(b)前記(a)工程の後、前記ダイシング領域に形成された前記複数の配線を除去する工程、
(c)前記(b)工程の後、複数の電極が形成された主面を有する半導体チップを複数個準備し、前記複数のパッケージ基板形成領域上に前記複数の半導体チップをそれぞれ搭載する工程、
(d)前記(c)工程の後、前記複数の電極と前記複数のボンディングパッドをそれぞれ電気的に接続する工程、
(e)前記(d)工程の後、前記複数の半導体チップを樹脂で封止する工程、
(f)前記(e)工程の後、前記ダイシング領域をダイシングブレードにより切断する工程、
を含むことを特徴とする半導体装置の製造方法。 - 前記複数の配線及び前記複数のボンディングパッドのそれぞれには、電解メッキ法によりNiおよびAuが形成されていることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記(b)工程では、前記ダイシング領域に形成された前記複数の配線を、ルータにより除去することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記(e)工程において、前記ダイシングブレードの幅は、前記ルータの幅よりも狭いことを特徴とする請求項3記載の半導体装置の製造方法。
- 前記(b)工程の後で、かつ前記(c)工程の前に、前記複数のパッケージ基板形成領域のそれぞれの導通試験を行うことを特徴とする請求項1記載の半導体装置の製造方法。
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