JP7200899B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP7200899B2 JP7200899B2 JP2019178966A JP2019178966A JP7200899B2 JP 7200899 B2 JP7200899 B2 JP 7200899B2 JP 2019178966 A JP2019178966 A JP 2019178966A JP 2019178966 A JP2019178966 A JP 2019178966A JP 7200899 B2 JP7200899 B2 JP 7200899B2
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- 239000004065 semiconductor Substances 0.000 title claims description 210
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title description 6
- 238000007789 sealing Methods 0.000 claims description 150
- 239000000463 material Substances 0.000 claims description 27
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 27
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- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Description
第2の開示に係る半導体装置は、ベース板と、該ベース板の上に設けられた第1半導体チップと、該第1半導体チップと第1接合部で接合され、該第1接合部よりも上方に湾曲部を有するボンディングワイヤと、該ベース板の上面から該第1接合部よりも高く該湾曲部よりも低い高さまで設けられ、該第1接合部を覆う第1封止部材と、該第1封止部材の上に設けられ、該湾曲部を覆い、該第1封止部材よりも弾性率が低い第2封止部材と、該ベース板を囲むケースと、を備え、該ケースは該第1封止部材の上面の高さに開口面を有する窪み部を有し、該第1封止部材は該窪み部を充填する。
第3の開示に係る半導体装置は、ベース板と、該ベース板の上に設けられた第1半導体チップと、該第1半導体チップと第1接合部で接合され、該第1接合部よりも上方に湾曲部を有するボンディングワイヤと、該ベース板の上面から該第1接合部よりも高く該湾曲部よりも低い高さまで設けられ、該第1接合部を覆う第1封止部材と、該第1封止部材の上に設けられ、該湾曲部を覆い、該第1封止部材よりも弾性率が低い第2封止部材と、該ベース板の上に設けられた第1バンプと、を備え、該第1半導体チップは該第1バンプの上に設けられる。
第4の開示に係る半導体装置は、ベース板と、該ベース板の上に設けられた第1半導体チップと、該第1半導体チップと第1接合部で接合され、該第1接合部よりも上方に湾曲部を有するボンディングワイヤと、該ベース板の上面から該第1接合部よりも高く該湾曲部よりも低い高さまで設けられ、該第1接合部を覆う第1封止部材と、該第1封止部材の上に設けられ、該湾曲部を覆い、該第1封止部材よりも弾性率が低い第2封止部材と、該ベース板の上に設けられた第1回路パターンと、該ベース板の上に設けられ該第1回路パターンよりも薄い第2回路パターンと、該第2回路パターンの上に設けられ、該第1半導体チップよりも厚い第2半導体チップと、を備え、該第1半導体チップは該第1回路パターンに接合材で接合され、該第1封止部材は該接合材を覆い、該第1半導体チップの上面と該第2半導体チップの上面の高さは揃っている。
図1は、実施の形態1に係る半導体装置100の断面図である。半導体装置100は例えば電力半導体装置である。半導体装置100は絶縁基板10を備える。絶縁基板10は例えば樹脂絶縁基板である。樹脂絶縁基板を用いることで、絶縁基板10に対する封止部材からの応力を緩和できる。絶縁基板10は、ベース板12と、ベース板12の上に設けられた絶縁層14と、絶縁層14の上に設けられた回路パターン16を有する。絶縁層14は例えば樹脂から形成される。回路パターン16は回路パターン16a、16bを含む。
Claims (10)
- ベース板と、
前記ベース板の上に設けられた第1半導体チップと、
前記第1半導体チップと第1接合部で接合され、前記第1接合部よりも上方に湾曲部を有するボンディングワイヤと、
前記ベース板の上面から前記第1接合部よりも高く前記湾曲部よりも低い高さまで設けられ、前記第1接合部を覆う第1封止部材と、
前記第1封止部材の上に設けられ、前記湾曲部を覆い、前記第1封止部材よりも弾性率が低い第2封止部材と、
を備え、
前記第1接合部は前記第1半導体チップの上面に設けられ、
前記第1封止部材の上面は、前記第1半導体チップの前記上面から前記ボンディングワイヤのワイヤ径の範囲内に設けられることを特徴とする半導体装置。 - 前記ベース板の上に設けられた第1回路パターンを備え、
前記第1半導体チップは前記第1回路パターンに接合材で接合され、
前記第1封止部材は前記接合材を覆うことを特徴とする請求項1に記載の半導体装置。 - 前記ベース板の上に設けられた第2回路パターンを備え、
前記ボンディングワイヤは前記第2回路パターンと第2接合部で接合され、
前記第1封止部材は前記第2接合部を覆うことを特徴とする請求項1または2に記載の半導体装置。 - ベース板と、
前記ベース板の上に設けられた第1半導体チップと、
前記第1半導体チップと第1接合部で接合され、前記第1接合部よりも上方に湾曲部を有するボンディングワイヤと、
前記ベース板の上面から前記第1接合部よりも高く前記湾曲部よりも低い高さまで設けられ、前記第1接合部を覆う第1封止部材と、
前記第1封止部材の上に設けられ、前記湾曲部を覆い、前記第1封止部材よりも弾性率が低い第2封止部材と、
前記ベース板を囲むケースと、
を備え、
前記ケースは前記第1封止部材の上面の高さに開口面を有する窪み部を有し、
前記第1封止部材は前記窪み部を充填することを特徴とする半導体装置。 - ベース板と、
前記ベース板の上に設けられた第1半導体チップと、
前記第1半導体チップと第1接合部で接合され、前記第1接合部よりも上方に湾曲部を有するボンディングワイヤと、
前記ベース板の上面から前記第1接合部よりも高く前記湾曲部よりも低い高さまで設けられ、前記第1接合部を覆う第1封止部材と、
前記第1封止部材の上に設けられ、前記湾曲部を覆い、前記第1封止部材よりも弾性率が低い第2封止部材と、
前記ベース板の上に設けられた第1バンプと、
を備え、
前記第1半導体チップは前記第1バンプの上に設けられることを特徴とする半導体装置。 - 前記ベース板の上に設けられ前記第1バンプよりも背の低い第2バンプと、
前記第2バンプの上に設けられ、前記第1半導体チップよりも厚い第2半導体チップと、
を備え、
前記第1半導体チップの上面と前記第2半導体チップの上面の高さは揃っていることを特徴とする請求項5に記載の半導体装置。 - ベース板と、
前記ベース板の上に設けられた第1半導体チップと、
前記第1半導体チップと第1接合部で接合され、前記第1接合部よりも上方に湾曲部を有するボンディングワイヤと、
前記ベース板の上面から前記第1接合部よりも高く前記湾曲部よりも低い高さまで設けられ、前記第1接合部を覆う第1封止部材と、
前記第1封止部材の上に設けられ、前記湾曲部を覆い、前記第1封止部材よりも弾性率が低い第2封止部材と、
前記ベース板の上に設けられた第1回路パターンと、
前記ベース板の上に設けられ前記第1回路パターンよりも薄い第2回路パターンと、
前記第2回路パターンの上に設けられ、前記第1半導体チップよりも厚い第2半導体チップと、
を備え、
前記第1半導体チップは前記第1回路パターンに接合材で接合され、
前記第1封止部材は前記接合材を覆い、
前記第1半導体チップの上面と前記第2半導体チップの上面の高さは揃っていることを特徴とする半導体装置。 - 前記第1半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1から7の何れか1項に記載の半導体装置。
- 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料またはダイヤモンドであることを特徴とする請求項8に記載の半導体装置。
- ベース板の上に半導体チップを設け、
前記半導体チップとボンディングワイヤとを接合し、前記ボンディングワイヤに前記半導体チップとの接合部よりも上方に湾曲部を形成し、
前記ベース板の上面から前記接合部よりも高く前記湾曲部よりも低い高さまでを第1封止部材で封止し、前記第1封止部材で前記接合部を覆い、
前記第1封止部材の上面を前記第1封止部材よりも弾性率が低い第2封止部材で封止し、前記第2封止部材で前記湾曲部を覆い、
前記接合部は前記半導体チップの上面に設けられ、
前記第1封止部材の上面は、前記半導体チップの前記上面から前記ボンディングワイヤのワイヤ径の範囲内に設けられることを特徴とする半導体装置の製造方法。
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WO2017145667A1 (ja) | 2016-02-24 | 2017-08-31 | 三菱電機株式会社 | 半導体モジュールおよびその製造方法 |
US10304788B1 (en) | 2018-04-11 | 2019-05-28 | Semiconductor Components Industries, Llc | Semiconductor power module to protect against short circuit event |
JP2021052068A (ja) | 2019-09-24 | 2021-04-01 | 株式会社東芝 | パワーモジュール |
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