CN108257934B - 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构 - Google Patents

焊垫开口及熔丝焊接口的制作方法与焊垫开口结构 Download PDF

Info

Publication number
CN108257934B
CN108257934B CN201611247351.8A CN201611247351A CN108257934B CN 108257934 B CN108257934 B CN 108257934B CN 201611247351 A CN201611247351 A CN 201611247351A CN 108257934 B CN108257934 B CN 108257934B
Authority
CN
China
Prior art keywords
opening
trench
dielectric layer
mask
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611247351.8A
Other languages
English (en)
Other versions
CN108257934A (zh
Inventor
张峰溢
李甫哲
邱仅鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN201611247351.8A priority Critical patent/CN108257934B/zh
Priority to US15/854,785 priority patent/US10396048B2/en
Publication of CN108257934A publication Critical patent/CN108257934A/zh
Priority to US16/505,724 priority patent/US10600749B2/en
Application granted granted Critical
Publication of CN108257934B publication Critical patent/CN108257934B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05019—Shape in side view being a non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本发明公开一种焊垫开口及熔丝焊接口的制作方法与焊垫开口结构。该焊垫开口及熔丝焊接口的制作方法包含提供一介电层，其中一导电垫和一熔丝位于介电层中，形成一第一掩模，覆盖介电层，接着进行第一次移除制作工艺，以第一掩模为掩模，移除部分的介电层以形成一第一沟槽，其中导电垫位于第一沟槽的正下方并且未从第一沟槽暴露出来，然后移除第一掩模，之后形成一第二掩模覆盖介电层，接续进行第二次移除制作工艺，以第二掩模为掩模，移除第一沟槽正下方的介电层以形成一焊垫开口，并且移除熔丝正上方的介电层以形成一熔丝焊接口。

Description

焊垫开口及熔丝焊接口的制作方法与焊垫开口结构
技术领域
本发明涉及一种焊垫开口及熔丝焊接口的制作方法，特别是涉及一种可避免导电垫在制作熔丝焊接口时被损坏的制作方法。
背景技术
随着半导体制作工艺的微小化以及复杂度的提高，半导体元件也变得更容易受各式缺陷或杂质所影响，而单一金属连线、二极管或晶体管等的失效往往即构成整个芯片的缺陷。因此为了解决这个问题，现行技术便会在集成电路中形成一些可熔断的连接线，也就是熔丝，以确保集成电路的可利用性。一般而言，熔丝连接集成电路中的冗余电路，一旦检测发现电路具有缺陷时，这些连接线就可用于修复或取代有缺陷的电路。
此外半导体工业的目标之一是生产出更小的半导体装置，越小的装置通常消耗更低的电力，具有更高的效能。更小的半导体装置可通过在前端制作工艺中以更小及更高密度的主动及被动元件来达成，后端制作工艺可通过在晶片或是基底之间电性互连来达成。晶片或是基底之间电性互连包含了利用打线、导电凸块或导电球等置入焊垫开口中并且电连结导电垫的方式，因此最佳化焊垫开口和熔丝焊接口的制作方法，一直为本领域的重要课题。
发明内容
有鉴于此，本发明提供一种新颖的焊垫开口及熔丝焊接口的制作方法。
根据本发明的一较佳实施例，一种焊垫开口结构包含一介电层、一导电垫设置于介电层中，一掩模层位于介电层上，一焊垫开口设置于介电层和掩模层中、位于导电垫的正上方并且导电垫由焊垫开口暴露出来，其中焊垫开口包含一第一部分和一第二部分，第一部分的宽度大于第二部分的宽度，且第一部分在第二部分之上。
根据本发明的一较佳实施例，一种焊垫开口结构包含一介电层，一导电垫设置于介电层中，一第一沟槽设置于介电层中，一第二沟槽设置于介电层中，第二沟槽和第一沟槽相通并且第二沟槽位于第一沟槽下方，第一沟槽的宽度大于第二沟槽的宽度，一感光性聚酰亚胺材料层位于介电层上，其中感光性聚酰亚胺材料层延伸至第一沟槽，使得感光性聚酰亚胺材料层的侧壁和第二沟槽的侧壁切齐，其中该感光性聚酰亚胺和该第二沟槽组成一焊垫开口，此外，导电垫由焊垫开口暴露出来。
根据本发明的一较佳实施例，一种焊垫开口及熔丝焊接口的制作方法，包含提供一介电层，其中一导电垫和一熔丝位于介电层中，形成一第一掩模，覆盖介电层，第一掩模包含一第一开口，第一开口位于导电垫的正上方，接着进行第一次移除制作工艺，以第一掩模为掩模，移除部分的介电层以形成一第一沟槽，其中导电垫位于第一沟槽的正下方并且未从第一沟槽暴露出来，然后移除第一掩模，之后形成一第二掩模覆盖介电层，其中第二掩模包含一第二开口和一第三开口，第二开口暴露第一沟槽，第三开口位于熔丝的正上方，接续进行第二次移除制作工艺，以第二掩模为掩模，移除第一沟槽正下方的介电层以形成一焊垫开口，并且移除熔丝正上方的介电层以形成一熔丝焊接口，其中导电垫由焊垫开口暴露出来。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举较佳实施方式，并配合所附附图，作详细说明如下。然而如下的较佳实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图4为根据本发明的第一较佳实施例所绘示的焊垫开口及熔丝焊接口的制作方法示意图；
图5和图6为根据本发明的第二较佳实施例所绘示的焊垫开口及熔丝焊接口的制作方法示意图；
图7所绘示的为形成导电凸块于焊垫开口内的步骤示意图；
图8和图9为根据本发明的第三较佳实施例所绘示的焊垫开口及熔丝焊接口的制作方法示意图；
图10为形成打线于焊垫开口内的步骤示意图。
主要元件符号说明
10 介电层 12 导电垫
14 熔丝 16 金属内连线
18 第一材料层 20 第二材料层
22 第一掩模 24 第一开口
26 第一沟槽 28 第二掩模
30 第二开口 32 第三开口
34 焊垫开口 36 熔丝焊接口
38 打线 40 第二沟槽
42 导电凸块 100 焊垫开口结构
112 导电垫 134 焊垫开口
200 焊垫开口结构 234 焊垫开口
236 第一部分 238 第二部分
具体实施方式
图1至图4为根据本发明的第一较佳实施例所绘示的焊垫开口及熔丝焊接口的制作方法。
如图1所示，提供一晶片(图未示)，一介电层10设置于晶片上，一导电垫12、一导电垫112和一熔丝14设置于介电层10中，在导电垫12、导电垫112和熔丝14的下方可以设置有金属内连线16与导电垫12和熔丝14接触并且电连结，导电垫12和导电垫112可以为铝、铜或是其它金属，熔丝14材料可以为铝、铜或是其它金属，介电层10可以为单层材料层或是多层堆叠材料层，介电层10可以包含氮化硅、氧化硅、氮氧化硅等介电材料。根据本发明的较佳实施例，介电层10包含一第一材料层18和一第二材料层20，第一材料层18设置于第二材料层20之下，第一材料层18为氧化硅层，第二材料层20为氮化硅层，第一材料层18的厚度约为100微米，第二材料层20的厚度约为80微米。接着形成一第一掩模22覆盖介电层10，第一掩模22包含一第一开口24，第一开口24位于导电垫12的正上方，导电垫112则完全被第一掩模22覆盖。第一掩模22较佳为光致抗蚀剂，但不限于此，根据其它制作工艺需求，第一掩模22可以为其它材料。
如图2所示，进行第一次移除制作工艺，以第一掩模22为掩模，移除部分的介电层10以形成一第一沟槽26，此时导电垫12位于第一沟槽26的正下方并且未从第一沟槽26暴露出来，也就是说还有部分的介电层10覆盖导电垫12，在本实施中是部分的第一材料层18盖住导电垫12，根据本发明的一较佳实施例，覆盖在导电垫12正上方的第一材料层18厚度约2000埃，之后移除第一掩模22。第一次移除制作工艺较佳是利用干蚀刻，例如以含氟气体为蚀刻气体，移除介电层10中的第一材料层18和第二材料层20，含氟气体包含CHF3、CF4、C4F8或者其它有机氟化合物。
如图3所示，形成一第二掩模28覆盖介电层10，第二掩模28包含一第二开口30和一第三开口32，由第二开口30暴露出第一沟槽26并且第二开口30的侧壁对齐第一沟槽26的侧壁，且第二掩模28并未填入第一沟槽26，而第三开口32则位于熔丝14的正上方，根据本发明的较佳实施例，第二掩模28包含感光性聚酰亚胺(polyimide)，因此在第二掩模28上的第二开口30和第三开口32可以利用曝光显影方式形成。
如图4所示，进行第二次移除制作工艺，以第二掩模28为掩模，移除第一沟槽26正下方的介电层10以形成一焊垫开口34，同时也移除熔丝14正上方的介电层10以形成一熔丝焊接口36，第二次移除制作工艺后，使得导电垫12由焊垫开口34暴露出来，而熔丝14则依然被介电层10覆盖，只是在熔丝14正上方的介电层10的厚度变小，详细来说熔丝14被第一材料层18覆盖，此外根据本发明的一较佳实施例，在熔丝14正上方的第一材料层18的厚度约为1500埃。此外焊垫开口34由介电层10和第二掩模28共同定义而成，熔丝焊接口36也是由介电层10和第二掩模28共同定义而成。此时本发明的焊垫开口34和熔丝焊接口36业已完成。由焊垫开口34暴露出导电垫12，而导电垫112上的介电层10和第二掩模28则维持未被蚀刻的状态，此外熔丝14正上方的介电层10的厚度变小后，若是在后续重分布制作工艺需要重新设计电路，或是需修复电路时，激光则可以轻易的穿透盖在熔丝14正上方的介电层10，烧断熔丝，另外熔丝14正上方的介电层10在重分布制作工艺之前可以扮演保护熔丝14，避免熔丝14氧化的作用。值得注意的是，第二掩模28在第二次移除制作工艺完成后保留作为保护元件免于宇宙射线伤害的材料层，在后续制作工艺也不会被移除。另外，根据本发明的较佳实施例，第二次移除制作工艺较佳是利用干蚀刻，例如以含氟气体为蚀刻气体，移除介电层10中的第一材料层18和第二材料层20，含氟气体包含CHF3、CF4、C4F8或者其它有机氟化合物，此外蚀刻气体也可以使用有机氟化合物混合NF3，其中有机氟化合物用来提高对感光性聚酰亚胺的选择比并且可使熔丝焊接口36的底部平坦，而NF3可以带走蚀刻过程中的副产物。此外当蚀刻介电层10至导电垫12暴露出来但熔丝焊接口36还未完成时，可在蚀刻气体中可加入SF6，SF6会在导电垫12上形成保护层，之后可再继续蚀刻介电层10以形成熔丝焊接口32，如此在形成熔丝焊接口36的过程中可减少对导电垫12的损害。此外，第二次移除制作工艺可以另外包含在完成焊垫开口34和熔丝焊接口36后，可以在蚀刻气体中再另外加入N2、H2、O2、CO、CO2或He，以清除在介电层10上或晶片上残留的蚀刻副产物。
接着，视产品需求可在焊垫开口34中形成一打线或一导电凸块接触导电垫12，打线或导电凸块用于将导电垫12和另一元件例如芯片、电路板或半导体基材电连结。
图1、图2、图5和图6为根据本发明的第二较佳实施例所绘示的焊垫开口及熔丝焊接口的制作方法，其中实施例中相同元件均以相同元件符号表示。第二较佳实施例和第一较佳实施例的不同之处在于第二较佳实施例中的第二掩模28延伸至第一沟槽26内，并且第二开口30也位于第一沟槽26内。第二较佳实施例中的图1和图2的步骤和第一实施例相同，在此不再赘述，此外图5是接续图2的步骤，如图5所示，在移除第一掩模22后，形成第二掩模28覆盖介电层10，第二掩模28延伸至第一沟槽26内，并且第二开口30也位于第一沟槽26内，也就是说第二掩模28接触第一沟槽26的侧壁，第二开口30的宽度比第一沟槽26的宽度小，此外第三开口32位于熔丝14的正上方。
如图6所示，进行第二次移除制作工艺，以第二掩模28为掩模，移除介电层10以在导电垫12正上方形成一第二沟槽40并且同时在熔丝14正上方形成熔丝焊接口36，焊垫开口134由第二掩模28和介电层10中的第二沟槽40共同定义，也就是说，焊垫开口134和熔丝焊接口36皆在第二次移除制作工艺中完成，第二掩模28的侧壁和第二沟槽40的侧壁切齐，详细来说，第二沟槽40位于第一材料层18中，而第一沟槽26同时位于第二材料层20和第一材料层18中，又第二沟槽40的侧壁和第一沟槽26的侧壁及底部共同构成一阶梯轮廓。另外，第二次移除制作工艺所使用的蚀刻气体以及详细步骤和第一较佳实施例中相同，此外，覆盖在熔丝14正上方的第一材料层18的厚度也和第一较佳实施例中相同，在此不再赘述。如图7所示，形成一导电凸块42于焊垫开口134中。导电凸块42用于将导电垫12和另一元件例如芯片、电路板或半导体基材电连结。此时第二掩模28在完成导电凸块42后依然覆盖介电层10，导电凸块42可以用打线取代。
图1、图2、图8和图9为根据本发明的第三较佳实施例所绘示的焊垫开口及熔丝焊接口的制作方法，其中实施例中相同元件均以相同元件符号表示。第三较佳实施例和第一较佳实施例的不同之处在于第三较佳实施例中的第二掩模上28的第二开口30的宽度大于第一沟槽26的宽度，并且第一沟槽26由第二开口30暴露出来。第三较佳实施例中的图1和图2的步骤和第一实施例相同，在此不再赘述，此外图8是接续图2的步骤，如图8所示，在移除第一掩模22后，形成第二掩模28覆盖介电层10，第二掩模28的第二开口30的宽度大于第一沟槽26的宽度，使得部分的介电层10的上表面由第二开口30暴露出来，此外同样地，第三开口32位于熔丝14的正上方。如图9所示，进行第二次移除制作工艺，以第二掩模28为掩模，移除介电层10以形成焊垫开口234和熔丝焊接口36，焊垫开口234由第二掩模28和介电层10共同定义，第二次移除制作工艺所使用的蚀刻气体以及详细步骤和第一较佳实施例中相同，此外，覆盖在熔丝14正上方的第一材料层18的厚度也和第一较佳实施例中相同，在此不再赘述。如图10所示，形成一打线38于焊垫开口234中。打线38用于将导电垫12和另一元件例如芯片、电路板或半导体基材电连结，打线38可以用导电凸块取代。
图6为根据本发明的第二较佳实施例的制作方法所完成的焊垫开口结构，如图6所示，焊垫开口结构100包含一介电层10，一导电垫12设置于介电层10中，介电层10可以为单层材料层或是多层堆叠材料层，介电层10可以包含氮化硅、氧化硅、氮氧化硅等介电材料。根据本发明的较佳实施例，介电层10为多层堆叠材料层，包含一第一材料层18和一第二材料层20，第一材料层18和第二材料层20不同，第一材料层18较佳为氧化硅层，而第二材料层20较佳为氮化硅层，一第一沟槽26和一第二沟槽40设置于介电层10中，第二沟槽40和第一沟槽26相通并且第二沟槽40位于第一沟槽26下方，第一沟槽26的宽度大于第二沟槽40的宽度，一第二掩模28，例如一感光性聚酰亚胺材料层，位于介电层10上，第二掩模28延伸至第一沟槽26，使得第二掩模28的侧壁和第二沟槽40的的侧壁切齐，其中第二掩模28和第二沟槽40组成焊垫开口134，并且导电垫12由焊垫开口134暴露出来。第二沟槽40由第一材料层18构成，第一沟槽26由第一材料层18和第二材料层20共同构成。如图7所示，一导电凸块42可以设置于焊垫开口134内并且接触导电垫12。
图9为根据本发明的第三较佳实施例的制作方法所完成的焊垫开口结构，焊垫开口结构200包含一介电层10，介电层10可以为单层材料层或是多层堆叠材料层，介电层10可以包含氮化硅、氧化硅、氮氧化硅等介电材料。根据本发明的较佳实施例，介电层10包含一第一材料层18和一第二材料层20，一导电垫12设置于介电层10中，一第二掩模28位于介电层10上，一焊垫开口234设置于介电层10和掩模层28中并且位于导电垫12的正上方并且导电垫12由焊垫开口234暴露出来，焊垫开口234包含一第一部分236和一第二部分238，第一部分236的宽度大于第二部分238的宽度，且第一部分236在第二部分238之上，第一部分236由第二掩模28、第一材料层18和第二材料层20构成，第二部分238只由介电层10中的第一材料层18构成，又第二部分238的侧壁、第一部分236的侧壁和第一材料层18的上表面共同形成一阶梯轮廓。此外，第二掩模28较佳为感光性聚酰亚胺材料层。如图10所示，一打线38可以设置于焊垫开口234内并且接触导电垫12。
本发明在第一次移除制作工艺时，特意控制蚀刻深度，让导电垫正上方的介电层只有部分被移除，直到第二次移除制作工艺在制作熔丝焊接口的同时，才移除导电垫正上方的介电层使得导电垫暴露出来，因此本发明的制作工艺中，导电垫在第一次移除制作工艺时不会接触到蚀刻气体，相较于传统制作工艺，本发明的制作工艺降低了导电垫接触蚀刻气体的时间，减少导电垫的表面被耗损的程度。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种焊垫开口结构，包含：
介电层；
导电垫，设置于该介电层中；
掩模层，位于该介电层上；以及
焊垫开口，设置于该介电层和该掩模层中、位于该导电垫的正上方并且该导电垫由该焊垫开口暴露出来，其中该焊垫开口包含第一部分和第二部分，该第一部分的宽度大于该第二部分的宽度，且该第一部分在该第二部分之上，
其中该介电层包含氧化硅层和氮化硅层，该氮化硅层位于该氧化硅层上，
其中该焊垫开口的该第一部分位于该掩模层、该氮化硅层以及部分的氧化硅层中，
第二部分只由介电层中的氧化硅层构成，且第二部分的侧壁、第一部分的侧壁和氧化硅层的上表面共同形成一阶梯轮廓。
2.如权利要求1所述的焊垫开口结构，其中该掩模层包含感光性聚酰亚胺。
3.如权利要求1所述的焊垫开口结构，另包含导电凸块或打线，位于焊垫开口内并且电连结该导电垫。
4.一种焊垫开口结构，包含：
介电层；
导电垫，设置于该介电层中；
第一沟槽，设置于该介电层中；
第二沟槽，设置于该介电层中，该第二沟槽和该第一沟槽相通并且该第二沟槽位于该第一沟槽下方，该第一沟槽的宽度大于该第二沟槽的宽度；以及
感光性聚酰亚胺材料层，位于该介电层上，其中该感光性聚酰亚胺材料层延伸至该第一沟槽，使得该感光性聚酰亚胺材料层的侧壁和该第二沟槽的侧壁切齐，其中该感光性聚酰亚胺和该第二沟槽组成一焊垫开口，该导电垫由该焊垫开口暴露出来，
该介电层包含氧化硅层和氮化硅层，该氮化硅层位于该氧化硅层上，该第一沟槽位于该感光性聚酰亚胺材料层、该氮化硅层以及部分的氧化硅层中，
第二沟槽只由介电层中的氧化硅层构成，且第二沟槽的侧壁、第一沟槽的侧壁和氧化硅层的上表面共同形成一阶梯轮廓。
5.如权利要求4所述的焊垫开口结构，另包含导电凸块或打线，位于焊垫开口内并且电连结该导电垫。
6.一种焊垫开口及熔丝焊接口的制作方法，包含：
提供一介电层，其中一导电垫和一熔丝位于该介电层中；
形成一第一掩模，覆盖该介电层，该第一掩模包含第一开口，该第一开口位于该导电垫的正上方；
进行第一次移除制作工艺，以该第一掩模为掩模，移除部分的该介电层以形成一第一沟槽，其中该导电垫位于该第一沟槽的正下方并且未从该第一沟槽暴露出来；
移除该第一掩模；
形成一第二掩模覆盖该介电层，其中该第二掩模包含第二开口和第三开口，该第二开口暴露该第一沟槽，该第三开口位于该熔丝的正上方；
进行第二次移除制作工艺，以该第二掩模为掩模，移除该第一沟槽正下方的该介电层以形成一焊垫开口，并且同时移除该熔丝正上方的该介电层以形成一熔丝焊接口，其中该导电垫由该焊垫开口暴露出来，其中在该第二次移除制作工艺完成后，保留该第二掩模。
7.如权利要求6所述的焊垫开口及熔丝焊接口的制作方法，其中该第二开口对齐该第一沟槽。
8.如权利要求6所述的焊垫开口及熔丝焊接口的制作方法，其中该第二掩模延伸至该第一沟槽内，并且该第二开口位于该第一沟槽内。
9.如权利要求6所述的焊垫开口及熔丝焊接口的制作方法，其中该第二开口的宽度大于该第一沟槽的宽度，并且该第一沟槽由该第二开口暴露出来。
10.如权利要求6所述的焊垫开口及熔丝焊接口的制作方法，其中该第二掩模层包含感光性聚酰亚胺。
CN201611247351.8A 2016-12-29 2016-12-29 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构 Active CN108257934B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201611247351.8A CN108257934B (zh) 2016-12-29 2016-12-29 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构
US15/854,785 US10396048B2 (en) 2016-12-29 2017-12-27 Contact hole structure and fabricating method of contact hole and fuse hole
US16/505,724 US10600749B2 (en) 2016-12-29 2019-07-09 Contact hole structure and fabricating method of contact hole and fuse hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611247351.8A CN108257934B (zh) 2016-12-29 2016-12-29 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构

Publications (2)

Publication Number Publication Date
CN108257934A CN108257934A (zh) 2018-07-06
CN108257934B true CN108257934B (zh) 2021-02-19

Family

ID=62711203

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611247351.8A Active CN108257934B (zh) 2016-12-29 2016-12-29 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构

Country Status (2)

Country Link
US (2) US10396048B2 (zh)
CN (1) CN108257934B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10600732B1 (en) * 2018-09-05 2020-03-24 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN109830459B (zh) * 2019-01-28 2021-01-22 上海华虹宏力半导体制造有限公司 一种熔丝结构的形成方法
CN114446868B (zh) * 2020-11-05 2024-07-05 长鑫存储技术有限公司 集成电路装置及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5573962A (en) * 1995-12-15 1996-11-12 Vanguard International Semiconductor Corporation Low cycle time CMOS process
CN1471152A (zh) * 2002-07-24 2004-01-28 旺宏电子股份有限公司 形成接触窗的方法
CN1645565A (zh) * 2004-01-19 2005-07-27 恩益禧电子股份有限公司 半导体装置及其制造方法
CN104253083A (zh) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 熔丝器件的制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004834A (en) * 1995-11-29 1999-12-21 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having a fuse
US6235557B1 (en) * 1999-04-28 2001-05-22 Philips Semiconductors, Inc. Programmable fuse and method therefor
DE19961103C2 (de) * 1999-12-17 2002-03-14 Infineon Technologies Ag Dielektrische Füllung von elektrischen Verdrahtungsebenen und Verfahren zur Herstellung einer elektrischen Verdrahtung
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6348398B1 (en) * 2001-05-04 2002-02-19 United Microelectronics Corp. Method of forming pad openings and fuse openings
JP2003068856A (ja) * 2001-08-27 2003-03-07 Seiko Epson Corp ヒューズ素子、半導体装置及びその製造方法
JP2004349440A (ja) * 2003-05-22 2004-12-09 Renesas Technology Corp フリップチップ実装方法
US20070238304A1 (en) 2006-04-11 2007-10-11 Jui-Hung Wu Method of etching passivation layer
JP4937842B2 (ja) * 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR101534682B1 (ko) * 2009-03-13 2015-07-08 삼성전자주식회사 범프에 스틱을 구비하는 반도체 장치
US8587119B2 (en) * 2010-04-16 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive feature for semiconductor substrate and method of manufacture
US9496221B2 (en) * 2012-06-25 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming fuse pad and bond pad of integrated circuit
US8946891B1 (en) * 2012-09-04 2015-02-03 Amkor Technology, Inc. Mushroom shaped bump on repassivation
CN108630657B (zh) * 2017-03-24 2020-12-15 联华电子股份有限公司 半导体结构及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5573962A (en) * 1995-12-15 1996-11-12 Vanguard International Semiconductor Corporation Low cycle time CMOS process
CN1471152A (zh) * 2002-07-24 2004-01-28 旺宏电子股份有限公司 形成接触窗的方法
CN1645565A (zh) * 2004-01-19 2005-07-27 恩益禧电子股份有限公司 半导体装置及其制造方法
CN104253083A (zh) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 熔丝器件的制备方法

Also Published As

Publication number Publication date
US10600749B2 (en) 2020-03-24
US20190333884A1 (en) 2019-10-31
CN108257934A (zh) 2018-07-06
US20180190603A1 (en) 2018-07-05
US10396048B2 (en) 2019-08-27

Similar Documents

Publication Publication Date Title
KR100743648B1 (ko) 웨이퍼 레벨 시스템 인 패키지의 제조방법
CN108630657B (zh) 半导体结构及其制作方法
TW202015211A (zh) 封裝件及其形成方法
CN108257934B (zh) 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构
JP2011071239A (ja) 半導体装置の製造方法
US8129835B2 (en) Package substrate having semiconductor component embedded therein and fabrication method thereof
JP2009164607A (ja) ボンディングパッド構造物及びその製造方法、並びにボンディングパッド構造物を有する半導体パッケージ
KR102411678B1 (ko) 반도체 장치 및 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
US20080169558A1 (en) Redistribution circuit structure and manufacturing method thereof
US6479376B1 (en) Process improvement for the creation of aluminum contact bumps
US7682957B2 (en) Method of forming pad and fuse in semiconductor device
US20210257294A1 (en) Semiconductor device and method of fabricating the same
US9240374B2 (en) Semiconductor device and method of forming thereof
CN111681955B (zh) 半导体器件的制备方法
KR100754895B1 (ko) 반도체 장치 및 그 형성 방법
JP2008244383A (ja) 半導体装置およびその製造方法
SG184671A1 (en) Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer
CN105575880A (zh) 一种半导体器件的制作方法
JP5061653B2 (ja) 半導体装置及びその製造方法
JP2019121776A (ja) バンプ構造を有する半導体装置の製造方法
TWI575703B (zh) 逆熔絲結構及其編程方法
KR100933837B1 (ko) 반도체 소자의 제조방법
KR100854221B1 (ko) 반도체 디바이스의 제조 방법
KR101128896B1 (ko) 반도체 소자의 안티퓨즈 및 그 제조 방법
KR100861305B1 (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Hsinchu City, Taiwan, China

Applicant after: UNITED MICROELECTRONICS Corp.

Applicant after: Fujian Jinhua Integrated Circuit Co.,Ltd.

Address before: Hsinchu Science Industrial Park, Hsinchu City, Taiwan, China

Applicant before: UNITED MICROELECTRONICS Corp.

Applicant before: Fujian Jinhua Integrated Circuit Co.,Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant