TW202015211A - 封裝件及其形成方法 - Google Patents

封裝件及其形成方法 Download PDF

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TW202015211A
TW202015211A TW108131603A TW108131603A TW202015211A TW 202015211 A TW202015211 A TW 202015211A TW 108131603 A TW108131603 A TW 108131603A TW 108131603 A TW108131603 A TW 108131603A TW 202015211 A TW202015211 A TW 202015211A
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layer
package
die
conductive
forming
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TW108131603A
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TWI724525B (zh
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余振華
邵棟樑
志航 董
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括圖案化出穿過第一封裝元件之第一鈍化層的凹口。第一封裝元件包括第一半導體基板。上述方法亦包括接合第一封裝元件至第二封裝元件。第二封裝元件包括第二半導體基板與第二鈍化層。接合第一封裝元件至第二封裝元件的步驟包括直接將第一鈍化層接合至第二鈍化層。接合第一封裝元件至第二封裝元件的步驟亦包括回焊設置於凹口中的導電連接件之焊料區域以將第一封裝元件電性連接至第二封裝元件。

Description

封裝件及其形成方法
本發明實施例大抵上關於形成半導體封裝件之方法，且特別關於以接合之方式形成半導體封裝件之方法。
半導體裝置被用於各種電子裝置，例如:個人電腦、手機、數位相機以及其他電子設備。一般而言，在半導體基板上依序沉積絕緣或介電層、導電層以及半導體層，並且以微影之方式將各材料層圖案化以於其上形成電路組件及元件，藉此製造半導體裝置。
半導體工業經由持續降低最小特徵部件尺寸來持續精進各電子組件(例如:電晶體、二極體、電阻器、電容器等)的集積密度(integration density)，這使得更多組件可被整合至一給定面積。然而，隨著最小特徵部件尺寸之縮小，產生了其他需要被解決的問題。
本發明實施例包括一種封裝件之形成方法。上述方法包括圖案化出通過第一封裝元件之第一鈍化層的凹口。第一 封裝元件包括第一半導體基板。上述方法亦包括將第一封裝元件接合至第二封裝元件。第二封裝元件包括第二半導體基板與第二鈍化層。將第一封裝元件接合至第二封裝元件的步驟包括將第一鈍化層直接接合至第二鈍化層、以及回焊設置於凹口中的導電連接件的焊料區域以將第一封裝元件電性連接至第二封裝元件。
本發明實施例亦包括一種封裝件之形成方法。上述方法包括於第一封裝元件之第一鈍化層上形成第一晶種層、於第一晶種層上鍍覆一或多個第一導電層、於一或多個第一導電層上形成焊料區域、以及將第一封裝元件接合至第二封裝元件。第二封裝元件包括第二鈍化層。將第一封裝元件接合至第二封裝元件的步驟包括將焊料區域放置在延伸穿過第二鈍化層的開口中。開口暴露出第二封裝元件的接觸墊。將第一封裝元件接合至第二封裝元件的步驟亦包括將第一鈍化層直接接合至第二鈍化層、以及回焊焊料區域以將焊料區域延伸至第二封裝元件的接觸墊。
本發明實施例亦包括一種封裝件。上述封裝件包括第一晶粒。第一晶粒包括第一鈍化層、以及第一接觸墊。上述封裝件亦包括接合至第一晶粒的第二晶粒。第二晶粒包括第二鈍化層與第二接觸墊，第二鈍化層與第一鈍化層形成界面，第二接觸墊位於第二鈍化層的表面。上述封裝件亦包括晶粒連接件，晶粒連接件從第二接觸墊經由第一鈍化層延伸至第一接觸墊。晶粒連接件包括凸塊下金屬(UBM)。凸塊下金屬包括第二導電層上的第一導電層，第一導電層具有與第二導電層不同的寬度。晶粒連接件亦包括與第一接觸墊接觸的焊料區域。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本發明實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方，即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。此外，本發明實施例在各例子中可能重複標號及/或字母。此重複是為了達到簡明之目的，而並非用來指出所述之各實施例及/或配置之間的關係。
此外，其中可能用到與空間相對用詞，例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，這些空間相對用詞係為了便於描述圖示中一個(些)元件或特徵部件與另一個(些)元件或特徵部件之間的關係，這些空間相對用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
於此所述之實施例有關於用於封裝裝置之接合結構。在各實施例中，結合使用介電質至介電質接合(dielectric-to-dielectric bonding)與導體至導體接合(conductor-to-conductor bonding)以將兩個或更多的晶片(有時稱作晶粒)接合在一起。上述介電質接合與導體接合之結合可稱為混合式接合(hybrid bonding)。經由使用混合式接合方法，由於晶片連接件(connector)之尺寸(例如:高度)縮小以及不需要在接合之後於晶片之間施與底層充填材料(underfill)，可縮小所接合之封裝件的輪廓。於晶片之間省略底層充填材料更降低了所接合之封裝件中的電阻與寄生電容，這增進了電氣效能。
介電質至介電質接合包括將第一晶片之第一介電層直接接合至第二晶片之第二介電層，導體至導體接合包括將第一晶片之第一導電特徵部件接合至第二晶片之第二導電特徵部件。第一導電特徵部件或第二導電特徵部件之至少一者包括焊料區域，焊料區域係被用來形成導體至導體接合。因為焊料(solder)具有相對較低的回焊溫度(reflow temperature)，可於相對較低之溫度形成導體至導體接合，這降低了損害任何晶片元件之風險。因此，各實施例提供在相對較低之溫度下接合晶片之機制，同時仍提供低輪廓(low profile)以增進可靠度與電氣效能。
根據一些實施例，第1A至1H圖係為一製程中之中間步驟的各剖面圖，上述製程係經由將第一封裝元件接合至第二封裝元件以形成半導體封裝件300。於第1A至1E圖中，形成包括晶粒連接件128(請參照第1E圖)的第一封裝元件(例如:半導體晶粒100)。晶粒連接件128可被稱為凸形(convex)晶粒連接件，這是因為晶粒連接件128延伸遠離第一半導體晶粒100之最外鈍化層112。第1F至1H圖繪示出後續之接合製程，其將第一半導體晶粒100接合至第二封裝元件(例如:第二半導體晶粒200)，以形成接合之半導體封裝件300。第一半導體晶粒100之晶粒連接件128被接合至第二半導體晶粒200之晶粒連接件(例如:接合墊208)。第二半導體晶粒200之晶粒連接件可被稱為凹形(concave)晶粒連接件，這是因為第二半導體晶粒200之晶粒連接件係設置於第二半導體晶粒200之最外鈍化層212中的開口中。經由使用根據各實施例之接合配置，可提供低輪廓封裝件，其具有較高的可靠度以及較佳的電氣效能。
雖然晶粒100與晶粒200在此被稱為”晶粒” ，應理解的是，所形成之晶粒100與晶粒200可以是一較大晶圓之一部分(例如:與其他晶粒連接)。接下來，可將晶粒100與晶粒200從上述晶圓之其他特徵部件單離(singulated)出來。可於接合以形成封裝件300之前或者接合以形成封裝件300之後進行晶粒100或晶粒200各自之單離製程。舉例而言，於此所述之各實施例可被應用於晶粒至晶粒接合(die-to-die bonding)製程、晶粒至晶圓接合(die-to-wafer bonding)製程、或者晶圓至晶圓接合(wafer-to-wafer bonding)製程。
於第1A圖中，繪示出第一半導體晶粒100。晶粒100可為裸晶片半導體晶粒(例如:未封裝半導體晶粒)。舉例而言，晶粒100可為邏輯晶粒(logic die，例如:中央處理單元、微控制器等)、記憶體晶粒(memory die，例如:動態隨機存取記憶體晶粒(dynamic random access memory (DRAM) die)、混合記憶體立方(hybrid memory cube (HBC))、靜態隨機存取記憶體晶粒(static random access memory (SRAM) die)、寬輸入/輸出記憶體晶粒(wide input/output (wideIO) memory die)、磁阻式隨機存取記憶體晶粒(magnetoresistive random access memory (mRAM) die)、電阻式隨機存取記憶體晶粒(resistive random access memory (rRAM) die)等)、功率管理晶粒(power management die，例如:功率管理積體電路(PMIC)晶粒)、射頻晶粒(radio frequency (RF) die)、感應器晶粒(sensor die)、微機電系統晶粒(micro-electro-mechanical-system (MEMS) die)、訊號處理晶粒(例如:數位訊號處理(DSP)晶粒)、前端晶粒(front-end die，例如:類比前端晶粒(analog front-end (AFE) die))、生醫晶粒(biomedical die)、或類似之晶粒。
可根據適當之製程處理晶粒100，以於晶粒100中形成積體電路。舉例而言，晶粒100可包括半導體基板102，例如:摻雜或未摻雜的矽、或者絕緣層上半導體基板(semiconductor-on-insulator (SOI) substrate)的主動層。半導體基板可包括其他半導體材料(例如:鍺)、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、合金半導體(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)、或上述之組合。可使用其他基板，例如:多層(multi-layered)基板或組成漸變基板(gradient substrate)。裝置 104(例如:電晶體、二極體、電容器、電阻器等)可形成於半導體基板102之中及/或之上，且可經由互連結構106互連(如點110所指)，舉例而言，互連結構106包括半導體基板102上之一或多個介電層中的金屬化圖案。互連結構106與裝置104形成一或多個積體電路。在第1A圖中，僅繪示出晶粒100中之最頂金屬化圖案108。然而，應理解的是，互連結構106可包括設置於任何數量之介電層中之任何數量之金屬化圖案。
晶粒100更包括墊片(例如:墊片114)，互連結構106與裝置104係與上述墊片形成外部連接。墊片114可包括銅、鋁、或其他導電材料。墊片114可設置於可稱為積體電路晶粒100之主動側或前側的部分上。積體電路晶粒100之主動側以及前側可指涉半導體基板102之一側，且在該側上形成主動裝置(例如:裝置104)。積體電路晶粒100之背側可指涉半導體基板之相對於主動側/前側的一側。
鈍化薄膜112係設置於互連結構106上，且墊片114於鈍化薄膜112之頂表面露出。鈍化薄膜112可包括任何適當之介電材料，以在後續之製程步驟中可直接接合至另一介電層。舉例而言，鈍化薄膜112可包括氧化矽(例如:SiO2 )、氮氧化矽(silicon oxynitride)、氮化矽、或類似之材料。
在替代性的實施例中，晶粒100係為中介層晶圓(interposer wafer)，中介層晶圓中不具有主動裝置。根據一些實施例，晶粒100可包括或不包括被動裝置(未繪示於圖中)，例如:電阻器、電容器、電感器、變壓器(transformers)、以及類似之裝置。
在另一替代性的實施例中，晶粒100係為封裝基板條(package substrate strip)。在一些實施例中，晶粒100包括層疊封裝基板(laminate package substrates)，其中墊片114(示意性說明)埋置於層疊介電層(鈍化層112)中。在替代性的實施例中，晶粒100係為增層式封裝基板(build-up package substrate)，增層式封裝基板包括芯層(cores，未繪示於圖中)以及建構於芯層之兩相對側上的導線(以114表示)。
如第1A圖所更繪示出之內容，晶種層116係沉積於鈍化薄膜112與墊片114(有時候稱為凸塊金屬(bump metal (BPM))114)之上。在一些實施例中，晶種層116係為金屬層，其可為單一膜層或者複合層，複合層包括由不同材料所形成的複數個副層。在一些實施例中， 晶種層116包括鈦層以及上述鈦層上的銅層。舉例而言，可使用物理氣相沉積或類似之製程來形成晶種層116。
在第1B圖中，於晶種層116上形成並圖案化光阻118。可經由旋轉塗布或類似之製程形成光阻118，且可將之暴露於光中以進行圖案化。雖然僅繪示出單一光阻層，光阻118可包括一或多層之光敏材料(photosensitive material)以及底部抗反射塗層(backside anti-reflective coating (BARC) layer)、硬罩幕層或類似之膜層。光阻118之圖案對應於後續所形成之晶粒連接件128(請參照第1D圖)。上述圖案化製程形成了開口120，開口120穿過光阻118以露出晶種層116。
在第1C圖中，於光阻118之開口120中以及晶種層116之露出的部分上形成導電材料。導電材料可包括可選膜層(optional layer)122、膜層122上的膜層124、以及膜層124上的焊料層126。在一實施例中，膜層122包括鎳，且膜層124包括銅。其他材料亦可用於膜層122及/或124。舉例而言，膜層124可包括鎳、金、或任何適當之導電化合物，而可在回焊(reflow)之後與焊料反應以形成介金屬化合物(intermetallic compound (IMC))。可經由鍍覆(plating，例如:電鍍或者無電鍍)、或類似之製程形成各導電材料(例如:膜層122、膜層124、以及焊料層126)。
接著，於第1D圖中，移除光阻118以及其上未形成有導電材料(例如:可選膜層122、膜層124、以及焊料層126)之晶種層116之部分。可經由適當之灰化或剝離製程移除光阻118，例如:使用氧電漿或類似之移除方式。在移除了光阻118之後，移除露出之晶種層116之部分，例如:經由使用適當之蝕刻製程(例如:濕式或乾式蝕刻)。晶種層116之殘留部分與導電材料(例如:可選膜層122、膜層124、以及膜層126)形成晶粒連接件128。
晶粒連接件128包括凸塊下金屬(underbump metallurgy (UBM))128A與凸塊下金屬128A上的焊料層126。凸塊下金屬128A包括晶種層116之殘留部分、可選膜層122、以及膜層124。焊料層126可具有任何可在相對較低的溫度(例如:小於300 ℃，例如(約160℃至約260℃))下被回焊之適當的材料組成。舉例而言，焊料層126可為合金，合金可包括銅、錫、銀、銦、上述之組合、或類似之材料。焊料之回焊溫度相較於被用來接合其他導電材料(例如:銅)的退火溫度(例如:300℃或更高)相對較低。經觀察，此相對較低的回焊溫度使得晶粒100在後續的製程步驟中可在相對較低的溫度下被接合，這有利地降低了晶粒100之內部特徵部件(例如:裝置104)被損害之風險。
第1E圖繪示出在後續之製程步驟中晶粒連接件128之凸塊下金屬128A之可選的(optional)蝕刻。可蝕刻凸塊下金屬128A，以於凸塊下金屬128A與焊料層126之間的界面縮小凸塊下金屬128A之表面面積。在回焊時，焊料層126可因表面張力而於凸塊下金屬128A之頂表面上成珠(bead up)。經由減少此表面面積，於回焊時，焊料層126所橫跨之垂直距離可被有利地增大。舉例而言，當在界面的表面面積較小時，焊料層126可於回焊時形成高度較大的珠狀物。舉例而言，經觀察，當縮小表面面積時，焊料層126之垂直高度增加約50%至約60%，相較之下，當未縮小表面面積時，焊料層126之垂直高度增加約40%。焊料層126之經增加的垂直高度導致較多體積之焊料層126遠離凸塊下金屬128A流動，這增進了在接合結構中焊料層126所提供的電連接。
舉例而言，可使用濕式蝕刻的方式蝕刻凸塊下金屬128A，上述濕式蝕刻係蝕刻直接位於焊料層126下方的膜層124。在一實施例中，上述濕式蝕刻係為選擇性濕式蝕刻，其蝕刻膜層124的速率大於蝕刻可選膜層122的速率。舉例而言，針對第1E圖所繪示的凸塊下金屬配置，可使用氯化氫(HCl)蝕刻膜層124。
更因為用來形成晶種層116的製程不同於用來形成膜層124的製程，因此即使晶種層116與膜層124包括相同材料，在使用相同蝕刻製程時晶種層116的蝕刻速率可低於膜層124的蝕刻速率。舉例而言，HCl濕式蝕刻可選擇性地以較低的蝕刻速率蝕刻包括銅(晶種層116)的濺鍍層(sputtered layer)，上述蝕刻速率低於蝕刻包括銅(例如:膜層124)的鍍覆層(plated layer)的蝕刻速率。在蝕刻之後，膜層124之寬度W1可為約2μm至約20μm，且可小於晶種層116之寬度W2。晶種層116之寬度W2可為約3μm至約30μm。藉此，晶種層116與膜層124可包括相同的材料，但仍可在不過度蝕刻晶種層116的前提下蝕刻膜層124。若過度蝕刻晶種層116，可能會不慎降低晶粒連接件128與下方特徵部件之間的黏著力，造成製造上的缺陷。
在第1F圖中，晶粒100與晶粒200對齊。晶粒200亦可選自裝置晶粒(device die)、中介晶粒(interposer die)、封裝基板(package substrate)以及類似之晶粒。在一些實施例中，晶粒200可以作為晶圓的組成部分(例如:在從晶圓中之其他晶粒單離出來之前)來與晶粒100對齊。在其他的實施例中，晶粒200可在單離(singulation)之後與晶粒100對齊。晶粒200包括基板202、裝置204、連接(如點210所指)至裝置204的互連結構206(包括接觸墊214)、以及鈍化層212。晶粒200可具有類似於前述晶粒100之結構，於此將不再重複細節。晶粒200中之特徵部件之材料可參照晶粒100中類似的特徵部件，晶粒100中之特徵部件開始於數字“1”，其所對應之晶粒200中的特徵部件則具有開始於“2”的標號。於晶粒200中，接觸墊214經由開口216露出，開口216延伸穿過鈍化層212。晶粒100以各晶粒連接件128與開口216對齊的方式與晶粒200對齊，開口216暴露出接觸墊214的一部分。
在第1G圖中，晶粒100之鈍化層112物理接觸並接合至晶粒200之鈍化層212。在接合之前，鈍化層112或鈍化層212之至少一者接受表面處理。表面處理可為電漿處理。可於真空環境進行電漿處理。用來製造電漿的製程氣體可為含氫氣體(hydrogen-containing gas)，含氫氣體包括第一氣體、第二氣體或第三氣體，第一氣體包括H2 與Ar，第二氣體包括H2 與N2 ，第三氣體包括H2 與He。經由表面處理，增加了於鈍化層112及/或鈍化層212之表面的羥基(OH groups)數量，這有利於形成強的熔融接合(fusion bonds)。亦可使用純的或實質上純的H2 、Ar或N2 作為製程氣體進行電漿處理，其經由還原(reduction)及/或轟炸(bombardment)來處理鈍化層112及/或鈍化層212的表面。在表面處理之後，可對鈍化層112及/或鈍化層212施加清洗製程(例如:使用去離子水沖洗(rinse))。
在清洗之後，將晶粒100與晶粒200彼此壓靠。可施加預接合(pre-bonding)壓緊力(pressing force)以將晶粒100與晶粒200彼此壓靠。在一些例示性的實施例中，每個晶粒的壓緊力可小於約5 Newtons，但亦可使用更大或更小的力量。可於室溫(約21℃至約25℃)下進行預接合，但可使用更高的溫度。舉例而言，接合時間可小於約1分鐘。
在預接合之後，鈍化層112與鈍化層212被接合在一起。然而，須於後續的退火步驟中強化上述接合。舉例而言，可視情況在約170℃之溫度下對晶粒100與晶粒200進行退火約1小時。上述可選的(optional)退火製程與後文參照第1H圖所述的回焊製程可以是分開的。舉例而言，可退火晶粒100與晶粒200，接著可對焊料層126進行後續之回焊。作為替代方案，可省略上述可選的退火製程，並在回焊焊料層126時同時強化鈍化層112與鈍化層212之間的接合。當溫度上升時，鈍化層112與鈍化層212中的OH鍵斷裂以形成強的Si-O-Si鍵，因此晶粒100與晶粒200係經由熔融接合被接合在一起。退火溫度可小於焊料之回焊溫度。舉例而言，在接合鈍化層112與鈍化層212之後，晶粒連接件128可能仍未被接合至接觸墊214。因此，晶粒連接件128之高度可小於鈍化層212之高度(例如:厚度)，且間隙可設置於晶粒連接件128與接觸墊214之間。
於第1H圖中，對晶粒連接件128進行回焊以回焊焊料層126。回焊焊料層126的步驟係將晶粒連接件128物理性接合與電性接合至晶粒200之接觸墊 214。因此，於晶粒100與晶粒200之間所形成之接合係為混合接合(hybrid bonds)，且經由將晶粒100與晶粒200接合而提供封裝件300。由於上述之回焊，在焊料層126 與晶粒連接件128之界面區域附近形成了介金屬化合物。
在一些實施例中，在不使用助焊劑(flux)的情況下將晶粒連接件128接合至接觸墊214。舉例而言，在接合之前，不於接觸墊214上形成助焊劑，這有利地允許兩個或更多晶片之小節距接合。各實施例允許使用無助焊劑接合製程(flux-less bonding process)，這允許了兩個或更多晶片之小節距接合。由於助焊劑在回焊時可能會影響由焊料層126所形成之珠狀物的表面張力與高度，無助焊劑接合可允許更一致且可預測的製程。雖然所繪示的實施例係描述無助焊劑接合製程，在其他的實施例中，助焊劑之使用可作為接合製程之一部分。
因為焊料之回焊溫度小於為了達到其他材料(例如:金屬)之相互擴散(inter-diffusion)所要求之退火溫度，可進行較低溫度之退火以達到回焊。舉例而言，可在小於300℃(例如:約250℃至約260℃)的溫度下進行焊料層之回焊1分鐘至2分鐘。較低之退火溫度可使得所形成之製造缺陷較少，特別是在晶粒100及/或晶粒200對於溫度敏感(例如:特別是記憶體晶粒，生醫晶粒等)的情況下。由於回焊，晶粒連接件128之高度H1增加，舉例而言，其匹配鈍化層212之高度 H1(例如:厚度)。在一些實施例中，高度 H1為5µm或更小。
在封裝件300中，晶粒連接件128可稱為凸形晶粒連接件，這是因為其自晶粒100之最外鈍化層(例如:112)向外延伸。再者，接觸墊214可稱為凹形晶粒連接件，這是因為其係經由晶粒200之最外鈍化層(例如:212)中之開口216露出。在封裝件300中，晶粒連接件128設置於開口216中。在接合之後，晶粒連接件128周圍之開口216之部分仍未被填充而可為氣隙。因此，所接合之封裝件300的厚度可縮小，這是因為晶粒連接件128之整體或部分係嵌入於晶粒200之鈍化層212中。
再者，鈍化層212可在晶粒100與晶粒200之間被用來作為焊料罩幕與物理支撐。藉此，於晶粒100與晶粒200之間(舉例而言，在晶粒連接件128周圍)不須配置底層充填材料。經由省略底層充填材料，晶粒100與晶粒200之間的寄生電容與電阻可被降低。
根據一些實施例，第2A至2C圖繪示出形成接合封裝件400之中間製程步驟之剖面圖。在第2A至2C圖中，第一封裝元件(例如:晶粒100)被接合至第二封裝元件(例如:晶粒200)。晶粒100與晶粒200可類似於前文參照第1A至1H圖所述的特徵部件，其中類似的標號指涉使用類似製程所形成之類似的特徵部件。為了簡明起見，未對此些特徵部件進行進一步的說明。
如前文所述，晶粒200包括接觸墊214、最外鈍化層212、以及延伸穿過鈍化層212且暴露出接觸墊214的開口216。在第2A至2B圖中，接合墊308係形成於開口216的側壁與底表面上。
在第2A圖中，晶種層302係沉積於開口216的側壁與底表面上。在一些實施例中，晶種層302係為金屬層，其可為單一膜層或者為複合層，複合層包括複數個由不同材料所形成的副層。在一些實施例中，晶種層302包括鈦層與鈦層上的銅層。舉例而言，可使用物理氣相沉積或類似之方式形成晶種層302。
導電材料係形成於晶種層302上。導電材料可包括可選的膜層304以及膜層306。在一實施例中，膜層304包括鎳，且膜層306包括銅。其他材料亦可能用於膜層304及/或膜層306。可經由鍍覆(例如:電鍍或無電鍍或類似之製程)形成各導電材料(例如:膜層304與膜層306)。
接下來，在第2B圖中，可對晶種層302、膜層304以及膜層306進行平坦化製程(例如:化學機械研磨(CMP)、研磨拋光、回蝕刻、或類似之製程)以移除鈍化層212之頂表面之上之晶種層302、膜層304以及膜層306之部分。因此，接合墊308係沿著開口216之側壁與底表面形成，開口216延伸穿過鈍化層212。接合墊308更可物理連接並且電性連接至經由開口216露出之接觸墊 214。
在第2C圖中，晶粒200係混合接合至晶粒100以形成封裝件400。混合式接合可包括使用類似前文參照第1G圖所述的製程在鈍化層112與鈍化層212之間形成介電質至介電質接合。混合式接合可更包括回焊製程，回焊製程將晶粒100之晶粒連接件128接合至晶粒200之接合墊308。回焊製程可類似於前文參照第1H圖所述的製程。舉例而言，可將晶粒連接件128的焊料層126回焊以物理接合與電性接合至晶粒200之接合墊308。
根據一些實施例，第3A至3E圖繪示出經由將第一封裝元件(例如:晶粒100)接合至第二封裝元件(例如:晶粒200)以形成接合封裝件500之中間製程步驟之剖面圖。晶粒100與晶粒200可類似於前文參照第1A至1H圖所述的特徵部件，其中類似的標號指涉使用類似製程所形成之類似的特徵部件。為了簡明起見，省略此些特徵部件之進一步說明。
如前文所述，晶粒200包括接觸墊214、最外鈍化層212、以及開口216，開口216延伸穿過鈍化層212且暴露出接觸墊214。在第3A至3B圖中，接合墊408係形成於開口 216的側壁與底表面上。
在第3A圖中，晶種層302、可選的導電層304、以及導電層306係依序形成於開口216的側壁與底表面上。晶種層302、膜層304以及膜層306可類似於第2B圖中所揭露的特徵部件，其中類似的標號指涉使用類似製程所形成之類似的元件。
如第3A圖進一步所繪示之內容，光阻402係形成於膜層306之上且延伸進入開口 216中。可使用旋轉塗布或類似之方式形成光阻402，並可將其暴露於光中以圖案化。雖然僅繪示出單一光阻層，光阻402可包括一或多層之光敏材料與背側抗反射塗層、硬罩幕層或類似之膜層。光阻402之圖案對應於後續將形成之導電針狀物(參照第3B圖)。上述圖案化形成了穿過光阻402的開口404以暴露出膜層306。
在第3B圖中，導電材料係形成於光阻402之開口404中及露出之膜層306之部分上。導電材料可包括導電針狀物406。導電針狀物406可稱為針狀物是因為各針狀物相對較細。舉例而言，各導電針狀物406之寬度W3可為約0.5μm至約5μm。在一些實施例中，導電針狀物406包括銅。其他材料亦可用於導電針狀物406。舉例而言，導電針狀物406可包括鎳、金或其他任何可與焊料反應以在回焊後形成介金屬化合物的導電材料。可經由鍍覆(電鍍、或無電鍍、或類似之方式)形成導電針狀物406。鍍覆製程可使用露出之膜層306作為晶種層而不需要另一晶種層。雖然繪示出三個導電針狀物406，但可於膜層306上形成任何數量之導電針狀物406。
在第3C圖中，移除光阻402。可經由適當之灰化或剝離製程(例如:使用氧電漿或類似之方式)移除光阻402。在移除光阻402之後，接著可對晶種層302、膜層304以及膜層306進行平坦化製程(例如:化學機械研磨(CMP)、研磨拋光、回蝕刻或類似之製程)以移除鈍化層212之頂表面之上之晶種層302、膜層304以及膜層306之部分。因此，接合墊408係沿著開口216之側壁與底表面形成，開口216延伸穿過鈍化層212。接合墊408可物理連接並電性連接至被開口216露出之接觸墊214，且接合墊408可更包括向上延伸的(例如:在遠離基板202的方向上)導電針狀物406。
在第3D圖中，晶粒100與晶粒200對齊並相互接觸。在使晶粒100接觸晶粒200時，接合墊408之導電針狀物406之上部可嵌入於晶粒200之晶粒連接件128中。舉例而言，導電針狀物406之上部可延伸進入焊料層126中而導電針狀物406之下部仍可維持在焊料層126之外。可經由使用相對於焊料層126較硬的材料形成導電針狀物406之材料而使導電針狀物406嵌入。舉例而言，在一實施例中，導電針狀物406是銅，而焊料層是銦層。銦的彈性係數(elastic modulus)與硬度分別是11 GPa與0.009 GPa，而銅的彈性係數與硬度則分別是110 GPa與2.15 GPa。由於導電針狀物406之硬度相對較高，導電針狀物406可至少部分地嵌入於焊料層126中。
在第3E圖中，晶粒200混合接合至晶粒100以形成封裝件500。混合式接合可包括使用類似於前文參照第1G圖所述之製程於鈍化層112與鈍化層212之間形成介電質至介電質接合。在接合鈍化層112與鈍化層212之後，封裝件500可具有類似如第3D圖所繪示的配置。舉例而言，焊料層126可與膜層306保持物理分離，導電針狀物406之上部延伸進入晶粒連接件128之焊料層126中。混合式接合可更包括回焊製程，回焊製程使晶粒100之晶粒連接件128接合至晶粒200之接合墊408。回焊製程可類似於前述參照第1H圖所述的製程。舉例而言，晶粒連接件128之焊料層126可被回焊以物理接合並電性接合至晶粒200之接合墊408。此外，接合墊408之導電針狀物406可嵌入於晶粒連接件128之經回焊之焊料層126中。經由回焊，介金屬化合物可形成於焊料層126與接合墊408/導電針狀物406之界面的周圍區域。經由將導電針狀物406嵌入於晶粒連接件128中，晶粒100與晶粒200之間可具有較佳的電連接。於接合時將導電針狀物406部分地嵌入於晶粒連接件128中更可增大晶粒連接件128之高度及/或開口216之寬度的製程容許範圍(process window)，這使得封裝件500之製造變得容易。
根據一些實施例，第4A至4F圖繪示出經由將第一封裝元件(例如:晶粒10o)接合至第二封裝元件(例如:晶粒200)以形成接合封裝件600之中間製程步驟的剖面圖。晶粒100與晶粒200可類似於前文參照第1A至1H圖所述的特徵部件，其中類似的標號指涉使用類似製程所形成之類似的特徵部件。為了簡明起見，未對此些特徵部件進行進一步的說明。
如前文所述，晶粒200包括接觸墊214、最外鈍化層212、以及開口216，開口216延伸穿過鈍化層212且露出接觸墊214。在第4A至4D圖中，類似於晶粒連接件128的晶粒連接件514係形成於接觸墊214上的開口216中。在第4A至4E圖的實施例中，晶粒200之開口216中的晶粒連接件514可取代晶粒100之晶粒連接件128。
在第4A圖中，晶種層502係形成於開口216之側壁與底表面上。晶種層502可由類似於前文參照第2A圖所述之晶種層302之材料及／或製程所形成。
如第4A圖更進一步繪示出的內容，光阻504係形成於膜層502之上且延伸進入開口216中。可經由旋轉塗布或類似之方式形成光阻504，且可將光阻504暴露於光中以將其圖案化。雖然僅繪示出單一光阻層，光阻504可包括一或多層之光敏材料以及底部抗反射塗層、硬罩幕層或類似之膜層。上述圖案化製程形成了開口506，開口506穿過光阻504以露出晶種層502。
在第4B圖中，導電材料形成於光阻504之開口506中及露出之晶種層502之部分之上。導電材料可包括可選的膜層508、膜層508上的膜層510、以及膜層510上的焊料層512。可經由類似於前述參照第1C圖所述之膜層122之材料並使用類似之製程形成可選的膜層508，可經由類似於前述參照第1C圖所述之膜層124之材料並使用類似之製程形成膜層510，可經由類似於前述參照第1C圖所述之焊料層126之材料並使用類似之製程形成焊料層512。
接著，在第4C圖中，移除光阻504與上方未形成有導電材料(例如:可選的膜層508、膜層510以及焊料層512)之晶種層502之部分。可經由適當之灰化或剝離製程(例如:氧電漿或類似之方式)移除光阻504。在光阻504被移除後，露出之晶種層502之部分被移除，例如:使用適當之蝕刻製程(例如:濕式或乾式蝕刻)。剩餘之晶種層502之部分以及導電材料(例如:可選的膜層508、膜層510以及焊料層512)形成晶粒連接件514。晶粒連接件514係設置於開口216中且至少部分地延伸穿過晶粒200之鈍化層212。
晶粒連接件514包括凸塊下金屬514A以及凸塊下金屬514A上的焊料層512。凸塊下金屬514A包括晶種層502之剩餘部分、可選的膜層508以及膜層510。經觀察，此相對較低的回焊溫度使得晶粒200在後續的製程步驟中可在相對較低的溫度下被接合，這有利地降低了晶200之內部特徵部件(例如:裝置104)被損害之風險。
第4D圖繪示出在後續之製程步驟中晶粒連接件514之凸塊下金屬514A之可選的蝕刻。可蝕刻凸塊下金屬514A以於凸塊下金屬514A與焊料層512之間之界面縮小凸塊下金屬514A之表面面積。如前文針對凸塊下金屬128A之可選的蝕刻所述之內容，經由減少此表面面積，於回焊時，焊料層512所橫跨之垂直距離可被有利地增大。舉例而言，當在界面的表面面積較小時，焊料層512可於回焊時形成高度較大的珠狀物。
舉例而言，可使用蝕刻直接位於焊料層512下方之膜層510的濕式蝕刻來蝕刻凸塊下金屬514A。在一實施例中，上述濕式蝕刻係為選擇性濕式蝕刻，其蝕刻膜層510的速率大於可選的膜層508。舉例而言，針對第1E圖中所繪示之凸塊下金屬配置，可使用氯化氫(HCl)蝕刻膜層510。
更因為用來形成晶種層502的製程不同於用來形成膜層510的製程，因此即使晶種層502與膜層510包括相同材料，在使用相同蝕刻製程時，晶種層502的蝕刻速率可低於膜層510的蝕刻速率。舉例而言，HCl濕式蝕刻可選擇性地以較低的蝕刻速率蝕刻包括銅(晶種層502)的濺鍍層(sputtered layer)，上述蝕刻速率低於蝕刻包括銅(例如: 膜層510)的鍍覆層(plated layer)的蝕刻速率。在蝕刻之後，膜層510之寬度W4可為約1μm至約19μm，且可小於晶種層502之寬度W5。晶種層502之寬度W5可為約1.5μm至約20μm。藉此，晶種層502與膜層510可包括相同的材料，但仍可在不過度蝕刻晶種層502的前提下蝕刻膜層510。若過度蝕刻晶種層502，可能會不慎降低晶粒連接件514與下方特徵部件之間的黏著力，造成製造上的缺陷。
在第4E圖中，晶粒100與晶粒200相互對齊且相互接觸。在使晶粒100與晶粒200接觸時，晶粒連接件514與晶粒100之接觸墊114物理性分離。舉例而言，晶粒連接件514之焊料層512與晶粒100之接觸墊114之間設置有間隙。
在第4F圖中，晶粒200混合接合至晶粒100以形成封裝件600。混合式接合可包括使用類似於前文參照第1G圖所述之製程於鈍化層112與鈍化層212之間形成介電質至介電質接合。在接合鈍化層112與鈍化層212之後，封裝件600可具有類似如第4E圖所繪示的配置。舉例而言，焊料層512可與接觸墊114保持物理分離。
混合式接合可更包括回焊製程，回焊製程使晶粒200之晶粒連接件214接合至晶粒100之接合墊114。回焊製程可類似於前述參照第1H圖所述的製程。舉例而言，晶粒連接件514之焊料層512可被回焊以物理接合並電性接合至晶粒100之接合墊114。
根據一些實施例，第5圖繪示出封裝件750之剖面圖。封裝件750包括使用與前述類似之接合配置接合至多個其他封裝元件(例如:堆疊晶粒700B、700C、700D、以及700E(例如:記憶體晶粒))的第一封裝元件(例如:晶粒700A(例如:邏輯晶粒))。晶粒700A、700B、700C、700D與700E中之特徵部件的材料與形成方法可參照晶粒100中之類似的特徵部件，其中晶粒100中之類似之特徵部件係以數字“1”作為開始，晶粒700A、700B、700C、700D與700E中之特徵部件的標號則以數字“7”作為開始，其對應於晶粒200中之特徵部件。舉例而言，晶粒700A、700B、700C、700D與700E各自包括相應之半導體基板702A、702B、702C、702D與702E，此些半導體基板上形成有主動裝置。互連結構706A、706B、706C、706D、706E與706F包括一或多個介電層中的一或多層之互連結構，其使各晶粒700A、700B、700C、700D與700E中之主動裝置電性互連以形成功能電路。晶粒700A、700B、700C、700D與700E各自更包括相應之複數個貫穿導孔(through vias)732A、732B、732C、732D與732E。複數個貫穿導孔732A、732B、732C、732D與732E各自提供穿過晶粒700A、700B、700C、700D與700E之各自相應之半導體基板702A、702B、702C、702D與702E的電連接。在一些實施例中，晶粒700A、700B、700C、700D與700E各自之高度可為約30μm或更小。
晶粒700A、700B、700C、700D與700E之接合可使用如前述之混合式接合配置。舉例而言，鈍化層712A、712B、712C、712D、712E、712F、712G與712H被用來在晶粒700A、700B、700C、700D與700E之相應之界面形成介電質至介電質接合。凹口716A、716B、716C與716D延伸穿過相應之鈍化層712B、712D、712E與712H。晶粒連接件728A、728B、728C與728D係設置於相應之凹口716A、716B、716C、716D中，且晶粒連接件728A、728B、728C與728D經由在晶粒700A、700B、700C、700D與700E之相應之界面上之導體至導體接合提供電連接。晶粒連接件728A、728B、728C與728D各自包括焊料區域，焊料區域被回焊以形成導體至導體接合。晶粒700A更包括晶粒連接件730(例如:微凸塊(microbumps (μbumps)))，其可被用來將封裝件750接合至另一封裝元件(例如:基板、封裝基板、中介層、印刷電路板、其他封裝件、母板(motherboard)、或類似之元件)。晶粒連接件730可設置在晶粒700A的前側上。因為使用混合配置，不須在晶粒700A、700B、700C、700D與700E之間設置底層充填材料。經由省略底層充填材料，可降低寄生電容與電阻，藉此增進電氣效能。此外，各種混合式接合配置允許低輪廓且高密度之接合。舉例而言，在一些實施例中，晶粒700A、700B、700C、700D與700E之間的間隙高度(standoff height)H2可為約5μm或更小。間隙高度H2可等於晶粒連接件728A、728B、728C與 728D之高度且更可等於鈍化層712B、712D、712E與712H之高度。晶粒700A、700B、700C、700D與700E之相鄰兩者之間之各間隙高度H2可相同或不同於晶粒700A、700B、700C、700D與700E之其他相鄰兩者之間之其他間隙高度H2。
在一實施例中，晶粒連接件728A、728B、728C與728D各自之焊料區域係同時被回焊。舉例而言，可將晶粒700A、700B、700C、700D與700E對齊，且可在不回焊任何晶粒連接件728A、728B、728C與728D之焊料區域的情況下於相鄰之鈍化層712A、712B、712C、712D、712E、712F、712G與712H之間形成介電質至介電質接合。舉例而言，晶粒連接件728A、728B、728C與728D的狀態可類似於前文參照第1G圖所述之狀態。在堆疊晶粒700A、700B、700C、700D與700E之後，可進行單一回焊以同時回焊各晶粒連接件728A、728B、728C與728D。經由僅進行單一回焊， 減少了熱製程之次數，且晶粒700A、700B、700C、700D與700E不受制於多次的回焊製程，藉此減少製造缺陷之風險。
雖然第5圖繪示出具有與第1H圖類似配置之凹口中之晶粒連接件，但可使用任何前文所述之接合配置。舉例而言，接觸墊可形成於凹口716A、716B、716C與716D的側壁與底表面上。接觸墊可具有導電針狀物(例如:如第3E圖所示)或不具有導電針狀物(例如:如第2C圖所示)。此外，雖然在第5圖中有5個晶粒接合在一起，在其他的實施例中，更多或更少的晶粒可被接合在一起。
根據不同的實施例802、804、806與808，第6圖繪示出接合前晶粒700A、700B、700C、700D與700E之前側與背側上可能的凹口(例如:凹口716A、716B、716C與716D)與晶粒連接件(例如:晶粒連接件728A、728B、728C與728D)配置的表格。其他配置亦是有可能的。舉例而言，在一些實施例中，晶粒連接件728A、728B、728C與728D可形成於相應之凹口716A、716B、716C與716D中(例如:如第4A至4E圖所描述之內容)。
於此所述之實施例有關於用於封裝裝置的接合結構。在各實施例中，使用混合接合(結合介電質至介電質接合與導體至導體接合)將兩個以上的晶片(有時稱為晶粒)接合在一起。經由使用混合式接合方法，由於晶片連接件之尺寸(例如:高度)縮小且不需要在接合之後於晶片之間施與底層充填材料，可縮小所接合之封裝件的輪廓。於晶片之間省略底層充填材料更允許所接合之封裝件中之較低之電阻與較低之寄生電容，藉此增進電氣效能。此外，用於混合式接合製程實施例之導體包括具有回焊溫度相對較低的焊料區域。因此，可於相對較低的溫度形成導體至導體接合，藉此降低了損害任何晶片之元件之風險。各實施例提供用於在相對較低之溫度下將晶片接合之機制，但仍提供低輪廓以增進可靠度與電氣效能。
根據一實施例，一種方法包括圖案化出穿過第一封裝元件之第一鈍化層的凹口。第一封裝元件包括第一半導體基板。上述方法亦包括將第一封裝元件接合至第二封裝元件。第二封裝元件包括第二半導體基板與第二鈍化層。將第一封裝元件接合至第二封裝元件的步驟包括將第一鈍化層直接接合至第二鈍化層、以及回焊設置於凹口中的導電連接件之焊料區域以將第一封裝元件電性連接至第二封裝元件。在一實施例中，導電連接件之形成係包括於第二鈍化層中的第一導電特徵部件之上形成晶種層、於晶種層之上形成第一金屬層、於第一金屬層之上形成第二金屬層、蝕刻第二金屬層、以及在蝕刻第二金屬層之後於第二金屬層之上形成焊料區域。在一實施例中，蝕刻第二金屬層之步驟於與第一金屬層相對的第二金屬層的表面縮小了第二金屬層之表面面積。在一實施例中，晶種層之形成係包括使用濺鍍製程形成第一銅層，第二金屬層之形成係包括使用鍍覆製程形成第二銅層，蝕刻第二金屬層的步驟係包括以大於第一銅層的蝕刻速率蝕刻第二銅層。在一實施例中，上述方法更包括在將第一封裝元件接合至第二封裝元件之前於凹口的側壁與底表面上鍍覆第二導電特徵部件。在一實施例中，將第一封裝元件接合至第二封裝元件的步驟包括將第二導電特徵部件之複數個導電針狀物嵌入於焊料區域中。在一實施例中，上述方法更包括在將第一封裝元件接合至第二封裝元件之前於凹口中形成導電連接件。在一實施例中，將第一封裝元件接合至第二封裝元件的步驟係為無助焊劑接合製程。
根據一實施例，一種方法包括於第一封裝元件之第一鈍化層上形成第一晶種層、於第一晶種層上鍍覆一或多個第一導電層、於一或多個第一導電層上形成焊料區域、以及將第一封裝元件接合至第二封裝元件。第二封裝元件包括第二鈍化層。將第一封裝元件接合至第二封裝元件的步驟包括將焊料區域放置在延伸穿過第二鈍化層的開口中。開口暴露出第二封裝元件的接觸墊。將第一封裝元件接合至第二封裝元件的步驟亦包括將第一鈍化層直接接合至第二鈍化層、以及回焊焊料區域以將焊料區域延伸至第二封裝元件的接觸墊。在一實施例中，一或多個第一導電層包括銅層，且上述方法更包括在將第一封裝元件接合至第二封裝元件之前蝕刻銅層以縮小銅層之表面面積。在一實施例中，上述方法更包括蝕刻第一晶種層以縮小第一晶種層之寬度並同時蝕刻銅層。在一實施例中，經由蝕刻銅層與第一晶種層，第一晶種層之寬度被縮小而小於銅層之寬度。在一實施例中，在將第一鈍化層直接接合至第二鈍化層之後以及在回焊焊料區域之前，於焊料區域與接觸墊之間設置有間隙。在一實施例中，上述方法更包括沿著開口之側壁與底表面形成接觸墊。在一實施例中，上述方法更包括形成從接觸墊向上延伸的複數個導電區域，且將焊料區域放置於開口中的步驟包括將複數個導電區域之至少一部分嵌入於焊料區域中。
根據一實施例，封裝件包括第一晶粒。第一晶粒包括第一鈍化層、以及第一接觸墊。上述封裝件亦包括接合至第一晶粒的第二晶粒。第二晶粒包括第二鈍化層與第二接觸墊，第二鈍化層與第一鈍化層形成界面，第二接觸墊位於第二鈍化層的表面。上述封裝件亦包括晶粒連接件，晶粒連接件從第二接觸墊經由第一鈍化層延伸至第一接觸墊。晶粒連接件包括凸塊下金屬(UBM)。凸塊下金屬包括第二導電層上的第一導電層，第一導電層具有與第二導電層不同的寬度。晶粒連接件亦包括與第一接觸墊接觸的焊料區域。在一實施例中，凸塊下金屬更包括第一導電層與第二導電層之間的第三導電層，第三導電層比第一導電層與第二導電層寬。在一實施例中，第一接觸墊係沿著第一鈍化層之側壁設置。在一實施例中，第一接觸墊包括延伸進入焊料區域的複數個導電區域。在一實施例中，第一導電層係設置於第二導電層與焊料區域之間，且第二導電層比第一導電層寬。
前述內文概述了許多實施例之特徵部件，使本技術領域中具有通常知識者可以更加了解相應之詳細說明。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到與在此介紹的實施例相同之目的及/或達到與在此介紹的實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100:半導體晶粒； 102:半導體基板； 104:裝置； 106:互連結構； 108:金屬化圖案； 110:互連； 112:鈍化層； 114:墊片； 116:晶種層； 118:光阻； 120:開口； 122:可選膜層； 124:膜層； 126:焊料層； 128:晶粒連接件； 128A:凸塊下金屬； W1、W2:寬度； 200:晶粒； 202:半導體基板； 204:裝置； 206:互連結構； 210:互連； 212:鈍化層； 214:接觸墊； 216:開口； H1:高度； 300:半導體封裝件； 302:晶種層； 304:膜層； 306:膜層； 308:接合墊； 400:半導體封裝件； 402:光阻； 404:開口； 406:導電針狀物； W3:寬度； 500:半導體封裝件； 502:晶種層； 504:光阻； 506:開口； 508:可選膜層； 510:膜層； 512:焊料層； 514:晶粒連接件； 514A:凸塊下金屬； W4、W5:寬度； 700A、700B、700C、700D、700E:晶粒； 702A、702B、702C、702D、702E:半導體基板； 706A、706B、706C、706D、706E、706F:互連結構； 712A、712B、712C、712D、712E、712F、712G、712H:鈍化層； 716A、716B、716C、716D:凹口； 728A、728B、728C、728D:晶粒連接件； 732A、732B、732C、732D、732E:貫穿導孔 730:晶粒連接件； 750:封裝件； H2:間隙高度。
以下將配合所附圖式詳述本發明之各層面。應注意的是，各種特徵部件並未按照比例繪製且僅用以說明例示。事實上，元件的尺寸可能經放大或縮小，以清楚地說明本發明實施例。 第1A至1H圖根據一些實施例繪示出製造半導體封裝件(semiconductor package)之各中間步驟的剖面圖。 第2A至2C圖根據一些實施例繪示出製造半導體封裝件之各中間步驟的剖面圖。 第3A至3E圖根據一些實施例繪示出製造半導體封裝件之各中間步驟的剖面圖。 第4A至4F圖根據一些實施例繪示出製造半導體封裝件之各中間步驟的剖面圖。 第5圖根據一些實施例繪示出半導體封裝件的剖面圖。 第6圖根據一些實施例繪示出可能的半導體封裝件之配置之表格。
100:半導體晶粒
102:半導體基板
106:互連結構
112:鈍化層
124:膜層
126:焊料層
128:晶粒連接件
200:晶粒
202:半導體基板
206:互連結構
212:鈍化層
214:接觸墊
216:開口
H1:高度
300:半導體封裝件

Claims (20)

  1. 一種封裝件之形成方法，包括: 圖案化出通過一第一封裝元件之一第一鈍化層的一凹口，該第一    封裝元件包括一第一半導體基板；以及 將該第一封裝元件接合至一第二封裝元件，其中該第二封裝元件包括一第二半導體基板與一第二鈍化層，其中將該第一封裝元件接合至該第二封裝元件的步驟包括: 將該第一鈍化層直接接合至該第二鈍化層；以及 回焊設置於該凹口中的一導電連接件的一焊料區域以將該第一封裝元件電性連接至該第二封裝元件。
  2. 如申請專利範圍第1項所述之封裝件之形成方法，其中該導電連接件之形成步驟包括: 於該第二鈍化層中的一第一導電特徵部件之上形成一晶種層； 於該晶種層之上形成一第一金屬層； 於該第一金屬層之上形成一第二金屬層； 蝕刻該第二金屬層；以及 在蝕刻該第二金屬層之後，於該第二金屬層之上形成該焊料區域。
  3. 如申請專利範圍第2項所述之封裝件之形成方法，其中蝕刻該第二金屬層的步驟於該第二金屬層之相對於該第一金屬層的一表面縮小該第二金屬層的一表面面積。
  4. 如申請專利範圍第3項所述之封裝件之形成方法，其中該晶種層之形成步驟包括使用一濺鍍製程形成一第一銅層，其中該第二金屬層之形成步驟包括使用一鍍覆製程形成一第二銅層，且其中蝕刻該第二金屬層的步驟包括以大於該第一銅層的速率蝕刻該第二銅層。
  5. 如申請專利範圍第1項所述之封裝件之形成方法，更包括: 在將該第一封裝元件接合至該第二封裝元件之前於該凹口的側壁與一底表面上鍍覆出一第二導電特徵部件。
  6. 如申請專利範圍第5項所述之封裝件之形成方法，其中將該第一封裝元件接合至該第二封裝元件的步驟包括將該第二導電特徵部件的複數個導電針狀物嵌入該焊料區域中。
  7. 如申請專利範圍第1項所述之封裝件之形成方法，更包括: 在將該第一封裝元件接合至該第二封裝元件之前於該凹口中形成該導電連接件。
  8. 如申請專利範圍第1項所述之封裝件之形成方法，其中將該第一封裝元件接合至該第二封裝元件的步驟是一無助焊劑接合製程。
  9. 一種封裝件之形成方法，包括: 於一第一封裝元件的一第一鈍化層上形成一第一晶種層； 於該第一晶種層上鍍覆出一或多個第一導電層； 於該一或多個第一導電層上形成一焊料區域；以及 將該第一封裝元件接合至一第二封裝元件，其中該第二封裝元件包括一第二鈍化層，且其中將該第一封裝元件接合至該第二封裝元件的步驟包括: 將該焊料區域放置於延伸通過該第二鈍化層的一開口中，其中該開口露出該第二封裝元件的一接觸墊； 將該第一鈍化層直接接合至該第二鈍化層；以及 回焊該焊料區域以將該焊料區域延伸至該第二封裝元件的該接觸墊。
  10. 如申請專利範圍第9項所述之封裝件之形成方法，其中該一或多個第一導電層包括一銅層，且其中該方法更包括在將該第一封裝元件接合至該第二封裝元件之前蝕刻該銅層以縮小該銅層的一表面面積。
  11. 如申請專利範圍第10項所述之封裝件之形成方法，更包括: 在蝕刻該銅層時蝕刻該第一晶種層以縮小該第一晶種層的一寬度。
  12. 如申請專利範圍第11項所述之封裝件之形成方法，蝕刻該銅層與該第一晶種層的步驟造成該第一晶種層的該寬度之減少小於該銅層的一寬度之減少。
  13. 如申請專利範圍第10項所述之封裝件之形成方法，其中在將該第一鈍化層直接接合至該第二鈍化層之後以及回焊該焊料區域之前，於該焊料區域與該接觸墊之間設置有一間隙。
  14. 如申請專利範圍第10項所述之封裝件之形成方法，更包括: 沿著該開口的側壁與一底表面形成該接觸墊。
  15. 如申請專利範圍第14項所述之封裝件之形成方法，更包括: 形成從該接觸墊向上延伸的複數個導電區域，且其中將該焊料區域放置於該開口中的步驟包括將該複數個導電區域之至少一部分嵌入該焊料區域中。
  16. 一種封裝件包括: 一第一晶粒包括: 一第一鈍化層；以及 一第一接觸墊； 一第二晶粒，接合至該第一晶粒，該第二晶粒包括: 一第二鈍化層， 該第二鈍化層與該第一鈍化層形成一界面；以及 一第二接觸墊，位於該第二鈍化層的一表面； 一晶粒連接件，從該第二接觸墊通過該第一鈍化層延伸至該第一接觸墊，該晶粒連接件包括: 一凸塊下金屬(UBM)，該凸塊下金屬包括位於一第二導電層上的一第一導電層，該第一導電層具有與該第二導電層不同的一寬度；以及 一焊料區域，接觸該第一接觸墊。
  17. 如申請專利範圍第16項所述的封裝件，其中該凸塊下金屬更包括位於該第一導電層與該第二導電層之間的一第三導電層，該第三導電層比該第一導電層與該第二導電層寬。
  18. 如申請專利範圍第16項所述的封裝件，其中該第一接觸墊係沿著該第一鈍化層的側壁設置。
  19. 如申請專利範圍第16項所述的封裝件，其中該第一接觸墊包括複數個延伸至該焊料區域中的導電區域。
  20. 如申請專利範圍第16項所述的封裝件，其中該第一導電層係設置於該第二導電層與該焊料區域之間，且其中該第二導電層比該第一導電層寬。
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