CN110942983A - 接合的半导体器件及其形成方法 - Google Patents

接合的半导体器件及其形成方法 Download PDF

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CN110942983A
CN110942983A CN201811511262.9A CN201811511262A CN110942983A CN 110942983 A CN110942983 A CN 110942983A CN 201811511262 A CN201811511262 A CN 201811511262A CN 110942983 A CN110942983 A CN 110942983A
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layer
die
bonding
package
conductive
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CN110942983B (zh
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余振华
邵栋梁
董志航
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括穿过第一封装组件的第一钝化层图案化腔，第一封装组件包括第一半导体衬底，以及将第一封装组件接合到第二封装组件。第二封装组件包括第二半导体衬底和第二钝化层。将第一封装组件接合到第二封装组件包括：将第一钝化层直接接合到第二钝化层；以及回流设置在腔中的导电连接件的焊料区，以将第一封装组件电连接到第二封装组件。本发明的实施例还涉及接合的半导体器件及其形成方法。

Description

接合的半导体器件及其形成方法
技术领域
本发明的实施例涉及接合的半导体器件及其形成方法。
背景技术
半导体器件用于各种电子应用，例如个人计算机、手机、数码相机和其他电子设备。通常通过在半导体衬底上顺序沉积绝缘或介电层、导电层和半导体材料层，并使用光刻图案化各个材料层以在其上形成电路组件和元件来制造半导体器件。
半导体工业通过不断减小最小部件尺寸继续改善各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多组件集成到给定区域中。然而，随着最小部件尺寸的减小，出现了应该解决的其他问题。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：穿过第一封装组件的第一钝化层图案化腔，所述第一封装组件包括第一半导体衬底；以及将所述第一封装组件接合到第二封装组件，所述第二封装组件包括第二半导体衬底和第二钝化层，其中，将所述第一封装组件接合到所述第二封装组件包括：将所述第一钝化层直接接合到所述第二钝化层；和回流设置在所述腔中的导电连接件的焊料区，以将所述第一封装组件电连接到所述第二封装组件。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：在第一封装组件的第一钝化层上形成第一晶种层；在所述第一晶种层上镀一个或多个第一导电层；在所述一个或多个第一导电层上形成焊料区；以及将所述第一封装组件接合到第二封装组件，其中，所述第二封装组件包括第二钝化层，并且其中，将所述第一封装组件接合到所述第二封装组件包括：将所述焊料区放置在延伸穿过所述第二钝化层的开口中，所述开口暴露所述第二封装组件的接触焊盘；将所述第一钝化层直接接合到所述第二钝化层；和回流所述焊料区以将所述焊料区延伸到所述第二封装组件的所述接触焊盘。
本发明的又一实施例提供了一种封装件，包括：第一管芯，包括：第一钝化层；和第一接触焊盘；第二管芯，接合到所述第一管芯，所述第二管芯包括：第二钝化层，与所述第一钝化层形成界面；和第二接触焊盘，位于所述第二钝化层的表面处；管芯连接件，从所述第二接触焊盘穿过所述第一钝化层延伸到所述第一接触焊盘，所述管芯连接件包括：凸块下金属(UBM)，包括位于第二导电层上的第一导电层，所述第一导电层具有与所述第二导电层不同的宽度；和焊料区，与所述第一接触焊盘接触。
附图说明
当接合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1H示出了根据一些实施例的制造半导体封装件的各个中间步骤的截面图。
图2A至图2C示出了根据一些实施例的制造半导体封装件的各个中间步骤的截面图。
图3A至图3E示出了根据一些实施例的制造半导体封装件的各个中间步骤的截面图。
图4A至图4F示出了根据一些实施例的制造半导体封装件的各个中间步骤的截面图。
图5示出了根据一些实施例的半导体封装件的截面图。
图6示出了根据一些实施例的可能的半导体封装件配置的表格。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
这里讨论的实施例涉及用于封装的器件的接合结构。在各种实施例中，使用电介质-电介质接合和导体-导体接合的组合将两个或多个芯片(有时称为管芯)接合在一起。电介质和导体接合的这种组合可以称为混合接合。通过采用混合接合方法，可以减小接合的封装件的轮廓，因为芯片连接件的尺寸(例如，高度)减小并且在接合之后不需要在芯片之间分配底部填料。在芯片之间省略底部填料还允许在接合的封装件中降低电阻和降低寄生电容，这改善了电性能。
电介质-电介质接合包括将第一芯片的第一介电层直接接合到第二芯片的第二介电层，并且导体-导体接合包括将第一芯片的第一导电部件接合到第二芯片的第二导电部件。第一导电部件或第二导电部件中的至少一个包括焊料区，焊料区用于形成导体-导体接合。因为焊料具有相对较低的回流温度，所以可以在相对较低的温度下形成导体-导体接合，这降低了损坏芯片的任何组件的风险。因此，各种实施例提供了用于在相对较低的温度下接合芯片的机制，同时仍然提供低轮廓以改善可靠性和电性能。
图1A至图1H是根据一些实施例的通过将第一封装组件接合到第二封装组件来形成半导体封装件300的工艺期间的中间步骤的各种截面图。在图1A至图1E中，形成包括管芯连接件128(见图1E)的第一封装组件(例如，半导体管芯100)。管芯连接件128可以称为凸管芯连接件，因为它远离第一半导体管芯100的最外钝化层112延伸。图1F至图1H示出了随后的接合工艺，其中第一半导体管芯100接合到第二封装组件(例如，第二半导体管芯200)以形成接合的半导体封装件300。第一半导体管芯100的管芯连接件128接合到第二半导体管芯200的管芯连接件(例如，接合焊盘208)。第二半导体管芯200的管芯连接件可以称为凹管芯连接件，因为它设置在第二半导体管芯200的最外钝化层212中的开口内。通过使用根据各种实施例的接合配置，可以提供具有增大的可靠性和改善的电性能的较低轮廓的封装件。
虽然这里将管芯100和200称为“管芯”，但应该理解，管芯100和200可以形成为较大晶圆的一部分(例如，连接到其他管芯)。随后，可以从晶圆的其他部件分割管芯100和200。每个管芯100或200的分割工艺可以在接合之前实施以形成封装件300，或者在接合之后实施以形成封装件300。例如，本文描述的各种实施例可以应用于管芯-管芯接合、管芯-晶圆接合或晶圆-晶圆接合工艺。
在图1A中，示出了第一半导体管芯100。管芯100可以是裸芯片半导体管芯(例如，未封装的半导体管芯)。例如，管芯100可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、混合存储器数据集(HBC)、静态随机存取存储器(SRAM)管芯、宽输入/输出(宽IO)存储器管芯、磁阻随机存取存储器(mRAM)管芯、电阻随机存取存储器(rRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)、生物医学管芯等。
可以根据适用的制造工艺处理管芯100，以在管芯100中形成集成电路。例如，管芯100可以包括半导体衬底102，例如掺杂或未掺杂的硅或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用其他衬底，例如多层或梯度衬底。诸如晶体管、二极管、电容器、电阻器等的器件104可以形成在半导体衬底102中和/或上，并且可以通过互连结构106互连(如点110所示)，互连结构106包括例如半导体衬底102上的一个或多个介电层中的金属化图案。互连结构106和器件104形成一个或多个集成电路。在图1A中，仅示出了管芯100中的最顶部金属化图案108。然而，应该理解，互连结构106可以包括设置在任何数量的介电层中的任何数量的金属化图案。
管芯100还包括焊盘，例如焊盘114，通过焊盘制成到互连结构106和器件104的外部连接。焊盘114可以包括铜、铝或其他导电材料。焊盘114设置在可以称为集成电路管芯100的有源侧或前侧的位置上。集成电路管芯100的有源侧和前侧可以指的是半导体衬底102的形成有源器件(例如，器件104)的一侧。集成电路管芯100的背侧可以指半导体衬底的与有源侧/前侧相对的一侧。
钝化膜112设置在互连结构106上，并且焊盘114暴露在钝化膜112的顶面处。钝化膜112可以包括在随后的工艺步骤中可以直接接合到另一介电层的任何合适的介电材料。例如，钝化膜112可以包括氧化硅(例如，SiO2)、氮氧化硅、氮化硅等。
在替代实施例中，管芯100是中介层晶圆，其中没有有源器件。根据一些实施例，管芯100可以包括或可以不包括无源器件(未示出)，诸如电阻器、电容器、电感器、变压器等。
在又一些替代实施例中，管芯100是封装衬底条。在一些实施例中，管芯100包括层压封装衬底，其中焊盘114(示意性地示出)嵌入层压介电层(钝化层112)中。在替代实施例中，管芯100是积层封装衬底，其包括芯(未示出)和构建在芯的相对侧上的导电迹线(由114表示)。
如图1A中进一步所示，在钝化膜112和焊盘114(有时称为凸块金属(BPM)114)上方沉积晶种层116。在一些实施例中，晶种层116是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层116包括钛层和钛层上的铜层。晶种层116可以使用例如PVD等形成。
在图1B中，在晶种层116上形成并图案化光刻胶118。光刻胶118可以通过旋涂等形成，并且可以暴露于光以进行图案化。尽管示出了单个光刻胶层，但是光刻胶118可以包括与背侧抗反射涂层(BARC)、硬掩模层等组合的一层或多层光敏材料。光刻胶118的图案对应于随后形成的管芯连接件128(参见图1D)。图案化形成穿过光刻胶118的开口120以暴露晶种层116。
在图1C中，导电材料形成在光刻胶118的开口120中和晶种层116的暴露部分上。导电材料可以包括可选层122、位于层122上的层124以及位于层124上的焊料层126。在一个实施例中，层122包括镍，并且层124包括铜。层122和/或124也可以是其他材料。例如，层124可以包括镍、金或任何其他导电化合物，其可以在回流之后与焊料反应以形成金属间化合物(IMC)。每种导电材料(例如，层122、层124和焊料层126)可以通过镀形成，例如电镀或化学镀等。
然后，在图1D中，去除光刻胶118和晶种层116的其上未形成导电材料(例如，可选层122、层124和焊料层126)的部分。可以通过可接受的灰化或剥离工艺去除光刻胶118，例如使用氧等离子体等。一旦去除光刻胶118，就去除晶种层116的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿或干蚀刻。晶种层116的剩余部分和导电材料(例如，可选层122、层124和层126)形成管芯连接件128。
管芯连接件128包括凸块下金属(UBM)128A和位于UBM 128A上的焊料层126。UBM128A包括晶种层116的剩余部分、可选层122和层124。焊料层126可具有能够在相对较低的温度下(例如，小于300℃，诸如约160℃至约260℃)回流的任何合适的材料组分。例如，焊料层126可以是包括铜、锡、银、铟、它们的组合等的合金。与用于接合其他导电材料(例如，铜)的退火温度(例如，300℃或更高)相比，焊料的回流温度相对较低。已经观察到，这种相对较低的回流温度允许管芯100在相对较低的温度下在后续工艺步骤中接合，这有利地降低了损坏管芯100的内部部件(例如，器件104)的风险。
图1E示出了在后续工艺步骤中对管芯连接件128的UBM 128A的可选蚀刻。可以蚀刻UBM 128A以减小UBM 128A在UBM 128A和焊料层126之间的界面处的表面积。在回流期间，焊料层126可能由于表面张力而在UBM 128A的顶面上形成珠状。通过减小该表面积，可以有利地增加在回流期间由焊料层126穿过的垂直距离。例如，当界面处的表面积较小时，焊料层126可以在回流期间形成具有更大高度的珠子。例如，已经观察到，当表面积减小时，与焊料层126的垂直高度相比，焊料层126的垂直高度增加约50％至约60％，在不减小表面积的情况下增加约40％。焊料层126的垂直高度增加导致更大量的焊料层126从UBM 128A流出，这改善了由接合结构中的焊接层126提供的电连接。
可以使用例如湿蚀刻来蚀刻UBM 128A，湿蚀刻蚀刻位于焊料层126正下方的层124。在一个实施例中，湿蚀刻是选择性湿蚀刻，其蚀刻层124比蚀刻可选层122更快。例如，对于图1E中所示的UBM配置，可以使用氯化氢(HCl)来蚀刻层124。
此外，因为晶种层116使用与层124不同的工艺形成，所以即使当晶种层116和层124包含相同的材料时，也可以使用相同的蚀刻工艺以低于层124的速率蚀刻晶种层116。例如，HCl湿蚀刻可以以比包括铜的镀层(例如，层124)更低的速率选择性地蚀刻包括铜的溅射层(晶种层116)。在蚀刻之后，层124的宽度W1可以在约2μm至约20μm的范围内并且可以小于晶种层116的宽度W2。晶种层116的宽度W2可以在约3μm到约30μm的范围内。以这种方式，晶种层116和层124可以包括相同的材料，但是可以蚀刻层124而不过度蚀刻晶种层116。如果晶种层116被过度蚀刻，则管芯连接件128和下面的部件之间的粘合可能会无意地降低，从而导致制造缺陷。
在图1F中，管芯100与管芯200对准。管芯200也可以选自器件管芯、中介层管芯、封装衬底等。在一些实施例中，管芯200可以与管芯100对准作为晶圆的组件(例如，在从晶圆中的其他管芯分割之前)。在其他实施例中，在分割之后，管芯200可以与管芯100对准。管芯200包括衬底202、器件204、连接(如点210所示)到器件204的互连结构206(包括接触焊盘214)和钝化层212。管芯200可以具有与所描述的管芯100类似的结构，这里不再重复细节。管芯200中的部件的材料可以通过参考管芯100中的相同部件找到，其中管芯100中的相同部件以数字“1”开始，这些部件对应于管芯200中并且具有以数字“2”开始的参考标号的部件。在管芯200中，接触焊盘214通过开口216暴露，开口216延伸穿过钝化层212。管芯100以每个管芯连接件128和开口216对准的方式与管芯200对准，开口216暴露焊盘214的部分。
在图1G中，管芯100的钝化层112物理接触并接合到管芯200的钝化层212。在接合之前，钝化层112或212中的至少一个可以经受表面处理。表面处理可以是等离子体处理。等离子体处理可以在真空环境中进行。用于产生等离子体的工艺气体可以是含氢气体，其包括含有氢气(H2)和氩气(Ar)的第一气体、含有H2和氮气(N2)的第二气体或含有H2和氦气(He)的第三气体。通过表面处理，钝化层112和/或212的表面的OH基团的数量增加，这有利于形成强熔合键。等离子体处理也可以使用纯的或基本上纯的H2、Ar或N2作为工艺气体来实施，工艺气体通过还原和/或轰击来处理钝化层112和/或钝化层212的表面。在表面处理之后，可以对钝化层112和/或钝化层212施加清洁工艺(例如，用去离子水冲洗)。
在清洁之后，将管芯100和200彼此压靠。可以施加预接合压力以将管芯100和200彼此压靠。在一些示例性实施例中，压力可低于每个管芯约5牛顿，但也可使用更大或更小的力。预接合可以在室温(约21℃至约25℃之间)下进行，但可以使用更高的温度。例如，接合时间可以短于约1分钟。
在预接合之后，钝化层112和212彼此接合。然而，接合需要在随后的退火步骤中进行加强。例如，可以对管芯100和200在约170℃的温度下进行可选的退火约1小时。可选的退火工艺可以与下面参考图1H讨论的回流工艺分开。例如，可以对管芯100和200进行退火，然后可以使焊料层126回流。或者，可以省略可选的退火，并且可以在回流焊料层126的同时强化钝化层112和212之间的接合。当温度升高时，钝化层112和212中的OH键断裂以形成强Si-O-Si键，因此管芯100和200通过熔合接合彼此接合。退火温度可低于焊料的回流温度。例如，在接合钝化层112和212之后，管芯连接件128可以保持未接合到接触焊盘214。结果，管芯连接件128的高度可以小于钝化层212的高度(例如，厚度)，并且间隙可以设置在管芯连接件128和接触焊盘214之间。
在图1H中，对管芯连接件128实施回流以使焊料层126回流。使焊料层126回流将管芯连接件128物理地并且电连接到管芯200的接触焊盘214。因此，管芯100和200之间产生的接合是混合接合，并且通过接合管芯100和200来提供封装件300。作为回流的结果，可以在焊料层126与管芯连接件128对接的区域周围形成IMC。
在一些实施例中，管芯连接件128在没有焊剂的情况下接合到接触焊盘214。例如，在接合之前在接触焊盘214上没有形成焊剂，这有利地允许两个或更多个芯片的细间距接合。各种实施例允许使用无焊剂接合工艺，这允许两个或更多个芯片的细间距接合。由于焊剂可以在回流期间影响由焊料层126形成的珠子的表面张力和高度，因此无焊剂接合可以允许更均匀和可预测的制造工艺。尽管所示实施例描述了无焊剂接合工艺，但在其他实施例中，焊剂可用作接合工艺的一部分。
因为焊料的回流温度低于实现其他材料(例如，金属)的相互扩散所需的退火温度，所以可以实施较低温度的退火以实现回流。例如，回流焊料层可以在低于300℃的温度下(例如约250℃至约260℃)进行1分钟至2分钟。较低的退火温度允许较少的制造缺陷，特别是当管芯100和/或200对温度敏感时(例如，特别是在存储器管芯、生物医学管芯等中)。作为回流的结果，可以增加管芯连接件128的高度H1，例如，以匹配钝化层212的高度H1(例如，厚度)。在一些实施例中，高度H1可以是5μm或更小。
在封装件300中，管芯连接件128可以称为凸管芯连接件，因为它远离管芯100的最外钝化层(例如，112)延伸。此外，接触焊盘214可以称为凹管芯连接件，因为它通过管芯200的最外钝化层(例如，212)中的开口216暴露。在封装件300中，管芯连接件128设置在开口216中。在接合之后，管芯连接件128周围的开口216的部分可以保持未填充并且是气隙。因此，可以减小接合的封装件300的厚度，因为管芯连接件128的全部或一部分嵌入在管芯200的钝化层212内。
此外，钝化层212可以用作管芯100和200之间的焊料掩模和物理支撑。如此，底部填料不需要在管芯100和200之间分配，例如，围绕管芯连接件128。通过省略底部填料，可以减小管芯100和管芯200之间的寄生电容和电阻。
图2A至图2C示出了根据一些实施例的形成接合的封装件400的中间工艺步骤的截面图。在图2A至图2C中，第一封装组件(例如，管芯100)接合到第二封装组件(例如，管芯200)。管芯100和管芯200可以类似于上面关于图1A至图1H讨论的部件，其中相同的附图标记表示使用相同工艺形成的相同部件。为简洁起见，省略了对这些部件的进一步描述。
如上所述，管芯200包括接触焊盘214、最外钝化层212以及延伸穿过钝化层212并暴露接触焊盘214的开口216。在图2A至图2B中，接合焊盘308形成在开口216的侧壁和底面上。
在图2A中，晶种层302沉积在开口216的侧壁和底面上。在一些实施例中，晶种层302是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层302包括钛层和钛层上的铜层。可以使用例如PVD等形成晶种层302。
在晶种层302上形成导电材料。导电材料可以包括可选层304和层306。在一个实施例中，层304包括镍，并且层306包括铜。层304和/或306也可以是其他材料。每种导电材料(例如，层304和层306)可以通过镀形成，例如电镀或化学镀等。
随后，在图2B中，可以对晶种层302、层304和层306实施平坦化工艺(例如，化学机械抛光(CMP)、研磨、回蚀刻等)，以去除位于钝化层212的顶面上的晶种层302、层304和层306的部分。因此，沿着开口216的侧壁和底面形成接合焊盘308，接合焊盘308延伸穿过钝化层212。接合焊盘308还可以物理地和电气地连接到由开口216暴露的接触焊盘214。
在图2C中，管芯200混合接合到管芯100以形成封装件400。混合接合可以包括使用如上关于图1G所述的类似工艺在钝化层112和212之间形成电介质-电介质接合。混合接合还可以包括回流工艺，回流工艺将管芯100的管芯连接件128接合到管芯200的接合焊盘308。回流工艺可以类似于上面关于图1H描述的工艺。例如，可以回流管芯连接件128的焊料层126以物理地和电气地接合到管芯200的接合焊盘308。
图3A至图3E示出了根据一些实施例的通过将第一封装组件(例如，管芯100)接合到第二封装组件(例如，管芯200)来形成接合的封装件500的中间工艺步骤的截面图。管芯100和管芯200可以类似于上面关于图1A至图1H讨论的部件，其中相同的附图标记表示使用相同工艺形成的相同部件。为简洁起见，省略了对这些部件的进一步描述。
如上所述，管芯200包括接触焊盘214、最外钝化层212以及延伸穿过钝化层212并暴露接触焊盘214的开口216。在图3A至图3B中，接合焊盘408形成在开口216的侧壁和底面上。
在图3A中，晶种层302、可选的导电层304和导电层306依次形成在开口216的侧壁和底面上。晶种层302、层304和层306可以类似于图2B中公开的部件，其中相同的附图标记表示使用相同的工艺形成的相同元件。
如图3A进一步所示，光刻胶402形成在层306上方并延伸到开口216中。光刻胶402可以通过旋涂等形成，并且可以暴露于光以进行图案化。尽管示出了单个光刻胶层，但是光刻胶402可以包括与背侧抗反射涂层(BARC)、硬掩模层等组合的一层或多层光敏材料。光刻胶402的图案对应于随后形成的导电针(参见图3B)。图案化形成穿过光刻胶402的开口404以暴露层306。
在图3B中，导电材料形成在光刻胶402的开口404中和层306的暴露部分上。导电材料可包括导电针406。导电针406可称为针，因为每根针都相对较薄。例如，每个导电针406的宽度W3可以在约0.5μm至约5μm的范围内。在一些实施例中，导电针406包括铜。导电针406也可以是其他材料。例如，导电针406可以包括镍、金或任何其他导电材料，其可以在回流之后与焊料反应以形成金属间化合物(IMC)。导电针406可以通过镀形成，例如电镀或化学镀等。镀工艺可以使用暴露的层306作为晶种层，而不需要单独的晶种层。尽管示出了三个导电针406，但是可以在层306上形成任何数量的导电针406。
在图3C中，去除光刻胶402。可以通过可接受的灰化或剥离工艺去除光刻胶402，例如使用氧等离子体等。一旦去除光刻胶402，然后可以对晶种层302、层304和层306实施平坦化工艺(例如，化学机械抛光(CMP)、研磨、回蚀刻等)，以去除位于钝化层212的顶面上的晶种层302、层304和层306的部分。因此，沿着开口216的侧壁和底面形成接合焊盘408，接合焊盘408延伸穿过钝化层212。接合焊盘408可以物理地和电气地连接到由开口216暴露的接触焊盘214，并且接合焊盘408还可以包括向上延伸的导电针406(例如，在远离衬底202的方向上)。
在图3D中，管芯100和管芯200对准并接触在一起。在使管芯100和200接触时，接合焊盘408的导电针406的上部可以嵌入管芯200的管芯连接件128中。例如，导电针406的上部可以延伸到焊料层126中，同时导电针406的下部可以保留在焊料层126的外部。嵌入导电针406可以是导电针406的材料由与焊料层126相比相对硬的材料形成的结果。例如，在一个实施例中，导电针406是铜，焊料层是铟层。铟的弹性模量和硬度分别为11GPa和0.009GPa，而铜的弹性模量和硬度分别为110GPa和2.15GPa。由于导电针406的相对硬度，导电针406可以至少部分地嵌入在焊料层126内。
在图3E中，管芯200混合接合到管芯100以形成封装件500。混合接合可以包括使用如上关于图1G所述的类似工艺在钝化层112和212之间形成电介质-电介质接合。在接合钝化层112和212之后，封装件500可以具有与图3D中所示类似的配置。例如，焊料层126可以保持与层306物理分离，并且导电针406的上部延伸到管芯连接件128的焊料层126中。混合接合可以进一步包括回流工艺，回流工艺将管芯100的管芯连接件128接合到管芯200的接合焊盘408。回流工艺可以类似于上面关于图1H描述的工艺。例如，可以回流管芯连接件128的焊料层126以物理地和电气地接合到管芯200的接合焊盘408。此外，接合焊盘408的导电针406可以嵌入在管芯连接件128的回流的焊料层126内。作为回流的结果，可以在焊料层126与接合焊盘408/导电针406接合的区域周围形成IMC。由于将导电针406嵌入管芯连接件128中，可以在管芯100和管芯200之间制成改进的电连接。在接合期间将导电针406部分地嵌入管芯连接件128中可以进一步扩大管芯连接件128的高度和/或开口216的宽度的工艺窗口，这提高了制造封装件500的便利性。
图4A至图4F示出了根据一些实施例的通过将第一封装组件(例如，管芯100)接合到第二封装组件(例如，管芯200)来形成接合的封装件600的中间工艺步骤的截面图。管芯100和管芯200可以类似于上面关于图1A至图1H讨论的部件，其中相同的附图标记表示使用相同工艺形成的相同部件。为简洁起见，省略了对这些部件的进一步描述。
如上所述，管芯200包括接触焊盘214、最外钝化层212以及延伸穿过钝化层212并暴露接触焊盘214的开口216。在图4A至图4D中，类似于管芯连接件128的管芯连接件514形成在开口216中的接触焊盘214上。在图4A至图4E的实施例中，管芯200的开口216中的管芯连接件514可以代替管芯100的管芯连接件128。
在图4A中，晶种层502形成在开口216的侧壁和底面上。晶种层502可以由与上面关于图2A描述的晶种层302类似的材料和/或工艺形成。
如图4A进一步所示，光刻胶504形成在层502上方并延伸到开口216中。光刻胶504可以通过旋涂等形成，并且可以暴露于光以进行图案化。尽管示出了单个光刻胶层，但是光刻胶5o4可以包括与背侧抗反射涂层(BARC)、硬掩模层等组合的一层或多层光敏材料。图案化形成穿过光刻胶504的开口506以暴露晶种层502。
在图4B中，导电材料形成在光刻胶504的开口506中和晶种层502的暴露部分上。导电材料可以包括可选层508、位于层508上的层510以及位于层510上的焊料层512。可选层508可以使用与层122类似的工艺由类似的材料形成；层510可以使用与层124类似的工艺由类似的材料形成；焊料层512可以使用与上面参照图1C描述的焊料层126类似的工艺由类似的材料形成。
然后，在图4C中，去除光刻胶504和晶种层502的其上未形成导电材料(例如，可选层508、层510和焊料层512)的部分。可以通过可接受的灰化或剥离工艺去除光刻胶504，例如使用氧等离子体等。一旦去除光刻胶504，就去除晶种层502的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿或干蚀刻。晶种层502的剩余部分和导电材料(例如，可选层508、层510和层512)形成管芯连接件514。管芯连接件514设置在开口216中并且至少部分地延伸穿过管芯200的钝化层212。
管芯连接件514包括凸块下金属(UBM)514A和位于UBM 514A上的焊料层512。UBM514A包括晶种层502的剩余部分、可选层508和层510。已经观察到，这种相对较低的回流温度允许管芯200在相对较低的温度下在后续工艺步骤中接合，这有利地降低了对管芯200的内部部件(例如，器件104)的损坏的风险。
图4D示出了在后续工艺步骤中对管芯连接件514的UBM 514A的可选蚀刻。可以蚀刻UBM 514A以在UBM 514A和焊料层512之间的界面处减小UBM 514A的表面积。如关于UBM128A的可选蚀刻所述，通过减小该表面积，可以有利地增加在回流期间由焊料层512穿过的垂直距离。例如，当UMB 514A的表面区域处的表面积较小时，焊料层512可以在回流期间形成具有更大高度的珠子。
可以使用例如湿蚀刻来蚀刻UBM 514A，湿蚀刻蚀刻位于焊料层512正下方的层510。在一个实施例中，湿蚀刻是选择性湿蚀刻，其蚀刻层510比蚀刻可选层508更快。例如，对于图4D中所示的UBM配置，可以使用氯化氢(HCl)来蚀刻层510。
此外，因为晶种层502使用与层510不同的工艺形成，所以即使当晶种层502和层510包含相同的材料时，也可以使用相同的蚀刻工艺以低于层510的速率蚀刻晶种层502。例如，HCl湿蚀刻可以以比包含铜的镀层(例如，层510)更低的速率选择性地蚀刻包括铜的溅射层(晶种层502)。在蚀刻之后，层510的宽度W4可以在约1μm至约19μm的范围内并且可以小于晶种层502的宽度W5。晶种层502的宽度W5可以在约1.5μm至约20μm的范围内。以这种方式，晶种层502和层510可以包括相同的材料，但是可以蚀刻层510而不过度蚀刻晶种层502。如果晶种层502被过度蚀刻，则管芯连接件514和下面的部件之间的粘合可能会无意地降低，从而导致制造缺陷。
在图4E中，管芯100和管芯200对准并接触在一起。在使管芯100和200接触时，管芯连接件514与管芯100的接触焊盘114物理分离。例如，可以在管芯连接件514的焊接层512和管芯的接触焊盘114之间设置间隙。
在图4F中，管芯200混合接合到管芯100以形成封装件600。混合接合可以包括使用如上关于图1G所述的类似工艺在钝化层112和212之间形成电介质-电介质接合。在接合钝化层112和212之后，封装件600可以具有与图4E中所示类似的配置。例如，焊料层512可以保持与接触焊盘114物理分离。
混合接合可以进一步包括回流工艺，回流工艺将管芯200的管芯连接件514接合到管芯100的接触焊盘114。回流工艺可以类似于上面关于图1H描述的工艺。例如，可以回流管芯连接件514的焊料层512以物理地和电气地接合到管芯100的接触焊盘114。
图5示出了根据一些实施例的封装件750的截面图。封装件750包括使用类似于上面讨论的那些的接合配置接合到多个其他封装组件(例如，堆叠管芯700B、700C、700D和700E(例如，存储器管芯))的第一封装组件(例如，管芯700A(例如，逻辑管芯))。管芯700A、700B、700C、700D和700E中的部件的材料和形成方法可以通过参考管芯100中的相同部件找到，其中管芯100中的相同部件以数字“1”开始，这些部件对应于管芯200中并且具有以数字“7”开始的附图标号的部件。例如，管芯700A、700B、700C、700D和700E中的每一个包括相应的半导体衬底702A、702B、702C、702D和702E，在半导体衬底上形成有源器件。互连结构706A、706B、706C、706D、706E和706F包括在一个或多个介电层中的一层或多层互连结构，互连结构将各个管芯700A、700B、700C、700D和700E的有源器件电互连以形成功能电路。管芯700A、700B、700C、700D和700E中的每一个还包括相应的多个通孔732A、732B、732C、732D和732E。多个通孔732A、732B、732C、732D和732E中的每一个穿过管芯700A、700B、700C、700D和700E的相应半导体衬底702A、702B、702C、702D和702E提供电连接。在一些实施例中，每个管芯700A、700B、700C、700D和700E的高度可以为约30μm或更小。
管芯700A、700B、700C、700D和700E的接合可以使用如上所述的混合接合配置。例如，钝化层712A、712B、712C、712D、712E、712F、712G和712H用于在管芯700A、700B、700C、700D和700E的相应界面处形成电介质-电介质接合。腔716A、716B、716C和716D延伸穿过相应的钝化层712B、712D、712E和712H。管芯连接件728A、728B、728C和728D设置在相应的腔716A、716B、716C和71D中，并且管芯连接件728A、728B、728C和728D通过在管芯700A、700B、700C、700D和700E的各个界面处的导体-导体接合提供电连接。每个管芯连接件728A、728B、728C和728D包括焊料区，焊料区被回流以形成导体-导体接合。管芯700A还包括管芯连接件730(例如，微凸块(μ凸块))，其可用于将封装件750接合到另一封装组件，例如衬底、封装衬底、中介层、印刷电路板、另一封装件、主板等。管芯连接件730可以设置在管芯700A的前侧上。因为使用混合配置，所以不需要在管芯700A、700B、700C、700D和700E之间分配底部填料。通过省略底部填料，可以减小寄生电容和电阻，从而改善电性能。此外，各种混合接合配置允许较低轮廓和高密度接合。例如，在一些实施例中，管芯700A、700B、700C、700D和700E之间的间隔高度H2可以是约5μm或更小。间隔高度H2可以等于管芯连接件728A、728B、728C和728D的高度，并且还可以等于钝化层712B、712D、712E和712H的高度。相邻的一对管芯700A、700B、700C、700D和700E之间的每个间隔高度H2可以与其他相邻的一对管芯700A、700B、700C、700D和700E之间的其他间隔高度H2相同或不同。
在一个实施例中，管芯连接件728A、728B、728C和728D的每个焊料区同时回流。例如，管芯700A、700B、700C、700D和700E可以对准，并且可以在相邻的钝化层712A、712B、712C、712D、712E、712F、712G和712H之间形成电介质-电介质接合，而无需回流管芯连接件728A、728B、728C和728D的任何焊料区。例如，管芯连接件728A、728B、728C和728D可以处于类似于上面关于图1G描述的状态。在堆叠管芯700A、700B、700C、700D和700E之后，可以实施单次回流以同时回流每个管芯连接件728A、728B、728C和728D。通过仅实施一次回流，减少了热工艺的数量，并且管芯700A、700B、700C、700D和700E不经受多次回流工艺，从而降低了制造缺陷的风险。
尽管图5示出了具有与图1H类似的配置的腔中的管芯连接件，但是可以使用上面讨论的任何接合配置。例如，接触焊盘可以形成在腔716A、716B、716C和716D的侧壁和底面上。接触焊盘可以(例如，如图3E所示)或可以不(例如，如图2C所示)具有导电针。此外，尽管在图5中将五个管芯接合在一起，但是在其他实施例中可以将更多或更少的管芯接合在一起。
图6示出了根据不同的实施例802、804、806和808的在接合之前的管芯700A、700B、700C、700D和700E的前侧和后侧上的可能的腔(例如，腔716A、716B、716C和716D)和管芯连接件(例如，管芯连接件728A，728B，728C和728D)配置的表格。其他配置也是可能的。例如，在一些实施例中，管芯连接件728A、728B、728C和728D可以形成在相应的腔716A、716B、716C和716D中(例如，如图4A至图4E中所述)。
这里讨论的实施例涉及用于封装的器件的接合结构。在各种实施例中，使用混合接合(电介质-电介质接合和导体-导体接合的组合)将两个或更多个芯片(有时称为管芯)接合在一起。通过采用混合接合方法，可以减小接合的封装件的轮廓，因为芯片连接件的尺寸(例如，高度)减小并且在接合之后不需要在芯片之间分配底部填料。在芯片之间省略底部填料还允许在接合的封装件中降低电阻和降低寄生电容，这改善了电性能。此外，在实施例混合接合工艺中使用的导体包括具有相对较低的回流温度的焊料区。因此，导体-导体接合可以在相对较低的温度下形成，这降低了损坏芯片的任何组件的风险。各种实施例提供用于在相对较低的温度下接合芯片的机制，同时仍然提供低轮廓以改善可靠性和电性能。
根据一个实施例，一种方法包括穿过第一封装组件的第一钝化层图案化腔，第一封装组件包括第一半导体衬底；以及将第一封装组件接合到第二封装组件。第二封装组件包括第二半导体衬底和第二钝化层。将第一封装组件接合到第二封装组件包括：将第一钝化层直接接合到第二钝化层；以及回流设置在腔中的导电连接件的焊料区，以将第一封装组件电连接到第二封装组件。在一个实施例中，导电连接件的形成包括：在第二钝化层中的第一导电部件上形成晶种层；在晶种层上形成第一金属层；在第一金属层上形成第二金属层；蚀刻第二金属层；以及在蚀刻第二金属层之后，在第二金属层上形成焊料区。在一个实施例中，蚀刻第二金属层减小了第二金属层的与第一金属层相对的表面处的第二金属层的表面积。在一个实施例中，晶种层的形成包括使用溅射工艺形成第一铜层，其中形成第二金属层包括使用镀工艺形成第二铜层，并且其中蚀刻第二金属层包括以比第一铜层更高的速率蚀刻第二铜层。在一个实施例中，该方法还包括在将第一封装组件接合到第二封装组件之前，在腔的侧壁和底面上镀第二导电部件。在一个实施例中，将第一封装组件接合到第二封装组件包括将第二导电部件的多个导电针嵌入焊料区中。在一个实施例中，该方法还包括在将第一封装组件接合到第二封装组件之前，在腔中形成导电连接件。在一个实施例中，将第一封装组件接合到第二封装组件是无焊剂接合工艺。
根据一个实施例，一种方法包括在第一封装组件的第一钝化层上形成第一晶种层；在第一晶种层上镀一个或多个第一导电层；在一个或多个第一导电层上形成焊料区；以及将第一封装组件接合到第二封装组件。第二封装组件包括第二钝化层。将第一封装组件接合到第二封装组件包括：将焊料区放置在延伸穿过第二钝化层的开口中，该开口暴露第二封装组件的接触焊盘；将第一钝化层直接接合到第二钝化层；以及回流焊料区以将焊料区延伸到第二封装组件的接触焊盘。在一个实施例中，一个或多个第一导电层包括铜层，并且所述方法还包括在将所述第一封装组件接合到所述第二封装组件之前，蚀刻铜层以减小铜层的表面积。在一个实施例中，该方法还包括在蚀刻铜层的同时，蚀刻第一晶种层以减小第一晶种层的宽度。在一个实施例中，由于蚀刻铜层和第一晶种层，第一晶种层的宽度比铜层的宽度减小得更少。在一个实施例中，在将第一钝化层直接接合到第二钝化层之后并且在回流焊料区之前，在焊料区和接触焊盘之间设置间隙。在一个实施例中，该方法还包括沿着开口的侧壁和底面形成接触焊盘。在一个实施例中，该方法还包括形成从接触焊盘向上延伸的多个导电区域，并且其中将焊料区放置在开口中包括将多个导电区域的至少一部分嵌入焊料区中。
根据一个实施例，一种封装件包括第一管芯，第一管芯包括：第一钝化层；和第一接触焊盘；第二管芯，接合到第一管芯，第二管芯包括：第二钝化层，与第一钝化层形成界面；和第二接触焊盘，位于第二钝化层的表面处；管芯连接件，从第二接触焊盘穿过第一钝化层延伸到第一接触焊盘，管芯连接件包括：凸块下金属(UBM)，包括位于第二导电层上的第一导电层，第一导电层具有与第二导电层不同的宽度；以及焊料区，与第一接触焊盘接触。在一个实施例中，凸块下金属还包括位于第一导电层和第二导电层之间的第三导电层，第三导电层比第一导电层和第二导电层宽。在一个实施例中，第一接触焊盘沿第一钝化层的侧壁设置。在一个实施例中，第一接触焊盘包括延伸到焊料区中的多个导电区域。在一个实施例中，第一导电层设置在第二导电层和焊料区之间，并且其中第二导电层比第一导电层宽。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
穿过第一封装组件的第一钝化层图案化腔，所述第一封装组件包括第一半导体衬底；以及
将所述第一封装组件接合到第二封装组件，所述第二封装组件包括第二半导体衬底和第二钝化层，其中，将所述第一封装组件接合到所述第二封装组件包括：
将所述第一钝化层直接接合到所述第二钝化层；和
回流设置在所述腔中的导电连接件的焊料区，以将所述第一封装组件电连接到所述第二封装组件。
2.根据权利要求1所述的方法，其中，所述导电连接件的形成包括：
在所述第二钝化层中的第一导电部件上形成晶种层；
在所述晶种层上形成第一金属层；
在所述第一金属层上形成第二金属层；
蚀刻所述第二金属层；以及
在蚀刻所述第二金属层之后，在所述第二金属层上形成所述焊料区。
3.根据权利要求2所述的方法，其中，蚀刻所述第二金属层减小了所述第二金属层的与所述第一金属层相对的表面处的所述第二金属层的表面积。
4.根据权利要求3所述的方法，其中，所述晶种层的形成包括使用溅射工艺形成第一铜层，其中，形成所述第二金属层包括使用镀工艺形成第二铜层，并且其中，蚀刻所述第二金属层包括以比所述第一铜层更高的速率蚀刻所述第二铜层。
5.根据权利要求1所述的方法，还包括在将所述第一封装组件接合到所述第二封装组件之前，在所述腔的侧壁和底面上镀第二导电部件。
6.根据权利要求5所述的方法，其中，将所述第一封装组件接合到所述第二封装组件包括将所述第二导电部件的多个导电针嵌入所述焊料区中。
7.根据权利要求1所述的方法，还包括在将所述第一封装组件接合到所述第二封装组件之前，在所述腔中形成所述导电连接件。
8.根据权利要求1所述的方法，其中，将所述第一封装组件接合到所述第二封装组件是无焊剂接合工艺。
9.一种形成半导体器件的方法，包括：
在第一封装组件的第一钝化层上形成第一晶种层；
在所述第一晶种层上镀一个或多个第一导电层；
在所述一个或多个第一导电层上形成焊料区；以及
将所述第一封装组件接合到第二封装组件，其中，所述第二封装组件包括第二钝化层，并且其中，将所述第一封装组件接合到所述第二封装组件包括：
将所述焊料区放置在延伸穿过所述第二钝化层的开口中，所述开口暴露所述第二封装组件的接触焊盘；
将所述第一钝化层直接接合到所述第二钝化层；和
回流所述焊料区以将所述焊料区延伸到所述第二封装组件的所述接触焊盘。
10.一种封装件，包括：
第一管芯，包括：
第一钝化层；和
第一接触焊盘；
第二管芯，接合到所述第一管芯，所述第二管芯包括：
第二钝化层，与所述第一钝化层形成界面；和
第二接触焊盘，位于所述第二钝化层的表面处；
管芯连接件，从所述第二接触焊盘穿过所述第一钝化层延伸到所述第一接触焊盘，所述管芯连接件包括：
凸块下金属(UBM)，包括位于第二导电层上的第一导电层，所述第一导电层具有与所述第二导电层不同的宽度；和
焊料区，与所述第一接触焊盘接触。
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