CN106548997A - 半导体器件和电子器件 - Google Patents

半导体器件和电子器件 Download PDF

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Publication number
CN106548997A
CN106548997A CN201610805906.XA CN201610805906A CN106548997A CN 106548997 A CN106548997 A CN 106548997A CN 201610805906 A CN201610805906 A CN 201610805906A CN 106548997 A CN106548997 A CN 106548997A
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China
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layer
diffusion impervious
width
side wall
prop
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CN106548997B (zh
Inventor
徐善京
柳承官
崔朱逸
赵泰济
权容焕
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

公开了一种电子器件和一种半导体器件。所述电子器件包括其上具有电气导电的接触焊盘的基底和在接触焊盘上的电气导电的连接端子。连接端子包括导电柱结构和在柱结构上延伸并且与柱结构的侧壁的突出部分接触的焊料层。柱结构可包括下柱层、在下柱层上的扩散阻挡层和在扩散阻挡层上的上柱层。在发明的一些附加实施例中，柱结构的侧壁的突出部分包括扩散阻挡层的上表面的最外侧部分。这可通过使扩散阻挡层的宽度当在横向剖面上观察时大于上柱层的宽度来获得。

Description

半导体器件和电子器件
本申请要求于2015年9月22日提交到韩国知识产权局的第10-2015-0133876号韩国专利申请的权益，该韩国专利申请的公开内容通过引用被全部包含于此。
技术领域
发明构思涉及半导体器件及其制造方法，更具体地，涉及包括凸点结构的半导体器件及其制造方法。
背景技术
随着电子产业的显著增长和用户需求的增加，电子器件具有较小的设计和增多的功能。也越来越多地需要用在电子器件中的半导体器件具有较小的设计和更多的功能。因此，需要包括具有微间距的连接端子的半导体器件。然而，因为包括在具有微间距的连接端子中的焊料层的量是少的，所以在半导体器件和外部器件之间难以提供可靠的电连接。
发明内容
发明构思提供了一种可以提供可靠的电连接的包括具有微间距的连接端子的半导体器件以及一种制造该半导体器件的方法。
根据发明的一些实施例，提供了一种电子器件，其包括其上具有电气导电的接触焊盘的基底和在接触焊盘上的电气导电的连接端子。连接端子包括电气导电的柱结构和在柱结构上延伸并且与柱结构的侧壁的突出部分接触的焊料层。在本发明的这些实施例的一些中，柱结构包括下柱层、在下柱层上的扩散阻挡层和在扩散阻挡层上的上柱层。在本发明的一些附加实施例中，柱结构的侧壁的突出部分包括扩散阻挡层的上表面的最外侧部分。这可通过使扩散阻挡层的宽度在横向剖面上观察时大于上柱层的宽度来获得，使得焊料层直接接触扩散阻挡层的上表面的最外侧部分(在回流后)。
根据发明的再进一步的实施例，扩散阻挡层的上表面构造为直接接触上柱层的底表面。当沿横向剖面观察时，扩散阻挡层的宽度也可以比下柱层的宽度大。基于这种构造，当沿垂直于扩散阻挡层的上表面的方向观察时，扩散阻挡层的上表面的最外侧部分将是环/环形形状(例如，圆环形、矩形环形等)。此外，焊料层可以直接接触上柱层的上表面与扩散阻挡层的上表面的环状部分的全部。上柱层和扩散阻挡层相对于焊料可以构造为相对于焊料具有不同回流特性的材料。
根据发明的再进一步的实施例，如从上柱层的上表面测量的焊料层的高度在扩散阻挡层的宽度的大约50％至大约90％的范围内。上柱层的宽度也可以在扩散阻挡层的宽度的大约80％至大约98％的范围内。类似地，扩散阻挡层的宽度在沿横向剖面观察时可以比下柱层的宽度大，下柱层的宽度可以在扩散阻挡层的宽度的大约80％至大约98％的范围内。在发明的再进一步的实施例中，上柱层的宽度可以在扩散阻挡层的宽度的大约30％至大约80％的范围内，并且下柱层的宽度在沿横向剖面观察时可以比上柱层的宽度小。
根据发明的附加实施例，钝化层设置在基底上。钝化层内可以具有暴露接触焊盘的上表面的开口。在这些实施例的一些中，所述开口至少局部地内衬有下金属层，下柱层的侧壁可以相对于下金属层的侧壁对齐(或凹进)。
根据发明构思的附加实施例，提供了一种半导体器件，所述半导体器件包括设置在基底上的导电焊盘和电连接到导电焊盘的连接端子。连接端子包括具有顺序地堆叠的下柱层、扩散阻挡层和上柱层的导电柱结构。导电柱结构还包括在导电柱结构的侧壁上的突出和设置在上柱层上并且接触突出的至少一部分的焊料层。
根据发明构思的另一方面，提供了一种半导体器件，所述半导体器件包括设置在基底上的导电焊盘和电连接到导电焊盘的连接端子。连接端子包括具有顺序地堆叠在导电焊盘上的下柱层、扩散阻挡层和上柱层的导电柱结构以及设置在上柱层与扩散阻挡层的一部分上的焊料层。上柱层的在平行于基底的顶表面的第一方向上的第一宽度可以比扩散阻挡层在第一方向上的第二宽度小。
根据本发明的再进一步的实施例，提供了一种形成电子器件的方法，其包括形成下柱层、在下柱层上的扩散阻挡层和在扩散阻挡层上的上柱层的组合件。在使上柱层的侧壁相对于焊料层的侧壁和扩散阻挡层的侧壁凹进之前，在上柱层上也形成焊料层。这个凹进步骤之后是使焊料层回流到上柱层的凹进的侧壁上和扩散阻挡层的上表面上。具体地，凹进步骤可以包括使上柱层的侧壁凹进以暴露扩散阻挡层的环状的上表面和焊料层的环状的下表面。然后，凹进之后是使焊料层回流到上柱层的凹进的侧壁上和扩散阻挡层的环状的上表面上。
根据发明构思的另一方面，提供了一种制造半导体器件的方法。这个方法可包括：在基底上形成包括开口的掩模层；在开口中顺序地形成下柱层、扩散阻挡层、上柱层和焊料层；去除掩模层；减小上柱层的宽度使得上柱层的侧壁比扩散阻挡层的侧壁进一步向内。
附图说明
通过以下结合附图的详细描述将更加清楚地理解发明构思的示例性实施例，在附图中：
图1是根据示例实施例的半导体器件的剖视图；
图2是根据示例实施例的半导体芯片的剖视图；
图3是根据示例实施例的半导体芯片的剖视图；
图4是根据示例实施例的半导体芯片的剖视图；
图5是根据示例实施例的半导体芯片的剖视图；
图6是根据示例实施例的半导体芯片的剖视图；
图7至图13是用于解释根据示例实施例的制造半导体芯片的方法的剖视图；
图14是用于解释根据示例实施例的制造半导体芯片的方法的剖视图；
图15至图18是用于解释根据示例实施例的制造半导体芯片的方法的剖视图；
图19是用于解释根据示例实施例的制造半导体芯片的方法的剖视图；
图20至图23是用于解释根据示例实施例的制造半导体芯片的方法的剖视图；以及
图24是用于解释根据示例实施例的制造半导体器件的方法的剖视图。
具体实施方式
现在，在下文中将参照示出了发明构思的元件的附图对发明构思进行更加充分地描述。然而，发明构思可以以许多不同的形式实施，并且不应被解释为限制于在此阐述的示例实施例。相反，提供这些实施例使得本公开是彻底的和完全的，并且将把发明构思的范围充分地传达给本领域的普通技术人员。在附图中，为了便于解释，可以夸大元件的尺寸和相关尺寸。
将理解的是，当元件或层被称作“形成在”另一元件“上”时，该元件或层可以直接地或间接地形成在所述另一元件上。即，例如，可以存在中间元件。相反，当元件被称作“直接地形成在”另一元件“上”时，没有中间元件存在。应以同样的方式解释用来描述元件之间关系的其它词语(例如，“在……之间”相对于“直接在……之间”等)。
将理解的是，尽管可以在这里使用术语第一、第二、第三等来描述各种元件，但是这些元件不应该受这些术语限制。这些术语仅用来将一个元件与另一元件区分开。因此，在不脱离示例实施例的教导的情况下，可将第一元件命名为第二元件，类似地，可将第二元件命名为第一元件。
在这里使用的术语仅用于描述示例实施例的目的而非意图限制发明构思的示例实施例。如在这里使用的，除非上下文另有明确指示，否则单数形式“一个”、“一种”和“该/所述”也意图包括复数形式。还将理解的是，术语“包括”及其变型用在这里使用时，表明存在陈述的特征、整体、步骤、操作、元件、组件和/或它们的组，但是不排除存在或添加一个或更多个其它的特征、整体、步骤、操作、元件、组件和/或它们的组。
除非另有限定，否则在这里使用的所有术语具有与示例实施例所属领域的普通技术人员通常理解的含义相同的含义。如这里使用的，术语“和/或”包括一个或更多个相关所列项目的任何组合和所有组合。诸如“……中的至少一个(种)”的表述位于一列元件(要素)之后时，修饰整列的元件(要素)，而不是修饰该列中的个别元件(要素)。
图1是根据示例实施例的半导体器件1的剖视图。参照图1，半导体器件1可以包括半导体芯片100、封装基底200以及被构造为连接半导体芯片100和封装基底200的连接端子140。半导体器件1可以是通过使用连接端子140以面朝下的方式将半导体芯片100安装在封装基底200上的倒装芯片封装件。
半导体芯片100可以包括半导体基底110和形成在半导体基底110上并且可以对外部应用半导体器件1的电路功能的导电焊盘122。包括针对半导体器件1的电路功能的单独的单元元件的电路单元可以通过使用半导体制造工艺来形成在半导体芯片100上。即，晶体管、电阻器、电容器、导电布线和设置在它们之间的绝缘层可以形成在半导体芯片100上。
导电焊盘122可以暴露于作为半导体器件1的电路单元的最后的保护层的钝化层124。导电焊盘122可以电连接到半导体器件1的电路单元并且可以将半导体器件1的电路单元电连接到封装基底200。
诸如存储器元件(例如，动态随机存取存储器(DRAM)或闪存)、逻辑元件(例如，微控制器)、模拟元件、数字信号处理器元件、芯片上系统元件或它们的组合的各种半导体元件中的任何可以形成在半导体芯片100上。
封装基底200可以包括基础基底210、连接焊盘220、绝缘层230、外部端子连接焊盘240和外部端子250。基础基底210可以包括从例如酚醛树脂、环氧树脂和聚酰亚胺中选择的至少一种材料。连接焊盘220可以形成在基础基底210的一个表面上并且可以将封装基底200和连接端子140电连接。绝缘层230可以形成在基础基底210的顶表面上并且可以暴露连接焊盘220的顶表面的一部分。外部端子连接焊盘240可以形成在基础基底210的另一表面上，外部端子250可以附着到外部端子连接焊盘240。例如，外部端子250可以是焊料球。外部端子250可以将半导体器件1电连接到外部电子器件。
半导体芯片100的连接端子140可以附着到封装基底200的连接焊盘220，因此半导体芯片100的导电焊盘122可以电连接到连接焊盘220。连接端子140可以包括导电柱结构150和焊料层160。导电柱结构150和焊料层160将在下面参照图2进行详细地解释。底部填充层170可以形成在半导体芯片100和封装基底200之间的空间中。底部填充层170可以围绕连接端子140的侧壁并且可以填充相邻的连接端子140之间的空间。成型材料180可以形成为覆盖半导体芯片100的顶表面和侧壁。不同于图1中，可以不形成底部填充层170，并且成型材料180可以形成在半导体芯片100的顶表面和侧壁上以及连接端子140的侧壁上来填充半导体芯片100与封装基底200之间的空间。
图2是根据示例实施例的半导体芯片100的剖视图。与图1一起参照图2，导电焊盘122可以设置在半导体基底110的顶表面上。导电焊盘122可以包括铝(Al)、钨(W)、铜(Cu)、镍(Ni)或它们的组合。虽然未在图2中示出，但导电焊盘122可以电连接到用于形成在半导体基底110上的半导体器件1的电路单元的单独的单元元件(未示出)。
钝化层124可以设置在半导体基底110的顶表面上并且可以覆盖导电焊盘122的顶表面的一部分。钝化层124可以包括诸如光敏聚酰亚胺(PSPI)、氮化硅或氧化硅的绝缘材料。钝化层124可以作为用于保护形成在半导体基底110上的单独的单元元件免受外部撞击或湿气影响的保护膜。钝化层124可以具有开口124H，导电焊盘122的顶表面的一部分可以通过开口124H(例如见图7)暴露。
下金属层130可以覆盖导电焊盘122的一部分和相邻于导电焊盘122设置的钝化层124的一部分。下金属层130可以形成在连接端子140和导电焊盘122之间并且可以是用于形成连接端子140的种子层、粘附层和/或阻挡层。在示例实施例中，下金属层130可以包括铬(Cr)、钨(W)、钛(Ti)、铜(Cu)、镍(Ni)、铝(Al)、钯(Pd)、金(Au)或它们的组合。
虽然下金属层130是图2中的一层，但下金属层130可以具有包括多个金属层的堆叠结构。例如，下金属层130可以包括顺序地堆叠在导电焊盘122和钝化层124上的第一金属层、第二金属层和/或第三金属层。第一金属层可以作为用于将形成在第一金属层之上的连接端子140稳固地附着到导电焊盘122和/或钝化层124的粘附层。第一金属层可以包括可以容易地粘附到钝化层124的金属材料。例如，第一金属层可以包括Ti、Ti-W、Cr和Al中的至少一种。第二金属层可以作为用于防止包括在连接端子140中的金属材料扩散到形成在第二金属层下的半导体基底110中的阻挡层。第二金属层可以包括Cu、Ni、Cr-Cu和Ni-钒(V)中的至少一种。第三金属层可以作为用于改善用于形成连接端子140的种子层或焊料层的润湿特性的润湿层。第三金属层可以包括Ni、Cu和Al中的至少一种。
连接端子140可以设置在下金属层130上，下金属层130可以设置在连接端子140和导电焊盘122之间。连接端子140可以包括导电柱结构150和焊料层160。
导电柱结构150可以包括顺序地堆叠在下金属层130上的下柱层152、扩散阻挡层154和上柱层156。下柱层152可以设置在下金属层130上，下柱层152的侧壁可以与下金属层130的侧壁对齐。下柱层152可以包括Ni、Cu、Pd、铂(Pt)、Au或它们的组合。扩散阻挡层154可以设置在下柱层152上。扩散阻挡层154可以包括Ni、钴(Co)、Cu或它们的组合。上柱层156可以设置在扩散阻挡层154上并且可以包括Ni、Cu、Pd、Pt、Au或它们的组合。
在示例实施例中，上柱层156和扩散阻挡层154可以包括不同的材料。另外，上柱层156和扩散阻挡层154可以包括具有相对于彼此的蚀刻选择性的不同的材料。然而，发明构思不限于此。上柱层156和下柱层152可以包括相同的材料。然而，发明构思不限于此，上柱层156和下柱层152可以包括不同的材料。
如图2中所示，上柱层156可以具有第一宽度W1，第一宽度W1可以比扩散阻挡层154的第二宽度W2小。例如，上柱层156的第一宽度W1可以在扩散阻挡层154的第二宽度W2的大约80％至大约98％的范围，但不限于此。另外，下柱层152的第三宽度W3可以比扩散阻挡层154的第二宽度W2小。例如，下柱层152的第三宽度W3可以在扩散阻挡层154的第二宽度W2的大约80％至大约98％的范围，但不限于此。
因为上柱层156的第一宽度W1比扩散阻挡层154的第二宽度W2小，所以扩散阻挡层154的顶表面的一部分不会被上柱层156覆盖。扩散阻挡层154的顶表面的未被上柱层156覆盖的部分(即，扩散阻挡层154的外周边的顶表面)被称作扩散阻挡层154的边缘顶表面154U。扩散阻挡层154的边缘顶表面154U可以从导电柱结构150的侧壁向外突出。
另外，因为下柱层152的第三宽度W3比扩散阻挡层154的第二宽度W2小，所以扩散阻挡层154的底表面的一部分不会被下柱层152覆盖。因此，扩散阻挡层154的突出150O可以由扩散阻挡层154的边缘顶表面154U、侧壁154S和边缘底表面154L(即，扩散阻挡层154的底表面的未接触下柱层152的部分)限定。突出150O可以从导电柱结构150的侧壁向外突出。
上柱层156可以具有第一高度H1，扩散阻挡层154可以具有第二高度H2，第一高度H1和第二高度H2中的每个可以在从大约2微米至大约30微米的范围。下柱层152可以具有第三高度H3，第三高度H3可以在从大约5微米至大约100微米的范围。然而，发明构思不限于此。第一高度至第三高度H1、H2和H3可以根据半导体芯片100的厚度和/或宽度、导电焊盘122的间距以及包括在上柱层156、扩散阻挡层154和/或下柱层152中的每个中的材料的类型来适当地选择。
焊料层160可以设置在扩散阻挡层154的边缘顶表面154U的至少一部分上以及上柱层156的侧壁156S和顶表面上。在示例实施例中，焊料层160可以具有球形形状或球体形状。焊料层160可以包括锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、Cu、银(Ag)、锌(Zn)、铅(Pb)和/或它们的合金。例如，焊料层160可以包括Sn、Pb、Sn-Pb、Sn-Ag、Sn-Au、Sn-Cu、Sn-Bi、Sn-Zn、Sn-Ag-Cu、Sn-Ag-Bi、Sn-Ag-Zn、Sn-Cu-Bi、Sn-Cu-Zn或Sn-Bi-Zn。
如图2中所示，焊料层160可以覆盖上柱层156的整个顶表面和整个侧壁156S，并且可以基本上设置在扩散阻挡层154的边缘顶表面154U的整个区域上。因此，当与焊料层设置在具有圆柱形状的导电柱结构上的情况(即，焊料层设置在未形成有突出150O的具有圆柱形形状的导电柱结构的顶表面上的情况)相比时，焊料层160和导电柱结构150之间的接触面积可以增加。因此，可以增加在未塌陷的情况下可以在导电柱结构150上设置的焊料层160的量(或高度)。
通常，随着焊料层的量增加，当半导体芯片附着到封装基底或连接焊盘时可以由于焊料层而提供充分的电连接。具体地，用于将半导体芯片附着到封装基底的工艺可以在为了使焊料层的一部分熔化的足够高的温度下执行，半导体芯片会在这样高的温度下翘曲。当焊料层的量相对小时，设置在半导体芯片的翘曲的边缘部分上的焊料层不会接触封装基底，从而未在半导体芯片和封装基底之间提供可靠的电连接。因此，焊料层越大，与封装基底的电连接越可靠。然而，因为焊料层由于回流工艺而形成为具有球形形状(或球体形状)，所以可以设置在导电柱结构上的焊料层的量受导电柱结构的顶表面的面积限制。如果焊料层的量太大，那么焊料层在回流工艺过程中会熔化并且会沿着导电柱结构的侧壁向下流动，或者焊料层会塌陷并且设置在导电柱结构上的焊料层的量会进一步减少。
如上所述，焊料层160可以覆盖上柱层156的整个顶表面和整个侧壁156S，并且可以基本上设置在扩散阻挡层154的边缘顶表面154U的整个区域上。因此，可以在焊料层160和导电柱结构150之间确保相对大的接触面积，因此在未塌陷的情况下可以在导电柱结构150上设置的焊料层160的量(或高度)可以是相对大的。
由虚线示出的中间层160I可以形成在焊料层160和导电柱结构150之间的接触界面上。中间层160I可以包括由包括在焊料层160和导电柱结构150中的金属材料之间在相对高的温度下的反应形成的金属间化合物(IMC)。例如，当导电柱结构150包括Cu和/或Ni并且焊料层160包括Sn和/或Cu时，中间层160I可以包括(Cu,Ni)6Sn5、(Cu,Ni)3Sn4和(Cu,Ni)3Sn中的至少一种。然而，中间层160I的材料或成分不限于此，并且可以根据导电柱结构150的材料、焊料层160的材料以及回流工艺的温度和时间而改变。
当IMC在焊料层160和导电柱结构150之间的接触界面上形成为适当的厚度时，可以改善焊料层160的粘附特性并且还可以改善焊料层160的结构稳定性。如图2中所示，因为中间层160I形成在焊料层160的与上柱层156的顶表面和侧壁156S以及扩散阻挡层154的边缘顶表面154U接触的部分中，所以中间层160I可以具有相对大的表面积。具体地，当与焊料层设置在具有圆柱形形状的导电柱结构上的情况(即，焊料层设置在未形成有突出150O的具有圆柱形形状的导电柱结构的顶表面上的情况)相比时，中间层160I可以具有相对大的表面积。通常，中间层160I可以包括具有比焊料层160的熔点高的熔点的材料，或可以包括具有比焊料层160的机械强度大的机械强度的材料。因此，当中间层160的表面积相对大时，在未塌陷的情况下可以在导电柱结构150上设置的焊料层160的量可以是相对大的。
在示例实施例中，焊料层160可以具有从导电柱结构150的顶表面起的第四高度H4。例如，焊料层160的第四高度H4可以在扩散阻挡层154的第二宽度W2的大约50％至大约90％的范围。当第四高度H4小于50％并且半导体芯片100翘曲时，会难以提供与连接焊盘220的可靠电连接。当第四高度H4大于90％时，焊料层160会沿着导电柱结构150的侧壁向下流动或会在回流工艺过程中塌陷。然而，发明构思不限于此。
在示例实施例中，扩散阻挡层154的第二宽度W2可以比上柱层156的第一宽度W1和/或下柱层152的第三宽度W3大，焊料层160的第四高度H4可以在扩散阻挡层154的第二宽度W2的大约50％至大约90％的范围。因此，焊料层160的第四高度H4可以是相对大的，因此焊料层160的体积也可以是相对大的。
突出150O可以防止焊料层160在焊料层160的回流工艺或在为了将焊料层160附着到外部连接焊盘的工艺过程中沿着导电柱结构150的侧壁向下流动。具体地，可以在为了使焊料层160的一部分熔化的足够高的温度下执行这些工艺，在这种情况下，焊料层160的流动性可以增加。如果焊料层160的该部分沿着导电柱结构150的侧壁向下流动，那么焊料层160会通常与下柱层152的侧壁反应而进一步形成不期望的IMC，因此设置在导电柱结构150的顶表面上的焊料层160的量会进一步减少。另外，一旦形成不期望的IMC，就会在焊料层160中形成空隙，当半导体芯片100使用很长时间时，连接端子140的可靠性会由于该空隙而降低。
如图2中所示，导电柱结构150可以包括形成在侧壁上的突出150O，突出150O可以通过扩散阻挡层154的边缘顶表面154U、侧壁154S和边缘底表面154L来限定。设置在导电柱结构150上的焊料层160沿导电柱结构150的突出150O向下流经的流动路径可以包括扩散阻挡层154的侧壁154S和边缘底表面154L，因此该流动路径可以是相对长的。因此，可以避免焊料层160沿导电柱结构150的侧壁向下流动或者因此在焊料层160中形成空隙的现象。
如图2中所示，具有预定厚度的中间层160I可以形成在导电柱结构150和焊料层160之间的接触界面上(即，在焊料层160与上柱层156的顶表面和侧壁156S以及扩散阻挡层154的边缘顶表面154U之间的接触界面)。因为中间层160I可以形成在焊料层160的与扩散阻挡层154的顶表面接触的边缘部分上，所以IMC会在焊料层160的与扩散阻挡层154的顶表面接触的最下部表面上形成为预定厚度。如上所述，因为中间层160I可以包括具有比焊料层160的熔点和机械强度大的熔点和机械强度的材料并且中间层160I形成在焊料层160的边缘部分上，所以可以避免焊料层160沿导电柱结构150的侧壁向下流动或者因此在焊料层160中形成空隙的现象。
根据半导体芯片100，焊料层160可以接触导电柱结构150的突出150O的顶表面。焊料层160和导电柱结构150之间的接触面积可以是相对大的，因此在未塌陷的情况下可以在导电柱结构150上设置的焊料层160的量或高度可以增加。另外，突出150O可以防止焊料层160在焊料层160的回流工艺或在为了将焊料层160附着到外部连接焊盘的工艺过程中沿着导电柱结构150的侧壁向下流动。因此，半导体芯片100可以提供可靠的电连接。
图3是根据示例实施例的半导体芯片100A的剖视图。在图3中，与图1和图2中的附图标记相同的附图标记表示相同的元件。参照图3，底切130R可以通过去除下金属层130A的在导电柱结构150的侧壁下的一部分而形成在下金属层130A周围。下金属层130A的侧壁可以不与导电柱结构150的侧壁对齐并且可以比导电柱结构150的侧壁更向内设置。
在用于形成下金属层130A的示例工艺中，下金属层130A可以通过以下步骤来形成：形成覆盖导电焊盘122和钝化层124的初始下金属层130P；在初始下金属层130P上形成导电柱结构150；以及通过使用导电柱结构150作为蚀刻掩模来去除初始下金属层130P的未被导电柱结构150覆盖的一部分。例如，初始下金属层130P的该部分可以通过利用使用蚀刻剂的湿法蚀刻工艺来移除，下金属层130A在蚀刻剂中的蚀刻速度可以是相对高的。在这种情况下，在导电柱结构150的侧壁下的下金属层130A可以被进一步蚀刻预定的宽度，因此可以在下金属层130A周围形成底切130R。
虽然在图3中底切130R具有竖直的侧壁，但发明构思不限于此，底切130R可以具有倾斜的侧壁。例如，下金属层130A可以具有包括例如顺序地堆叠在导电焊盘122和钝化层124上的第一金属层、第二金属层和/或第三金属层的多个金属层的堆叠结构。当包括在第一金属层、第二金属层和/或第三金属层中的金属材料彼此不同时，在形成下金属层130A的工艺中第一金属层、第二金属层和/或第三金属层在蚀刻剂中的蚀刻速度可以彼此不同。在这种情况下，第一金属层、第二金属层和/或第三金属层可以被蚀刻不同的宽度，因此，底切130R可以具有倾斜的侧壁。
图4是根据示例实施例的半导体芯片100B的剖视图。在图4中，与图1至图3中的附图标记相同的附图标记表示相同的元件。参照图4，导电柱结构150A可以具有相对大的高度。突出150O可以形成在导电柱结构150A的侧壁上，且突出150O的宽度也可以是相对大的。
在示例实施例中，上柱层156A的第一宽度W1A可以在扩散阻挡层154的第二宽度W2的大约30％至大约80％的范围。上柱层156A的第一高度H1A可以比扩散阻挡层154的第二高度H2大。然而，发明构思不限于此。
上柱层156A的第一宽度W1A可以在扩散阻挡层154的第二宽度W2的大约30％至大约80％的范围，因此扩散阻挡层154的未被上柱层156A覆盖的边缘顶表面154U可以具有更大的宽度。另外，因为上柱层156A的第一高度H1A是相对大的，所以导电柱结构150A和焊料层160A之间的接触面积(或焊料层160A与上柱层156A的顶表面和侧壁156S以及扩散阻挡层154的边缘顶表面154U之间的接触面积)可以进一步增大。因此，在未塌陷的情况下可以在导电柱结构150A上设置的焊料层160A的量可以是相对大的。
如图4中所示，中间层160IA可以形成在导电柱结构150A和焊料层160A之间的接触界面上，中间层160IA的表面积可以是相对大的。中间层160IA可以包括诸如(Cu,Ni)6Sn5、(Cu,Ni)3Sn4或(Cu,Ni)3Sn的IMC。中间层160IA可以包括具有比焊料层160A的熔点或机械强度大的熔点或机械强度的材料，因此在未塌陷的情况下可以在导电柱结构150A上设置的焊料层160A的量可以进一步增加。
在示例实施例中，下柱层152A的第三宽度W3A可以在扩散阻挡层154的第二宽度W2的大约30％至大约80％的范围。另外，下柱层152A的第三高度H3A可以比扩散阻挡层154的第二高度H2或上柱层156A的第一高度H1A大。
下柱层152A的第三宽度W3A可以在扩散阻挡层154的第二宽度W2的大约30％至大约80％的范围，因此扩散阻挡层154的未与柱层152A接触的边缘底表面154L可以具有更大的宽度。因此，焊料层160A在回流工艺或在为了将连接端子140A附着到外部连接焊盘的工艺中沿着导电柱结构150A的侧壁向下流经的流动路径可以进一步增长，因此可以避免焊料层160A沿导电柱结构150A的侧壁向下流动或者因此在焊料层160A中形成空隙的现象。
因为下柱层152A的第三宽度W3A可以比扩散阻挡层154的第二宽度W2或焊料层160A的宽度小，所以相邻的下柱层152A之间的距离可以增大。因为在具有微间距的半导体芯片100中减小了导电焊盘122的间距，所以相邻的导电柱结构150A之间的距离也减小。然而，在图4中的半导体芯片100B中，相邻的下柱层152A之间的距离可以比相邻的扩散阻挡层154之间的距离或相邻的焊料层160A之间的距离大。即，即使当导电焊盘122之间的间距减小时，由于下柱层152A的小的第三宽度W3A和大的第三高度H3A也可以在下柱层152A周围确保相对大的空间。当半导体芯片100B附着到封装基底200的连接焊盘220(见图1)然后形成围绕焊料层160A和导电柱结构150A的侧壁的底部填充层170(见图1)时，底部填充层170可以没有空隙地填充在下柱层152A周围的相对大的空间中。
如上描述，用于将半导体芯片附着到封装基底的示例工艺可以在为了使焊料层的一部分熔化的足够高的温度下执行，半导体芯片会在这样高的温度下翘曲。当连接端子的高度小时，设置在半导体芯片的边缘部分上的焊料层在半导体芯片翘曲时不可能接触封装基底，从而在半导体芯片和封装基底之间提供不了可靠的电连接。然而，在图4中的半导体芯片100B中，焊料层160A的第四高度H4A可以是相对大的并且导电柱结构150A的高度(即，第一高度至第三高度H1A、H2和H3A的总和)可以是相对大的。因此，即使当半导体芯片100B在高温下翘曲时，设置在半导体芯片100B的边缘部分上的焊料层160A可以充分地接触封装基底200，从而在半导体芯片100B和封装基底200之间提供了可靠的电连接。
图5是根据示例实施例的半导体芯片100C的剖视图。在图5中，与图1至图4中的附图标记相同的附图标记表示相同的元件。参照图5，下柱层152B可以具有第三宽度W3B，第三宽度W3B可以比上柱层156的第一宽度W1小。因为下柱层152B的第三宽度W3B比上柱层156的第一宽度W1小，所以当半导体芯片100C附着到封装基底200(见图1)的连接焊盘220(见图1)然后形成围绕焊料层160和导电柱结构150B的侧壁的底部填充层170时，底部填充层170可以没有空隙地填充在下柱层152B周围的相对大的空间中。
在示例实施例中，下柱层152B可以包括与上柱层156的材料不同的材料。在用于形成下金属层130的示例工艺中，下金属层130可以通过以下步骤来形成：形成覆盖导电焊盘122和钝化层124的初始下金属层130P(见图8)；在初始下金属层130P上形成导电柱结构150B；然后通过使用导电柱结构150B作为蚀刻掩模来去除初始下金属层130P的未被导电柱结构150B覆盖的一部分。例如，初始下金属层130P的该部分可以通过利用使用蚀刻剂的湿法蚀刻工艺来去除，导电柱结构150B的暴露于蚀刻剂的侧壁也可以被去除预定的宽度。例如，下柱层152B和上柱层156可以包括不同的材料，下柱层152B和上柱层156在蚀刻剂中的蚀刻速度可以彼此不同。具体地，当下柱层152B的蚀刻速度比上柱层156的蚀刻速度高时，如图5中所示，下柱层152B的第三宽度W3B可以比上柱层156的第一宽度W1小。然而，发明构思不限于此。当下柱层152B的蚀刻速度比上柱层156的蚀刻速度低时，与图5中不同，可以获得下柱层152B的第三宽度W3B比上柱层156的第一宽度W1大的半导体芯片100C。
在其它示例实施例中，下柱层152B可以包括与上柱层156的材料相同的材料。例如，在用于形成下金属层130的湿法蚀刻工艺过程中上柱层156和下柱层152B在蚀刻剂中的蚀刻速度可以彼此基本上相同或相似，上柱层156和下柱层152B可以分别具有基本上相同的第一宽度W1和第三宽度W3(见图2)。此后，执行用于形成具有球体形状的焊料层160的回流工艺，然后可以执行附加蚀刻工艺。因为上柱层156的侧壁156S和顶表面由焊料层160覆盖，所以上柱层156在附加的蚀刻工艺中可以不被蚀刻。下柱层152B的侧壁可以暴露于在附加蚀刻工艺中使用的蚀刻剂中，并且可以被去除预定的宽度。因此，如图5中所示，下柱层152B的第三宽度W3B可以比上柱层156的第一宽度W1小。
图6是根据示例实施例的半导体芯片100D的剖视图。在图6中，与图1至图5中的附图标记相同的附图标记表示相同的元件。参照图6，导电焊盘122A可以形成在半导体基底110上，可以形成具有使导电焊盘122A的顶表面的一部分暴露的开口124H的钝化层124A。
再分布层192可以形成在导电焊盘122A和钝化层124A上。再分布层192可以覆盖开口124H的侧壁和底部并且可以延伸为设置在钝化层124A之上。再分布层192可以包括Cu、Al、W、Ni、Ti、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、Au或它们的组合。
具有使再分布层192的顶表面的一部分暴露的开口194H的再分布绝缘层194可以设置在再分布层192上。再分布绝缘层194可以包括光敏聚酰亚胺、氮化硅、氧化硅、氮氧化硅或它们的组合。
下金属层130可以形成在再分布绝缘层194上。下金属层130可以覆盖再分布绝缘层194的开口194H的侧壁和底部并且可以电连接到再分布层192。连接端子140可以设置在下金属层130上并且可以包括导电柱结构150和焊料层160。下金属层130、导电柱结构150和焊料层160具有与参照图2描述的技术特征相似的技术特征。另外，下金属层130可以由图3中的下金属层130A替代，连接端子140可以由图4中的连接端子140A和和图5中的连接端子140B替代。
根据半导体芯片100D，连接端子140可以设置在电连接到导电焊盘122A的再分布层192上。因此，即使当导电焊盘122A在具有微间距的半导体芯片100D中具有微间距时，连接端子140也可以在再分布层192上设置成具有相对大的间距。另外，再分布层192的布局可以独立于导电焊盘122A的布局。因此，半导体芯片100D可以具有改善的灵活性。
图7至图13是用于解释根据示例实施例的制造半导体芯片的方法的剖视图。图7至图13是用于解释制造图2的半导体芯片100的方法的剖视图。在图7至图13中，与图1至图6中的附图标记相同的附图标记表示相同的元件。参照图7，可以在半导体基底110上形成导电层(未示出)，然后可以通过将导电层图案化来在半导体基底110上形成导电焊盘122。可以根据半导体芯片的间距以预定的间隔设置多个导电焊盘122。
可以在导电焊盘122和半导体基底110上形成绝缘层(未示出)，然后可以通过将绝缘层图案化来形成其内具有使导电焊盘122的顶表面的一部分暴露的开口124H的钝化层124。
参照图8，可以在导电焊盘122的通过开口124H暴露的顶表面上和钝化层124的顶表面上形成初始下金属层130P。在示例实施例中，可以通过使用溅射工艺或化学气相沉积(CVD)工艺来形成初始下金属层130P。初始下金属层130P可以形成为与开口124H的侧壁和底部共形，因此可以不完全填充开口124H。
虽然初始下金属层130P在图8中是一个层，但是初始下金属层130P可以具有包括多层金属层的堆叠结构。例如，初始下金属层130P可以包括第一金属层至第三金属层，第一金属层至第三金属层中的每层可以分别作为粘附层、阻挡层、种子层或润湿层。初始下金属层130P的技术特征与参照图2描述的下金属层130的技术特征相似。
接着，可以在初始下金属层130P上形成具有开口310H的掩模层310。掩模层310可以是光致抗蚀剂图案。
开口310H可以形成为与导电焊盘122竖直地叠置。开口310H可以具有诸如圆柱形形状、矩形棱柱形形状或多棱柱形状的各种形状的任何形状。开口310H的水平宽度可以与扩散阻挡层154的第二宽度W2(见图2)基本上相同，但不限于此。
参照图9，可以通过在开口310H中顺序地形成下柱层152、扩散阻挡层154和上柱层156来形成导电柱结构150。上柱层156的顶表面可以在比掩模层310的顶表面低的水平处，因此可以不完全地填充开口310H。
在示例实施例中，可以通过使用第一电镀工艺来形成具有从开口310H的底部起的预定高度的下柱层152，可以通过使用第二电镀工艺在下柱层152上形成具有预定高度的扩散阻挡层154，可以通过使用第三电镀工艺在扩散阻挡层154上形成上柱层156。
在其它示例实施例中，可以通过使用第一电镀工艺来形成具有从开口310H的底部起的预定高度的下柱层152，可以通过使用溅射工艺在下柱层152上形成具有预定高度的扩散阻挡层154，可以通过使用第二电镀工艺在扩散阻挡层154上形成上柱层156。
在示例实施例中，下柱层152可以包括Ni、Cu、Pd、Pt、Au或它们的组合。扩散阻挡层154可以形成在下柱层152上。扩散阻挡层154可以包括Ni、Co、Cu或它们的组合。上柱层156可以包括Ni、Cu、Pd、Pt、Au或它们的组合。在示例实施例中，下柱层152和/或上柱层156可以包括具有相对于扩散阻挡层154的蚀刻选择性的材料。例如，下柱层152和上柱层156可以由Cu形成而扩散阻挡层154可以由Ni形成。然而，发明构思不限于此。
参照图10，可以在掩模层310的开口310H中的上柱层156上形成初始焊料层160P。在示例实施例中，初始焊料层160P可以通过使用电镀工艺形成。初始焊料层160P可以包括Sn、In、Bi、Sb、Cu、Ag、Zn、Pb和/或它们的合金。在示例实施例中，初始焊料层160P可以包括具有相对于下柱层152和/或上柱层156的蚀刻选择性的材料。
初始焊料层160P的形状可以根据掩模层310的高度或初始焊料层160P的体积而改变。在图10中，初始焊料层160P的顶表面基本上处于与掩模层310的顶表面的水平相同的水平。在这种情况下，初始焊料层160P可以呈具有平坦的顶表面的圆盘形形状，但不限于此。与图10中不同，初始焊料层160P的顶表面可以处于比掩模层310的顶表面的水平高的水平并且初始焊料层160P可以具有蘑菇形形状，或者初始焊料层160P的顶表面可以处于比掩模层310的顶表面的水平低的水平。
参照图11，可以去除掩模层310(见图10)。用于去除掩模层310的示例工艺可以是灰化工艺。当去除掩模层310时，可以使初始下金属层130P的顶表面和导电柱结构150的侧壁暴露。
参照图12，可以通过去除初始下金属层130P的未被初始焊料层160P和导电柱结构150覆盖的(见图11)的一部分来形成下金属层130。
在示例实施例中，用于去除初始下金属层130P的一部分的工艺可以是湿法蚀刻工艺。下柱层152和上柱层156的暴露于在湿法蚀刻工艺中使用的蚀刻剂的侧壁也可以均被去除按预定的宽度。
在示例实施例中，上柱层156和下柱层152可以均包括相对于扩散阻挡层154具有蚀刻选择性的材料。在这种情况下，上柱层156和下柱层152的暴露的侧壁均可以被蚀刻预定的宽度，而扩散阻挡层154暴露的侧壁几乎不被蚀刻，因此可以在导电柱结构150的侧壁上形成突出150O。可选地，虽然上柱层156、扩散阻挡层154和下柱层152都可以被蚀刻剂去除预定的宽度，但扩散阻挡层154的被去除的量比上柱层156和下柱层152的被去除的量少，因此可以在导电柱结构150的侧壁上形成突出150O。
因为在蚀刻工艺中上柱层156和下柱层152的暴露的侧壁比扩散阻挡层154的侧壁更向内设置，所以突出150O可以由扩散阻挡层154的边缘顶表面154U、侧壁154S和边缘底表面154L来限定。
初始焊料层160P可以包括但不限于相对于上柱层156和下柱层152具有蚀刻选择性的材料。因为下柱层152的侧壁凹进预定的宽度，所以下金属层130的设置在被移除部分下的一部分也可以暴露于蚀刻剂，因此也可以被去除。因此，如图12中所示，下金属层130的侧壁可以与下柱层152的侧壁对齐。
为了制造图5的半导体芯片100C，下柱层152B和上柱层156可以包括不同的材料，并且包括在下柱层152B和上柱层156的材料在蚀刻剂中的蚀刻速度可以彼此不同。具体地，当包括在下柱层152B中的材料的蚀刻速度比包括在上柱层156中的材料的蚀刻速度高时，下柱层152B的侧壁可以比上柱层156的侧壁更向内设置。在这种情况下，可以制造出图5的半导体芯片100C。
参照图13，可以通过回流工艺形成具有球形形状或球体形状的焊料层160。
在示例实施例中，当初始焊料层160P(见图12)在比初始焊料层160P的熔点低的温度下(例如，在从大约220℃至大约250℃的范围的温度下)回流时，初始焊料层160P可以变为液态。由于处于液态的初始焊料层160P的表面张力，使得可以形成具有球形形状或球体形状的焊料层160。包括在导电柱结构150中的材料在回流工艺中不会变为液态，并且可以保持导电柱结构150的形状。
在示例实施例中，焊料层160可以沿着导电柱结构150的侧壁向下流动，并且可以接触扩散阻挡层154的边缘顶表面154U。因此，焊料层160可以覆盖上柱层156的整个侧壁和整个顶表面，并且可以基本上覆盖扩散阻挡层154的边缘顶表面154U的整个区域。然而，焊料层160可以不形成在扩散阻挡层154的侧壁154S上。
在示例实施例中，可以在回流工艺过程中在导电柱结构150和焊料层160之间的接触界面上形成中间层160I。中间层160I可以包括通过包括在导电柱结构150中的材料与包括在焊料层160中的材料之间的反应形成的IMC。
可以通过执行以上工艺来制造半导体芯片100。
根据制造半导体芯片100的方法，可以形成在其侧壁上包括突出150O的导电柱结构150，设置在导电柱结构150上的焊料层160的量(或高度)可以增大。导电柱结构150的突出150O可以防止焊料层160沿侧壁向下流动。因此。半导体芯片100可以提供可靠的电连接。另外，因为当形成下金属层130时可以在导电柱结构150的侧壁上形成突出150O，所以可以简化制造半导体芯片100的工艺。
图14是用于解释根据示例实施例的制造半导体芯片的方法的剖视图。图14可以是用于解释制造图3的半导体芯片100A的方法的剖视图。在图14中，与图1至图13中的附图标记相同的附图标记表示相同的元件。
首先，可以通过执行以上图7至图11的工艺来将导电柱结构150和初始焊料层160P顺序地堆叠在初始下金属层130P上。
参照图14，可以通过去除初始下金属层130P的未被初始焊料层160P和导电柱结构150覆盖的一部分来形成下金属层130A。
包括在下金属层130A中的材料在蚀刻剂中的蚀刻速度可以比包括在下柱层152中的材料在蚀刻剂中的蚀刻速度高。在这种情况下，可以进一步蚀刻下金属层130A的侧壁的暴露部分，因此可以在下金属层130A周围形成底切130R。可以比下柱层152的侧壁更向内地设置下金属层130A。
接着，可以通过执行以上图13的工艺来制造半导体芯片100A。
图15至图18是用于解释根据示例实施例的制造半导体芯片的方法的剖视图。图15至图18可以是用于解释制造图4的半导体芯片100B的方法的剖视图。在图15至图18中，与图1至图14中的附图标记相同的附图标记表示相同的元件。
首先，可以通过执行以上图7和图8的工艺在半导体基底110上形成导电焊盘122、钝化层124和初始下金属层130P。
参照图15，可以在初始下金属层130P上形成具有开口320H的掩模层320。在这种情况下，掩模层320的高度可以比图8中的掩模层310的高度大。
可以通过执行以上图9和图10的工艺在掩模层320的开口320H中顺序地堆叠导电柱结构150A和初始焊料层160P。
导电柱结构150A可以包括顺序地堆叠的下柱层152A、扩散阻挡层154和上柱层156A。在示例实施例中，可以均通过使用相对于扩散阻挡层154具有蚀刻选择性的材料来形成下柱层152A和上柱层156A。另外，可以均通过使用相对于初始焊料层160P具有蚀刻选择性的材料来形成下柱层152A和上柱层156A。在示例实施例中，上柱层156A的第一高度H1A可以比扩散阻挡层154的第二高度H2大，并且下柱层152A的第三高度H3A可以比扩散阻挡层154的第二高度H2大。
参照图16，可以通过去除初始下金属层130P(见图15)的未被初始焊料层160P和导电柱结构150A覆盖的一部分来形成下金属层130。
在这种情况下，上柱层156A和下柱层152A的侧壁可以暴露于在用于形成下金属层130的蚀刻工艺中使用的蚀刻剂，因此可以被去除预定的宽度。扩散阻挡层154和初始焊料层160P的侧壁可以几乎不通过蚀刻剂去除或者可以按比上柱层156A和下柱层152A的去除宽度小得多的宽度来去除。因此，可以在导电柱结构150A的侧壁上形成突出150O。
参照图17，下柱层152A和上柱层156A的侧壁均可以被去除预定的宽度。
在示例实施例中，去除下柱层152A和上柱层156A的侧壁的工艺可以是湿法蚀刻工艺。扩散阻挡层154和初始焊料层160P可以包括相对于下柱层152A和上柱层156A具有蚀刻选择性的材料，因此可以在湿法蚀刻工艺中几乎不被去除。
在示例实施例中，上柱层156A的第一宽度W1A可以在扩散阻挡层154的第二宽度W2的大约30％至大约80％的范围。另外，下柱层152A的第三宽度W3A可以在扩散阻挡层154的第二宽度W2的大约30％至大约80％的范围。
参照图18，可以通过利用回流工艺来形成具有球形形状或球体形状的焊料层160A。
在示例实施例中，在回流工艺中，焊料层160A可以沿着上柱层156A的侧壁向下流动并且可以接触扩散阻挡层154的边缘顶表面154U。因此，焊料层160A可以覆盖上柱层156A的整个侧壁和整个顶表面，并且可以基本上覆盖扩散阻挡层154的边缘顶表面154U的整个区域。然而，焊料层160A可以不形成在扩散阻挡层154的侧壁154S上。
可以通过执行以上工艺来制造半导体芯片100B。
图19是用于解释根据示例实施例的制造半导体芯片的方法的剖视图。图19可以是用于解释制造图5的半导体芯片100C的方法的剖视图。在图19中，与图1至图18中的附图标记相同的附图标记表示相同的元件。
首先，可以通过执行以上图7至图13的工艺在导电柱结构150B上形成焊料层160。
参照图19，下柱层152B的侧壁可以被去除预定的宽度。
在示例实施例中，扩散阻挡层154可以包括具有相对于下柱层152B的蚀刻选择性的材料，扩散阻挡层154的侧壁在用于去除下柱层152B的侧壁的蚀刻工艺中可以几乎不被去除。另外，因为上柱层156的整个侧壁和整个顶表面由焊料层160覆盖，所以在蚀刻工艺中可以不损伤上柱层156。因此，下柱层152B的宽度W3B可以比上柱层156的第一宽度W1小。
可以通过执行以上工艺来制造半导体芯片100C。
图20至图23是用于解释根据示例实施例的制造半导体芯片的方法的剖视图。图20至图23可以是用于解释制造图6的半导体芯片100D的方法的剖视图。在图20至图23中，与图1至图19中的附图标记相同的附图标记表示相同的元件。参照图20，可以在半导体基底110上形成导电焊盘122A，可以在导电焊盘122A上形成钝化层124A。钝化层124A可以具有开口124H，开口124H可以暴露导电焊盘122A的顶表面的一部分。
可以在导电焊盘122A和钝化层124A上形成导电层(未示出)，然后可以通过将导电层图案化来形成电连接到导电焊盘122A的再分布层192。再分布层192可以覆盖开口124H的侧壁和底部并且可以延伸成设置在钝化层124A之上。
参照图21，可以形成覆盖钝化层124A和再分布层192的绝缘层(未示出)，可以通过对绝缘层执行图案化工艺来形成具有使再分布层192的顶表面的一部分暴露的开口194H的再分布绝缘层194。在示例实施例中，再分布绝缘层194可以通过使用光敏聚酰亚胺、氮化硅、氧化硅或氮氧化硅来形成。
接着，可以在再分布绝缘层194上形成初始下金属层130P。初始下金属层130P可以覆盖再分布绝缘层194的开口194H的侧壁和底部并且可以电连接到再分布层192。
参照图22，可以在再分布层192上形成具有开口330H的掩模层330。开口330H可以形成为与再分布绝缘层194的开口194H竖直地叠置。因此，可以通过掩模层330的开口330H暴露初始下金属层130P的与再分布层192接触的一部分。
接着，可以在开口330H中顺序地形成下柱层152、扩散阻挡层154、上柱层156和初始焊料层160P。
参照图23，可以去除掩模层330(见图22)，可以通过去除初始下金属层130P的未被初始焊料层160P和导电柱结构150覆盖的一部分来形成下金属层130。在这种情况下，在去除初始下金属层130P的所述一部分的工艺中下柱层152和上柱层156的暴露于蚀刻剂的侧壁均可以被去除预定的宽度。如图23中所示，上柱层156的侧壁156S可以比扩散阻挡层154的侧壁154S更向内设置，扩散阻挡层154的边缘顶表面154U可以被暴露。
返回参照图6，可以通过执行回流工艺来形成具有球形形状或球体形状的焊料层160。
可以通过执行以上工艺来制造半导体芯片100D。
图24是用于解释根据示例实施例的制造半导体器件1的方法的剖视图。在图24中，与图1至图23中的附图标记相同的附图标记表示相同的元件。
首先，可以通过执行以上图7至图13的工艺来形成半导体芯片100。半导体芯片100可以包括具有在导电柱结构150的侧壁上的突出150O的导电柱结构150和设置在导电柱结构150上的焊料层160。
虽然图24中未示出，但助焊剂(未示出)可以形成在焊料层160和导电柱结构150的一部分上。为了防止诸如焊料层160的氧化的不期望的反应，助焊剂可以在焊料层160的表面上形成为小厚度。在示例实施例中，助焊剂可以包括氯化物、氟化物或树脂并且可以通过利用涂覆来形成。
接着，可以在基础基底210的一个表面上设置包括连接焊盘220和使连接焊盘220的一部分暴露的绝缘层230的封装基底200。
半导体芯片100可以通过利用倒装键合来安装在封装基底200上。半导体芯片100的第一表面F1可以面对封装基底200，使得焊料层160接触连接焊盘220。在示例实施例中，可以在为了使焊料层160的一部分熔化的足够高的温度下执行用于将焊料层160附着到连接焊盘220的工艺。如图24中所示，突出150O可以形成在导电柱结构150的侧壁上，因此焊料层160不会沿导电柱结构150的侧壁向下流动，并且焊料层160不会与下柱层152的侧壁接触。
为了对比发明构思，在图24中以虚线示出了在包括导电柱结构(在侧壁上不包括突出)的半导体芯片中的焊料层的轮廓B。当焊料层设置于在侧壁上不包括突出的导电柱结构上时，焊料层会在焊料层的回流工艺和/或用于将焊料层附着到连接焊盘的工艺中沿导电柱结构的侧壁向下流动。因此，焊料层会覆盖下柱层的侧壁的一部分并且IMC会通过包括在焊料层和下柱层中的金属材料之间的反应来形成。当IMC形成时，可以有助于半导体芯片和连接焊盘之间的可靠电连接的焊料层的体积会减小。另外，空隙会形成在焊料层中，并且当半导体芯片长时间使用时，半导体芯片的可靠性会由于空隙而降低。
然而，如图24中所示，当突出150O形成在导电柱结构150的侧壁上时，可以防止焊料层160沿导电柱结构150的侧壁向下流动，因此连接端子140可以提供可靠的电连接。
返回参照图1，可以在半导体芯片100和封装基底200之间形成围绕连接端子140的侧壁的底部填充层170。接着，可以形成围绕半导体芯片100的顶表面和侧壁的成型材料180。成型材料180可以通过利用环氧成型化合物(EMC)等来形成。接着，可以在封装基底200的另一表面上形成外部端子连接焊盘240和附着到外部端子连接焊盘240的外部端子250。然而，可以在图24的附着半导体芯片100的工艺之前执行形成外部端子连接焊盘240和/或外部端子250的工艺。
因此，如上文中所述，提供了一种电子器件(例如，半导体器件)，所述电子器件包括其上具有电气导电的接触焊盘122和在接触焊盘122上的电气导电的连接端子140的基底110。连接端子140包括电气导电的柱结构150和在柱结构150上延伸并且与柱结构150的侧壁的突出部分接触的焊料层160。在发明的这些实施例的一些中，柱结构150包括下柱层152、在下柱层152上的扩散阻挡层154和在扩散阻挡层154上的上柱层156。柱结构150的侧壁的突出部分包括扩散阻挡层154的上表面(154U)的最外侧部分。这可通过使在横向剖面观察时扩散阻挡层154的宽度大于上柱层156的宽度来获得，使得焊料层160在执行回流工艺之后直接接触扩散阻挡层154的上表面(154U)的最外侧部分。
如前所描述和所示出的，将扩散阻挡层154的上表面(154U)构造为与上柱层156的底表面直接接触。当在横向剖面观察时，扩散阻挡层154的宽度也可以大于下柱层154的宽度。基于这样的构造，当在垂直于扩散阻挡层154的上表面的方向观察时，扩散阻挡层154的上表面(154U)的最外侧部分将是环/环形形状(例如，圆环、矩形环等)。此外，焊料层160可以与上柱层156的上表面和扩散阻挡层154的上表面(154U)的整个环形形状部分直接接触。上柱层156和扩散阻挡层154可以构造为相对于焊料具有不同回流特性的材料。
如前所述，如从上柱层156的上表面测量的焊料层160的高度在扩散阻挡层154的宽度的大约50％至大约90％的范围。上柱层156的宽度也可以在扩散阻挡层154的宽度的大约80％至大约98％的范围。类似地，当在横向剖面观察时，扩散阻挡层154的宽度可以比下柱层152的宽度大，下柱层152的宽度可以在扩散阻挡层154的宽度的大约80％至大约98％的范围。
如上进一步所示(例如，图2)，钝化层124设置在基底110上。钝化层124其内可以具有使接触焊盘122的上表面暴露的开口。如图2至图3所示，该开口可以内衬有下金属层130并且下柱层的侧壁可以相对于下金属层130(130A)的侧壁对齐(或凹进)。
另外，如图11至图13所示，例如，形成电子器件的方法包括形成下柱层152、在下柱层152上的扩散阻挡层154和在扩散阻挡层154上的上柱层156的组合件。如图12所示，焊料层160P也可以在使上柱层156的侧壁相对于焊料层160P和扩散阻挡层154的侧壁凹进之前形成在上柱层156上。然后，如图13所示，该凹进步骤之后是使焊料层160回流到上柱层156的凹进的侧壁上和扩散阻挡层154的环形形状上表面上。
虽然已经参照发明构思的示例实施例具体地示出和描述了发明构思，但将理解的是，在不脱离权利要求的精神和范围的情况下，可以在此做各种形式上和细节上的改变。

Claims (20)

1.一种电子器件，所述电子器件包括：
基底，所述基底上具有电气导电的接触焊盘；以及
电气导电的连接端子，位于所述接触焊盘上，所述连接端子包括电气导电的柱结构和在所述柱结构上延伸并且与柱结构的侧壁的突出部分接触的焊料层，所述柱结构包括下柱层、位于下柱层上的扩散阻挡层和位于扩散阻挡层上的上柱层。
2.根据权利要求1所述的电子器件，其中，柱结构的侧壁的突出部分包括扩散阻挡层的上表面的最外侧部分。
3.根据权利要求1所述的电子器件，其中，当在横向剖面观察时，扩散阻挡层的宽度比上柱层的宽度大。
4.根据权利要求3所述的电子器件，其中，扩散阻挡层的上表面与上柱层的底表面直接接触。
5.根据权利要求3所述的电子器件，其中，当在横向剖面观察时，扩散阻挡层的宽度比下柱层的宽度大。
6.根据权利要求2所述的电子器件，其中，焊料层与扩散阻挡层的上表面的最外侧部分直接接触。
7.根据权利要求6所述的电子器件，其中，当在与扩散阻挡层的上表面垂直的方向上观察时，扩散阻挡层的上表面的最外侧部分是环状的。
8.根据权利要求1所述的电子器件，其中，焊料层与上柱层的上表面和扩散阻挡层的上表面的整个环状部分直接接触。
9.根据权利要求8所述的电子器件，其中，上柱层和扩散阻挡层包括不同的材料。
10.根据权利要求3所述的电子器件，其中，按从上柱层的上表面测量的焊料层的高度在扩散阻挡层的宽度的50％至90％的范围内。
11.根据权利要求3所述的电子器件，其中，上柱层的宽度在扩散阻挡层的宽度的80％至98％的范围内。
12.根据权利要求1所述的电子器件，其中，当在横向剖面观察时，扩散阻挡层的宽度比下柱层的宽度大；其中，下柱层的宽度在扩散阻挡层的宽度的80％至98％的范围内。
13.根据权利要求3所述的电子器件，其中，上柱层的宽度是在扩散阻挡层的宽度的30％至80％的范围内。
14.根据权利要求1所述的电子器件，其中，当在横向剖面观察时，下柱层的宽度比上柱层的宽度小。
15.根据权利要求1所述的电子器件，所述电子器件还包括位于所述基底上的钝化层，所述钝化层中具有使接触焊盘的上表面暴露的开口；其中，所述开口至少部分地内衬有下金属层；其中，下柱层的侧壁与下金属层的侧壁对齐。
16.根据权利要求1所述的电子器件，所述电子器件还包括位于所述基底上的钝化层，所述钝化层中具有使接触焊盘的上表面暴露的开口；其中，所述开口至少部分地内衬有下金属层；其中，下金属层的侧壁相对于下柱层的侧壁凹进。
17.一种半导体器件，所述半导体器件包括：
导电焊盘，设置在基底上；以及
连接端子，电连接到导电焊盘，连接端子包括：
导电柱结构，包括顺序堆叠的下柱层、扩散阻挡层和上柱层，导电柱结构还包括位于导电柱结构的侧壁上的突出；和
焊料层，设置在上柱层上并且与突出的至少一部分接触。
18.根据权利要求17所述的半导体器件，其中，上柱层的在与基底的顶表面平行的第一方向上的第一宽度比扩散阻挡层的在第一方向上的第二宽度小。
19.根据权利要求17所述的半导体器件，其中，焊料层与扩散阻挡层的顶表面的至少一部分接触。
20.根据权利要求17所述的半导体器件，其中，突出是由扩散阻挡层的比上柱层的侧壁更向外突出的侧壁形成的。
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